CypressメーカーCY7C1422BV18の使用説明書/サービス説明書
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36-Mbit DDR-II SIO SRAM 2-W ord Burst Architecture CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18 Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document #: 001-07035 Rev .
CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18 Document #: 001-07035 Rev . *D Page 2 of 30 Logic Block Diagram (CY7C1422BV18) Logic Block Diagram (CY7C1429BV18) 2M x 8 Array CLK A (20:0) Gen. K K Control Logic Address Register D [7:0] Read Add.
CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18 Document #: 001-07035 Rev . *D Page 3 of 30 Logic Block Diagram (CY7C1423BV18) Logic Block Diagram (CY7C1424BV18) 1M x 18 Array CLK A (19:0) Gen. K K Control Logic Address Register D [17:0] Read Add.
CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18 Document #: 001-07035 Rev . *D Page 4 of 30 Pin Configuration The pin configuration for CY7C1422BV18, CY7C1429 BV18, CY7C1423BV18, and CY7C1424BV18 follow .
CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18 Document #: 001-07035 Rev . *D Page 5 of 30 CY7C1423BV18 (2M x 18) 123456789 10 11 A CQ NC/144M A R/W BWS 1 K NC/28 8M LD A NC/72M CQ B NC Q9 D9 A.
CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18 Document #: 001-07035 Rev . *D Page 6 of 30 Pin Definitions Pin Name IO Pin Descripti on D [x:0] Input- Synchronous Data Input Signals. Sampled on the rising edge of K and K clocks during val id write opera tions.
CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18 Document #: 001-07035 Rev . *D Page 7 of 30 CQ Echo Clock CQ Referenced with Respect to C . This is a free-running clock and is synchronized to the input clock for output data (C) of the DDR-II. In the single clock mode, CQ is generated with respect to K.
CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18 Document #: 001-07035 Rev . *D Page 8 of 30 Functional Overview The CY7C1422BV18, CY7C1429BV18, CY7C1423 BV18, and CY7C1424BV18 are synchronous pi.
CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18 Document #: 001-07035 Rev . *D Page 9 of 30 Echo Clocks Echo clocks are provided on the DDR- II to simplify data capture on high-speed systems. T wo echo clocks ar e generated by the DDR-II. CQ is referenced with respect to C and CQ is referenced with respect to C .
CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18 Document #: 001-07035 Rev . *D Page 10 of 30 T ruth T able The truth table for CY7C1422BV18, CY7C1429BV 18, CY7C1423BV18, and CY7C1424BV18 follo ws. [2, 3, 4, 5, 6, 7] Operation K LD R/W DQ DQ Write Cycle: Load address; wait one cycle; input write data on consecutive K and K rising edges.
CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18 Document #: 001-07035 Rev . *D Page 1 1 of 30 Write Cycle Descriptions The write cycle description tabl e for CY7C1429BV18 follows. [2, 8] BWS 0 K K Comments L L–H – During the Data portion of a write sequence, the single byte (D [8:0] ) is writ te n in to the device.
CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18 Document #: 001-07035 Rev . *D Page 12 of 30 IEEE 1 149.1 Serial Boundary Scan (JT AG) These SRAMs incorporate a serial boundary scan T est Access Port (T AP) in the FBGA p ackage. This part is fully comp liant with IEEE S tandard #1 149.
CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18 Document #: 001-07035 Rev . *D Page 13 of 30 IDCODE The IDCODE instruction loads a vendor-specific, 32-bi t code into the instruction re gister .
CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18 Document #: 001-07035 Rev . *D Page 14 of 30 T AP Controller St ate Diagram The state diagram for the T AP controller follows.
CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18 Document #: 001-07035 Rev . *D Page 15 of 30 T AP Controller Block Diagram T AP Electrical Characteristics Over the Operating Range [10, 1 1, 12] Parameter Description T est Conditions Min Max Unit V OH1 Output HIGH V oltage I OH = − 2.
CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18 Document #: 001-07035 Rev . *D Page 16 of 30 T AP AC Switching Characteristics Over the Operating Range [13, 14] Parameter Description Min Max Uni.
CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18 Document #: 001-07035 Rev . *D Page 17 of 30 Identification R egi ster Definitions Instruction Field Va l u e Description CY7C1422BV18 CY7C1429BV18 CY7 C1423BV18 CY7C1424BV18 Revision Numb er (31:29) 000 000 000 000 V ersion number .
CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18 Document #: 001-07035 Rev . *D Page 18 of 30 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bum p ID 0 6R 28 10G 56 6A 84 1J .
CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18 Document #: 001-07035 Rev . *D Page 19 of 30 Power Up Sequence in DDR-II SRAM DDR-II SRAMs must be power ed up and initialized in a predefined manner to prevent unde fined operation s. Power Up Sequence ■ Apply power and drive DO FF either HIGH or LOW (All other inputs can be HIGH or LOW).
CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18 Document #: 001-07035 Rev . *D Page 20 of 30 Maximum Ratings Exceeding maximum ratin gs may impair the useful life of the device. These user guidelines are not teste d. S torage T emperature ......
CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18 Document #: 001-07035 Rev . *D Page 21 of 30 I DD V DD Operating Supply V DD = Max, I OUT = 0 mA, f = f MAX = 1/t CYC 200MHz (x8) 600 mA (x9) 600 .
CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18 Document #: 001-07035 Rev . *D Page 22 of 30 Cap acit ance T ested initially and after any design or process change that may affect these parameters. Parameter Description T est Condit ions Max Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V DD = 1.
CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18 Document #: 001-07035 Rev . *D Page 23 of 30 Switching Characteristics Over the Operating Range [20, 21] Cypress Parameter Consor tium Parameter D.
CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18 Document #: 001-07035 Rev . *D Page 24 of 30 Output T imes t CO t CHQV C/C Clock Rise (or K/K in single clock mode) to Data V alid – 0.45 – 0.45 – 0.45 – 0.45 – 0.50 ns t DOH t CHQX Data Output Hold af ter Output C/C Clock Rise (Active to Active) –0.
CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18 Document #: 001-07035 Rev . *D Page 25 of 30 Switching W aveforms Figure 5. Read/Write/Deselect Sequence [2 7, 28, 29 ] K 123 4 5 6 7 8 K LD R/W A.
CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18 Document #: 001-07035 Rev . *D Page 26 of 30 Ordering Information Not all of the speed, package and temperature range s are ava ilable. Please contact your local sales representative or visit www .
CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18 Document #: 001-07035 Rev . *D Page 27 of 30 250 CY7C1422BV18-250BZC 51-85195 165-Ball F ine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Commercial CY7C1429BV18-250BZC CY7C1423BV18-250BZC CY7C1424BV18-250BZC CY7C1422BV18-250BZXC 51-85195 165-Ball Fine Pi tch Ball Grid Array (15 x 17 x 1.
CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18 Document #: 001-07035 Rev . *D Page 28 of 30 167 CY7C1422BV18-167BZC 51-85195 165-Ball F ine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Commercial CY7C1429BV18-167BZC CY7C1423BV18-167BZC CY7C1424BV18-167BZC CY7C1422BV18-167BZXC 51-85195 165-Ball Fine Pi tch Ball Grid Array (15 x 17 x 1.
CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18 Document #: 001-07035 Rev . *D Page 29 of 30 Package Diagram Figure 6. 165-ball FBGA (15 x 17 x 1.
Document #: 001-07035 Rev . *D Revised June 16, 2008 Page 30 of 30 QDR RAMs an d Quad Data Rate RAMs comp rise a new family of product s developed by Cypress, I DT , NEC, R enesas, and Sa msung. All pr oduct and comp any names mentioned i n this documen t are the tr ad emarks of their resp ectiv e ho lders.
デバイスCypress CY7C1422BV18の購入後に（又は購入する前であっても）重要なポイントは、説明書をよく読むことです。その単純な理由はいくつかあります：
Cypress CY7C1422BV18をまだ購入していないなら、この製品の基本情報を理解する良い機会です。まずは上にある説明書の最初のページをご覧ください。そこにはCypress CY7C1422BV18の技術情報の概要が記載されているはずです。デバイスがあなたのニーズを満たすかどうかは、ここで確認しましょう。Cypress CY7C1422BV18の取扱説明書の次のページをよく読むことにより、製品の全機能やその取り扱いに関する情報を知ることができます。Cypress CY7C1422BV18で得られた情報は、きっとあなたの購入の決断を手助けしてくれることでしょう。
Cypress CY7C1422BV18を既にお持ちだが、まだ読んでいない場合は、上記の理由によりそれを行うべきです。そうすることにより機能を適切に使用しているか、又はCypress CY7C1422BV18の不適切な取り扱いによりその寿命を短くする危険を犯していないかどうかを知ることができます。
ですが、ユーザガイドが果たす重要な役割の一つは、Cypress CY7C1422BV18に関する問題の解決を支援することです。そこにはほとんどの場合、トラブルシューティング、すなわちCypress CY7C1422BV18デバイスで最もよく起こりうる故障・不良とそれらの対処法についてのアドバイスを見つけることができるはずです。たとえ問題を解決できなかった場合でも、説明書にはカスタマー・サービスセンター又は最寄りのサービスセンターへの問い合わせ先等、次の対処法についての指示があるはずです。
