CypressメーカーCY7C1512KV18の使用説明書/サービス説明書
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72-Mbit QDR™-II SRAM 2-W ord Burst Architecture CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1 709 • 408-943-2600 Document Number: 001-00436 Rev .
CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 Document Number: 001-00436 Rev . *E Page 2 of 30 Logic Block Diagram (CY7C1510KV18) Logic Block Diagram (CY7C1525KV18) 4M x 8 Array CLK A (21:0) Gen. K K Control Logic Address Register D [7:0] Read Add.
CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 Document Number: 001-00436 Rev . *E Page 3 of 30 Logic Block Diagram (CY7C1512KV18) Logic Block Diagram (CY7C1514KV18) 2M x 18 Array CLK A (20:0) Gen. K K Control Logic Address Register D [17:0] Read Add.
CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 Document Number: 001-00436 Rev . *E Page 4 of 30 Pin Configuration The pin configurations for CY7C1510KV18, CY7C 1525 KV18, CY7C1512KV18, and CY7C1514KV18 fo llow . [1] 165-Ball FBGA (13 x 15 x 1 .
CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 Document Number: 001-00436 Rev . *E Page 5 of 30 CY7C1512KV18 (4M x 18) 123456789 10 11 A CQ NC/144M A WPS BWS 1 K NC/288M RPS AA C Q B NC Q9 D9 A.
CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 Document Number: 001-00436 Rev . *E Page 6 of 30 Pin Definitions Pin Name I/O Pin Description D [x:0] Input- Synchronous Data Input Signals . Sampled on the rising edge of K and K clocks during valid write operations.
CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 Document Number: 001-00436 Rev . *E Page 7 of 30 CQ Echo Clock CQ Referenced with Respect to C . This is a free running clock and is synchronized to the input clock for output data (C) of the QDR-II.
CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 Document Number: 001-00436 Rev . *E Page 8 of 30 Functional Overview The CY7C1510KV18, CY7C1525KV18, CY7C1512 KV18, and CY7C1514KV18 are synchronous pipelin ed Burst SRAMs with a read port and a write port.
CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 Document Number: 001-00436 Rev . *E Page 9 of 30 Echo Clocks Echo clocks are provided on the QD R-II to simplify data capture on high speed systems. T wo echo clocks are generated by the QDR-II. CQ is referenced with respect to C and CQ is referenced with respect to C .
CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 Document Number: 001-00436 Rev . *E Page 10 of 30 T ruth T able The truth table for CY7C1510KV18, CY7C1525KV18, CY7C1512KV18, and CY7C1514KV18 follow . [2, 3, 4, 5, 6, 7] Operation K RPS WPS DQ DQ Write Cycle: Load address on the rising ed ge of K ; input write data on K and K rising edges.
CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 Document Number: 001-00436 Rev . *E Page 1 1 of 30 Write Cycle Descriptions The write cycle description t able for CY7C1525KV18 follow . [2, 8] BWS 0 K K L L–H – During the data portion of a write sequence, the single b yte (D [8:0] ) is written into the device.
CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 Document Number: 001-00436 Rev . *E Page 12 of 30 IEEE 1 149.1 Serial Boundary Scan (JT AG) These SRAMs incorporate a serial boundary scan T est Access Port (T AP) in the FBGA package. This part is fully complia nt with IEEE S tandard #1 149.
CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 Document Number: 001-00436 Rev . *E Page 13 of 30 IDCODE The IDCODE instruction loads a vendor-specific, 32-bi t code into the instruction re gister .
CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 Document Number: 001-00436 Rev . *E Page 14 of 30 T AP Controller St ate Diag ram The state diagram for the T AP controller follows.
CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 Document Number: 001-00436 Rev . *E Page 15 of 30 T AP Controller Block Diagram T AP Electrical Characteristics Over the Operating Range [10, 1 1 , 12] Parameter Description T est Conditions Min Max Unit V OH1 Output HIGH V o ltage I OH = − 2.
CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 Document Number: 001-00436 Rev . *E Page 16 of 30 T AP AC Switching Characteristics Over the Operating Range [13, 14] Parameter Description Min Ma.
CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 Document Number: 001-00436 Rev . *E Page 17 of 30 Identification R egi ster Definitions Instruction Field Va l u e Description CY7C1510KV18 CY7C1525KV18 CY7 C1512KV18 CY7C1514KV18 Revision Numb er (31:29) 000 000 000 000 V ersion number .
CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 Document Number: 001-00436 Rev . *E Page 18 of 30 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bum p ID 0 6R 28 10G 56 6A 8.
CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 Document Number: 001-00436 Rev . *E Page 19 of 30 Power Up Sequence in QDR-II SRAM QDR-II SRAMs must be powered up and initialized in a predefined manner to prevent unde fined operation s. Power Up Sequence ■ Apply power and drive DOFF either HIGH or LOW (All other inputs can be HIGH or LOW).
CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 Document Number: 001-00436 Rev . *E Page 20 of 30 Maximum Ratings Exceeding maximum ratin gs may impair the useful life of the device. These user guidelines are not teste d. S torage T emperat ure .
CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 Document Number: 001-00436 Rev . *E Page 21 of 30 I DD [19] V DD Operating Supply V DD = Max, I OUT = 0 mA, f = f MAX = 1/t CYC 200 MHz (x8) 540 m.
CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 Document Number: 001-00436 Rev . *E Page 22 of 30 Cap acit ance T ested initially and after any design or process change that may affect these parameters. Parameter Description T est Conditions Max Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V DD = 1.
CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 Document Number: 001-00436 Rev . *E Page 23 of 30 Switching Characteristics Over the Operating Range [20, 21] Cypress Parameter Consorti um Parame.
CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 Document Number: 001-00436 Rev . *E Page 24 of 30 Output T imes t CO t CHQV C/C Clock Rise (or K/K in single clock mode) to Data V alid – 0.45 – 0.45 – 0.45 – 0.45 – 0.50 ns t DOH t CHQX Data Output Hold af ter Output C/C Clock Rise (Active to Active) –0.
CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 Document Number: 001-00436 Rev . *E Page 25 of 30 Switching W aveforms Figure 5. Read/Write/Deselect Sequence [2 6, 27, 28] K 1 2 34 5 8 10 6 7 K .
CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 Document Number: 001-00436 Rev . *E Page 26 of 30 Ordering Information The following table lists all possible speed, package, and temperat ure range options supported for these devi ces. Note that som e options listed may not be availabl e for order entry .
CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 Document Number: 001-00436 Rev . *E Page 27 of 30 250 CY7C1510KV18-250BZC 51-85180 165-Ball Fine Pi tch Ball Grid Array (13 x 15 x 1.4 mm) Commercial CY7C1525KV18-250BZC CY7C1512KV18-250BZC CY7C1514KV18-250BZC CY7C1510KV18-250BZXC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.
CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 Document Number: 001-00436 Rev . *E Page 28 of 30 167 CY7C1510KV18-167BZC 51-85180 165-Ball Fine Pi tch Ball Grid Array (13 x 15 x 1.4 mm) Commercial CY7C1525KV18-167BZC CY7C1512KV18-167BZC CY7C1514KV18-167BZC CY7C1510KV18-167BZXC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.
CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 Document Number: 001-00436 Rev . *E Page 29 of 30 Package Diagram Figure 6. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180 A 1 PIN 1 CORNER 15.00±0.10 13.00±0.10 7.00 1.00 Ø0.50 (165X) Ø 0 . 2 5MCAB Ø0.
Document Number: 001-00436 Rev . *E Revised March 30, 2009 Page 30 of 30 QDR RAMs an d Quad Data Rate RAMs comp rise a new family of product s develope d by Cypress, IDT , NEC, Renesas, and Samsung. A ll pr oduct an d company n ames mentione d in this do cument are the tr ademark s of their re specti ve holders .
デバイスCypress CY7C1512KV18の購入後に（又は購入する前であっても）重要なポイントは、説明書をよく読むことです。その単純な理由はいくつかあります：
Cypress CY7C1512KV18をまだ購入していないなら、この製品の基本情報を理解する良い機会です。まずは上にある説明書の最初のページをご覧ください。そこにはCypress CY7C1512KV18の技術情報の概要が記載されているはずです。デバイスがあなたのニーズを満たすかどうかは、ここで確認しましょう。Cypress CY7C1512KV18の取扱説明書の次のページをよく読むことにより、製品の全機能やその取り扱いに関する情報を知ることができます。Cypress CY7C1512KV18で得られた情報は、きっとあなたの購入の決断を手助けしてくれることでしょう。
Cypress CY7C1512KV18を既にお持ちだが、まだ読んでいない場合は、上記の理由によりそれを行うべきです。そうすることにより機能を適切に使用しているか、又はCypress CY7C1512KV18の不適切な取り扱いによりその寿命を短くする危険を犯していないかどうかを知ることができます。
ですが、ユーザガイドが果たす重要な役割の一つは、Cypress CY7C1512KV18に関する問題の解決を支援することです。そこにはほとんどの場合、トラブルシューティング、すなわちCypress CY7C1512KV18デバイスで最もよく起こりうる故障・不良とそれらの対処法についてのアドバイスを見つけることができるはずです。たとえ問題を解決できなかった場合でも、説明書にはカスタマー・サービスセンター又は最寄りのサービスセンターへの問い合わせ先等、次の対処法についての指示があるはずです。
