CypressメーカーCY7C68015Aの使用説明書/サービス説明書
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CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A EZ-USB FX2LP™ USB Microcontroller High-S peed USB Peripheral Controller Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document #: 38-08032 Rev . *L Revised February 8, 2008 1.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document #: 38-08032 Rev . *L Page 2 of 62 1.1 Features (CY7C68013A/14A only) ■ CY7C68014A: Ideal for battery powered a pplications ❐ Suspend current:.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document #: 38-08032 Rev . *L Page 3 of 62 2. Applications ■ Portable video recorder ■ MPEG/TV conversion ■ DSL modems ■ ATA i n t e r f a c e ■.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document #: 38-08032 Rev . *L Page 4 of 62 3.5 USB Boot Methods During the power up s equence, internal logic checks the I 2 C port for the connection of an EEPROM whose first byte is either 0xC0 or 0xC2.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document #: 38-08032 Rev . *L Page 5 of 62 The FX2LP jump instruction is encoded as follows: If Autovectoring is enabled (A V2EN = 1 in the INTSET -UP register), the FX2LP substitutes its INT2VEC byte.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document #: 38-08032 Rev . *L Page 6 of 62 If Autovectoring is enabled (A V4EN = 1 in the INTSET -UP register), the FX 2LP substitute s its INT4VEC byte.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document #: 38-08032 Rev . *L Page 7 of 62 3.9.2 Wakeup Pins The 8051 puts itself and the rest of the chip into a power down mode by setting PCON.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document #: 38-08032 Rev . *L Page 8 of 62 Figure 3. Internal Code Memory , EA = 0 Inside FX2LP Out side FX2LP 7.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document #: 38-08032 Rev . *L Page 9 of 62 Figure 4. External Code Memory , EA = 1 3.1 1 Register Addr esses Inside FX2LP Out side FX2LP 7.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document #: 38-08032 Rev . *L Page 10 of 62 3.12 End point RAM 3.12.1 Size ■ 3× 64 bytes (En dpoints 0 and 1) ■ 8 × 512 bytes (Endpoints 2, 4, 6, 8) 3.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document #: 38-08032 Rev . *L Page 1 1 of 62 3.12.5 Default F ull-Speed Alternate Setting s 3.12.6 Default High-Speed Alternate Settings 3.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document #: 38-08032 Rev . *L Page 12 of 62 3.13.3 GPIF and F IFO Clock Rates An 8051 register bit sele cts one of two frequencies for the inter- nally supplied interface clock: 30 MHz and 48 MHz.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document #: 38-08032 Rev . *L Page 13 of 62 3.18 I 2 C Controlle r FX2LP has one I 2 C port that is driven by tw o internal controllers, one that automati.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document #: 38-08032 Rev . *L Page 14 of 62 3.20 CY7C68013A/14 A and CY7C68 015A/16 A Difference s CY7C68013A is identical to CY7C6 8014A in form, fit, and functionality . CY7C68015A is identical to CY7C680 16A in form, fit, and functionality .
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document #: 38-08032 Rev . *L Page 15 of 62 Figure 6. S ignal RDY0 RDY1 CTL0 CTL1 CTL2 INT0#/PA0 INT1#/PA1 PA2 WU2/PA3 PA4 PA5 PA6 PA7 56 BKPT PORTC7/GPIF.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document #: 38-08032 Rev . *L Page 16 of 62 Figure 7. CY7C6801 3A/CY7C68014A 128-pin T QFP Pin Assignmen t CLKOUT VCC GND RDY0/*SLRD RDY1/*SLWR RDY2 RDY3 .
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document #: 38-08032 Rev . *L Page 17 of 62 Figure 8. CY7C6801 3A/CY7C68014A 100-pin T QFP Pin Assignmen t PD0/FD8 *WAKEUP VCC RESET# CTL5 GND PA7/*FLAGD/.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document #: 38-08032 Rev . *L Page 18 of 62 Figure 9. CY7C68013A/CY7C68014A 56-pin SSOP Pin Assignmen t 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document #: 38-08032 Rev . *L Page 19 of 62 Figure 10. CY7C68013A/14A/1 5A/16A 56 -pin QFN Pin Assignment 28 27 26 25 24 23 22 21 20 19 18 17 16 15 43 44 .
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document #: 38-08032 Rev . *L Page 20 of 62 Figure 1 1. CY7C68013A 56-pin VFBGA Pin Assignment - T op View 12345 678 A B C D E F G H 1A 2A 3A 4A 5A 6A 7A .
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document #: 38-08032 Rev . *L Page 21 of 62 4.1 CY7C68013A/15A Pin Descriptions The FX2LP Pin Descriptions follows. [10] T able 1 1. FX2LP Pin Descrip tions 128 TQFP 100 TQFP 56 SSOP 56 QFN 56 VF- BGA Name Ty p e Default Descrip tion 10 9 10 3 2D A VCC Power N/A Analog VCC .
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document #: 38-08032 Rev . *L Page 22 of 62 34 28 BKPT Output L Breakpoint . Th is pin goes active (HIGH) when the 8051 address bus matches the BP ADDRH/L registers and breakpoints are enabled in the BREAKPT register (BPEN = 1).
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document #: 38-08032 Rev . *L Page 23 of 62 85 70 43 36 7F P A 3 or WU2 IO/Z I (P A3) Multiplexed pi n whose function is selected by: W AKEUP .7 and OEA.3 PA 3 is a bidi rectional IO port pin. WU2 is an alternate source for USB W akeup, enabled by WU2EN bit (W AKEUP .
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document #: 38-08032 Rev . *L Page 24 of 62 55 45 30 23 5G PB5 or FD[5] IO/Z I (PB5) Multiplexed pin whose function is selected by the following bits: IFCONFIG [1..0] . PB5 is a bidirectional IO port pin. FD[5] is the bidirection al FIFO/GPIF data bus.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document #: 38-08032 Rev . *L Page 25 of 62 104 82 54 47 6B PD2 or FD[10] IO/Z I (PD2) Multiplexed pin whose function is selected by the IFCONFIG[ 1. .0 ] and EPxFIFOCFG .0 (wordwide) bit s. FD[10] is the bidirectional F IFO/GPIF data bus.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document #: 38-08032 Rev . *L Page 26 of 62 1 12 90 PE4 or RXD1OUT IO/Z I (PE4) Multiplexed pin whose function is selected by the PORTECFG .4 bit. PE4 is a bidire ctional IO port pin. RXD1OUT is an active-HIGH output from 8051 UART1.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document #: 38-08032 Rev . *L Page 27 of 62 70 55 37 30 7G CTL1 or FLAGB O/Z H Multiplexed pin whose function is selected by the following bits: IFCONFIG[1..0]. CTL1 is a GPIF control output. FLAGB is a programmable sl ave-FIFO output status flag signal.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document #: 38-08032 Rev . *L Page 28 of 62 50 40 TXD0 O utput H TXD 0 is the active-HIGH TXD0 output from 8051 UART0, which provides the output clock in sync mode, and the output data in async mode. 42 CS# Output H CS# is the active -LOW chip se lect for external memory .
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document #: 38-08032 Rev . *L Page 29 of 62 5. Register Summary FX2LP register bit definitions are described in the FX2LP TRM in grea ter de tail.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document #: 38-08032 Rev . *L Page 30 of 62 E62B 1 ECC1B1 ECC1 Byte 1 Ad dress LINE7 LINE6 LINE5 LINE4 LINE3 LINE2 LINE1 LINE0 000000 00 R E62C 1 ECC1B2 E.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document #: 38-08032 Rev . *L Page 31 of 62 E65D 1 USBIRQ [12] USB Inte rru pt Requests 0 EP0ACK HSGRANT URES SUSP SUTOK SOF SUDA V 0xxxxxxx rbbbbbbb E65E.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document #: 38-08032 Rev . *L Page 32 of 62 E69D 1 EP8BCL [1 1] Endpoint 8 Byt e Count L BC7/SKIP BC6 BC5 BC4 BC3 BC2 BC1 BC0 xxxxxxxx RW E69E 2 reserved .
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document #: 38-08032 Rev . *L Page 33 of 62 E6CB 1 FLOWSTB Flowst ate S trobe Configuration SLA VE RDY ASYNC CTL TOGL SUST AIN 0 MSTB2 MSTB1 MSTB0 00 1000.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document #: 38-08032 Rev . *L Page 34 of 62 xxxx I²C Configura tion Byte 0 DISCON 0 0 0 0 0 400KHZ xxxxxxxx [14] n/a S pecial Function Registers (SFRs) 8.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document #: 38-08032 Rev . *L Page 35 of 62 BE 1 GPIFSGLDA TLX [13] GPIF Data L w/ Trigger D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW BF 1 GPIFSGLDA TL- NOX [13].
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document #: 38-08032 Rev . *L Page 36 of 62 6. Absolute Maximum Ratings S torage T emperature ......................... ... ......................... ... ........... ... ... ........... ... .. ............
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document #: 38-08032 Rev . *L Page 37 of 62 9. DC Characteristics 9.1 USB T ransceiver USB 2.0 compliant in full-speed and high-spe ed modes. 10. AC Electrical Characterist ics 10.1 USB T ransceiver USB 2.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document #: 38-08032 Rev . *L Page 38 of 62 10.2 Program Memory Read Figure 12. Program Memo ry Read Timing Diagram t CL t DH t SOEL t SCSL PSEN# D[7..0] OE# A[15..0] CS# t STBL data in t ACC1 t AV t STBH t AV CLKOUT [17] [18] T able 15 .
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document #: 38-08032 Rev . *L Page 39 of 62 10.3 Dat a Memory Read Figure 13. Dat a Memory Read Timing Diagram data in t CL A[15..0] t AV t AV RD# t STBL t STBH t DH D[7..0] data in t ACC1 [19] t DSU Stretch = 0 Stretch = 1 t CL A[15.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document #: 38-08032 Rev . *L Page 40 of 62 10.4 Dat a Memory Write Figure 14. Data Memory W rite Timing Diagram When using the AUTPOPTR1 or AUTOPTR2 to address external memo ry , the address of AUTOP TR1 is only active while ei ther RD# or WR# are active.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document #: 38-08032 Rev . *L Page 41 of 62 10.5 PORTC Strobe Feature Timings The RD# and WR# are present in the 100-pin version and the 128-pin package. In these 100-pin and 128 -pin versions, an 8051 control bit can be se t to pulse the R D# and WR# pins w hen the 8051 reads from or writes to PORTC.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document #: 38-08032 Rev . *L Page 42 of 62 10.6 GPIF Synchronous Signals Figure 17. GPIF Synchronous Signals T iming Diagram [20] DATA(output) t XGD IFCLK RDY X DATA(input) valid t SRY t RYH t IFCLK t SGD CTL X t XCTL t DAH N N+1 GPIFADR[8:0] t SGA T ab le 18.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document #: 38-08032 Rev . *L Page 43 of 62 10.7 Slave FIFO Synchronous Read Figure 18. Slave FIFO Synchronous Read Timing Diagram [20] IFCLK SLRD FLAGS SLOE t SRD t RDH t OEon t XFD t XFLG DATA t IFCLK N+1 t OEoff N T ab le 20 .
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document #: 38-08032 Rev . *L Page 44 of 62 10.8 Slave FIFO Asynchronous Read Figure 19. Slave FIFO Asynchr onous Read Timing Diagram [20] SLRD FLAGS t RDpwl t RDpwh SLOE t XFLG t XFD DATA t OEon t OEoff N+1 N T ab le 22 .
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document #: 38-08032 Rev . *L Page 45 of 62 10.9 Slave FIFO Synchronous W rite Figure 20. Slave FIFO Sync hron ou s W rite Timing Diagram [20] Z Z t SFD t FDH DATA IFCLK SLWR FLAGS t WRH t XFLG t IFCLK t SWR N T ab le 23 .
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document #: 38-08032 Rev . *L Page 46 of 62 10.10 Slave FIFO Asynchronous W rite Figure 21. Slave FIFO Asynch ronous Write T iming Diagram [20] 10.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document #: 38-08032 Rev . *L Page 47 of 62 There is no specific timing re quiremen t that should be met for asserting PKTEND pin to a sserting SL WR. PKTEND can be asserted with the last data value clocked into the FIFOs or there- after .
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document #: 38-08032 Rev . *L Page 48 of 62 10.13 Slave FIFO Output Enable Figure 25. S lave FIFO Output En able Ti ming Diagram [20] 10.14 Slave FIFO Address to Flags/Dat a Figure 26. Slave FIFO Addres s to Flags/Data T iming Dia gr am [20] T able 29 .
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document #: 38-08032 Rev . *L Page 49 of 62 10.15 Slave FIFO Synchronous Address Figure 27. Slave FIFO Synchronous Addr ess Timing Diagram [20] 10.16 Slave FIFO Asynchronous Address Figure 28. Slave FIFO Asynch ronous Address T iming Diagram [20] IFCLK SLCS/FIFOADR [1:0] t SFA t FAH T ab le 31.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document #: 38-08032 Rev . *L Page 50 of 62 10.17 Sequence Diagram 10.17.1 Single and Burst Synchronous Read Exa mple Figure 29. Slave FIFO Synchron ou s Rea d Sequ en c e an d T iming Diagram [20] Figure 30.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document #: 38-08032 Rev . *L Page 51 of 62 10.17.2 Single and Bu rst Synchronous Write Figure 31. Slave FI FO Synchronou s Write Sequence and Timing Diagram [20] The Figure 31 shows the timing relationship of the SLA VE FIFO signals during a synchronou s write using IFCLK as the synchro- nizing clock.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document #: 38-08032 Rev . *L Page 52 of 62 10.17.3 Sequence Diagram of a Single and Burst Asynchronous Rea d Figure 32.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document #: 38-08032 Rev . *L Page 53 of 62 10.17.4 Sequence Diagram of a Single and Burst Asynchronous Wri te Figure 34. Slave FIFO Asynchronous Write Sequence and Timing Diagram [20] Figure 34 shows the timing relationship of the SLA VE FIFO write in an asynchronous mode.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document #: 38-08032 Rev . *L Page 54 of 62 1 1. Ordering Information T able 33. Orderi ng Informatio n Ordering Code Package T ype RAM Size # Prog IOs 80.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document #: 38-08032 Rev . *L Page 55 of 62 12. Package Diagrams The FX2LP is available in five packages: ■ 56-pin SSOP ■ 56-pin QFN ■ 100-pin TQFP ■ 128-pin TQFP ■ 56-ball VFBGA Package Diagrams 51-85062 -*C Figure 35.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document #: 38-08032 Rev . *L Page 56 of 62 Package Diagrams (continued) 51-85144-* D Figure 36. 56-Lead QFN 8 x 8 mm LF56A (51-85144) TOP VIEW 0.80[0.031] 7.70[0.303 ] 7.90[0.311] A C 1.00 [0 .039 ] MA X.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document #: 38-08032 Rev . *L Page 57 of 62 Package Diagrams (continued) NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document #: 38-08032 Rev . *L Page 58 of 62 Package Diagrams (continued) NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document #: 38-08032 Rev . *L Page 59 of 62 13. PCB Layout Recommendations Follow these recommendati ons to ensure reliable high p erfor- mance operation: [24] ■ Four layer impeda nce controlled boards a re required to maintain signal quali ty .
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document #: 38-08032 Rev . *L Page 60 of 62 14. Quad Flat Package No L eads (QFN) Package Design Notes Electrical cont act of the par t to the Printed Ci rcuit Board (PCB) is made by sold ering the leads on the botto m surface of the package to the PCB.
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document #: 38-08032 Rev . *L Page 61 of 62 Document History Page Document Title: CY7C68013A, C Y7C68014A, CY7C6801 5A, CY7C68016A, EZ-USB FX2LP™ U SB Microcontroller High-Speed USB Peri pheral Controller Document Number: 38-08032 REV .
Document #: 38-08032 Rev . *L Revised February 8, 2008 Page 62 of 62 Purchase of I 2 C components from Cypress, or one of its subli censed A ssociated Companies, conveys a li cense under the Philips I.
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Cypress CY7C68015Aをまだ購入していないなら、この製品の基本情報を理解する良い機会です。まずは上にある説明書の最初のページをご覧ください。そこにはCypress CY7C68015Aの技術情報の概要が記載されているはずです。デバイスがあなたのニーズを満たすかどうかは、ここで確認しましょう。Cypress CY7C68015Aの取扱説明書の次のページをよく読むことにより、製品の全機能やその取り扱いに関する情報を知ることができます。Cypress CY7C68015Aで得られた情報は、きっとあなたの購入の決断を手助けしてくれることでしょう。
Cypress CY7C68015Aを既にお持ちだが、まだ読んでいない場合は、上記の理由によりそれを行うべきです。そうすることにより機能を適切に使用しているか、又はCypress CY7C68015Aの不適切な取り扱いによりその寿命を短くする危険を犯していないかどうかを知ることができます。
ですが、ユーザガイドが果たす重要な役割の一つは、Cypress CY7C68015Aに関する問題の解決を支援することです。そこにはほとんどの場合、トラブルシューティング、すなわちCypress CY7C68015Aデバイスで最もよく起こりうる故障・不良とそれらの対処法についてのアドバイスを見つけることができるはずです。たとえ問題を解決できなかった場合でも、説明書にはカスタマー・サービスセンター又は最寄りのサービスセンターへの問い合わせ先等、次の対処法についての指示があるはずです。
