CypressメーカーCYDC128B08の使用説明書/サービス説明書
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1.8V 4k/8k/16k x 16 and 8k/16k x 8 ConsuMoBL Dual-Port S t atic RAM CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Cypress Semiconductor Corpora tion • 198 Champion Cou rt • San Jose , CA 95134-1 709 • 408-943-2 600 Document #: 001-01638 Rev .
CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Document #: 001-01638 Rev . *E Page 2 of 26 Notes: 1. A 0 –A 11 for 4k devices; A 0 –A 12 for 8k devices; A 0 –A 13 for 16k devices. 2. BUSY is an output in master mode and an input in slave mode.
CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Document #: 001-01638 Rev . *E Page 3 of 26 Pin Configurations [3, 4, 5, 6, 7] Notes: 3. A12L and A12R are NC pins for CYDC064B16. 4. IRR functionality is not supported for the CYDC256B 16 device.
CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Document #: 001-01638 Rev . *E Page 4 of 26 Notes: 8. IRR functionality is not supported for the CYDC128B 08 device. 9. Thi s pin is A 13L for CYD C128B08 devices. 10. This pin is A13R for CYDC128B08 devices.
CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Document #: 001-01638 Rev . *E Page 5 of 26 Functional Description The CYDC256B16, CYDC128B16 , CYDC064B16, CYDC128B08, CYDC064B08 are lo w-power CMOS 4k, 8k,16k x 16, and 8/16k x 8 dual-port static RAMs.
CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Document #: 001-01638 Rev . *E Page 6 of 26 then the SEM pin must be asserted instead of th e CE pin, and OE must also be asser ted. Interrupts The upper two memory locati ons may be used for message passing.
CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Document #: 001-01638 Rev . *E Page 7 of 26 When reading a semapho re, all sixteen/eight data lines output the semaphore value. The read value is latched in an output register to prevent the semapho re from changing state during a write from the o ther port.
CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Document #: 001-01638 Rev . *E Page 8 of 26 T ab le 3. Inpu t Read Register Operation [16, 19] SFEN CE R/W OE UB LB ADDR I/O 0 – I/O 1 I/O 2 – I/O 15 Mode HLHL L L x 0 0 0 0 - M a x V A L I D [17] VA L I D [1 7] S tandard Memory Access L L H L X L x0000 V ALID [18] X IRR Read T able 4.
CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Document #: 001-01638 Rev . *E Page 9 of 26 Maximum Ratings [23] (Above which the useful life may be impaired. For user guide- lines, not tested.) S torage T emperature ............. .........
CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Document #: 001-01638 Rev . *E Page 10 of 26 I IX Input Leakage Current 1.8V 1.8V –1 1 –1 1 µ A 2.5V 2.5V –1 1 –1 1 µ A 3.0V 3.0V –1 1 –1 1 µ A I CC Operating Current (V CC = Max.
CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Document #: 001-01638 Rev . *E Page 1 1 of 26 Electrical Characteristics for V CC = 2.5V Over the Operating Range Parameter Description CYDC2.
CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Document #: 001-01638 Rev . *E Page 12 of 26 Electrical Characteristics for 3.0V Over the Operating Range Parameter Description CYDC256B16, C.
CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Document #: 001-01638 Rev . *E Page 13 of 26 7 AC T est Loads and W aveforms Switching Characteristics for V CC = 1.
CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Document #: 001-01638 Rev . *E Page 14 of 26 t HA Address H old From W rite End 0 0 ns t SA [28] Address Set-up to W rite S tart 0 0 ns t PWE.
CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Document #: 001-01638 Rev . *E Page 15 of 26 Switching Characteristics for V CC = 2.5V Over the Operating Range Parameter Description CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Unit -40 -55 Min.
CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Document #: 001-01638 Rev . *E Page 16 of 26 Interrupt Timing [33] t INS INT Set T ime 35 45 ns t INR INT Reset T ime 35 45 ns Semaphore T im.
CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Document #: 001-01638 Rev . *E Page 17 of 26 t HZWE [30, 31] R/W LOW to High Z 15 25 ns t LZWE [30, 31] R/W HIGH to Low Z 0 0 ns t WDD [32] W.
CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Document #: 001-01638 Rev . *E Page 18 of 26 Switching W aveforms Read Cycle No.1 (Either Port Address Access ) [36, 37, 38] Read Cycle No.2 (Either Port CE /OE Access) [36, 39, 40] Read Cycle No.
CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Document #: 001-01638 Rev . *E Page 19 of 26 Write Cycle No.1: R/W Controlled T iming [41, 42, 43, 44, 45, 46] Write Cycle No. 2: CE Controlled T iming [41, 42, 43, 48] Notes: 43. t HA is me asured fro m the ea rlier of CE or R/W or (SEM or R/W ) going HIGH at the end of write cycle.
CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Document #: 001-01638 Rev . *E Page 20 of 26 Semaphore Read After W rite Timing, Either Side [49, 50] Timing Diagram of Semap hore Contention [51, 52] Notes: 49.
CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Document #: 001-01638 Rev . *E Page 21 of 26 Timing Diagram of Read with BUSY (M/S =HIGH) [53] Write T iming with Busy Input (M/S = LOW) Note: 53.
CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Document #: 001-01638 Rev . *E Page 22 of 26 Busy Timing Diagram No.1 (CE Arbitration) Busy Timing Diagram No.
CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Document #: 001-01638 Rev . *E Page 23 of 26 Interrupt Timing Diagrams Notes: 55. t HA depends on which enable pin (CE L or R/W L ) is deasserted first . 56. t INS or t INR depends on which enable pin (CE L or R/W L ) is asserted last.
CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Document #: 001-01638 Rev . *E Page 24 of 26 Ordering Information 16k x16 1.8 V Asynchronous Dual-Por t SRAM Spee d (ns) Orderin g Code Packa.
CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Document #: 001-01638 Rev . *E Page 25 of 26 © Cypress Semi conductor Corpora tion, 2006. The information con tained he rein is subject to change wit hout notice.
CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Document #: 001-01638 Rev . *E Page 26 of 26 Document History Page Document Title: CYDC256B16/CYDC128B16/CYDC06 4B16/CYDC 128B08/CYDC064B08 1.8V 4 k/ 8k/16k x 16 and 8k/16k x 8 ConsuMoBL Dual-Port St atic RAM Document Number: 00 1-01638 REV .
デバイスCypress CYDC128B08の購入後に(又は購入する前であっても)重要なポイントは、説明書をよく読むことです。その単純な理由はいくつかあります:
Cypress CYDC128B08をまだ購入していないなら、この製品の基本情報を理解する良い機会です。まずは上にある説明書の最初のページをご覧ください。そこにはCypress CYDC128B08の技術情報の概要が記載されているはずです。デバイスがあなたのニーズを満たすかどうかは、ここで確認しましょう。Cypress CYDC128B08の取扱説明書の次のページをよく読むことにより、製品の全機能やその取り扱いに関する情報を知ることができます。Cypress CYDC128B08で得られた情報は、きっとあなたの購入の決断を手助けしてくれることでしょう。
Cypress CYDC128B08を既にお持ちだが、まだ読んでいない場合は、上記の理由によりそれを行うべきです。そうすることにより機能を適切に使用しているか、又はCypress CYDC128B08の不適切な取り扱いによりその寿命を短くする危険を犯していないかどうかを知ることができます。
ですが、ユーザガイドが果たす重要な役割の一つは、Cypress CYDC128B08に関する問題の解決を支援することです。そこにはほとんどの場合、トラブルシューティング、すなわちCypress CYDC128B08デバイスで最もよく起こりうる故障・不良とそれらの対処法についてのアドバイスを見つけることができるはずです。たとえ問題を解決できなかった場合でも、説明書にはカスタマー・サービスセンター又は最寄りのサービスセンターへの問い合わせ先等、次の対処法についての指示があるはずです。