Cypress SemiconductorメーカーCY7C1302DV25の使用説明書/サービス説明書
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9-Mbit Burst of T wo Pipelined SRAMs with Q DR™ Architecture CY7C1302DV25 Cypress Semiconductor Corpora tion • 198 Champion Cou rt • San Jose , CA 95134-1 709 • 408-943-2 600 Document #: 38-05625 Rev .
CY7C1302DV25 Document #: 38-05625 Rev . *A Page 2 of 18 Selection Guide CY7C1302 DV25-167 U nit Maximum Operating Freq uency 167 MHz Maximum Operating Current 500 mA Pin Configuration 165-ball FBGA (13 x 15 x 1.
CY7C1302DV25 Document #: 38-05625 Rev . *A Page 3 of 18 Introduction Functional Overview The CY7C1302DV25 is a synchronous pipelined Burst SRAM equipped with both a Rea d port and a Write port. The Read port is dedicated to Read o perations and the Write port is dedicated to Write operations.
CY7C1302DV25 Document #: 38-05625 Rev . *A Page 4 of 18 Synchronous intern al circuitry will automatically thre e-state the outputs following the next rising edg e of the positive output clock (C). This will allow for a seamless transition between devices without the insertio n of wait states in a depth expanded memory .
CY7C1302DV25 Document #: 38-05625 Rev . *A Page 5 of 18 T ruth T able [2, 3, 4, 5, 6, 7] Operation K RPS WPS DQ DQ Write Cycle: Load address on the rising edge of K clock; input write data on K and K rising edges.
CY7C1302DV25 Document #: 38-05625 Rev . *A Page 6 of 18 IEEE 1 149.1 Serial Boundary Sc an (JT AG) These SRAMs incorporate a serial bo undary scan test access port (T AP) in the FBGA package. This part is fully compliant with IEEE S tandard #1 149.1-1900.
CY7C1302DV25 Document #: 38-05625 Rev . *A Page 7 of 18 is loaded into the instruction register upon power-up or whenever the T AP controller is given a test logic reset state. SAMPLE Z The SAMPLE Z instruction caus es the b oundary scan register to be connected between th e TDI and TDO pins when th e T AP controller is in a Shift-DR state.
CY7C1302DV25 Document #: 38-05625 Rev . *A Page 8 of 18 T AP Controller St ate Diagram [9] Note: 9. The 0/1 next to each state re present s the value at TMS at the rising edge of TCK.
CY7C1302DV25 Document #: 38-05625 Rev . *A Page 9 of 18 T AP Controller Block Diagram T AP Electrical Characteristics Over the Operatin g Range [10, 13, 15] Parameter Description T est Condition s Min. Max. Unit V OH1 Output HIGH V oltage I OH = − 2.
CY7C1302DV25 Document #: 38-05625 Rev . *A Page 10 of 18 Output Times t TDOV TCK Clock LOW to TDO V alid 20 ns t TDOX TCK Clock LOW to TDO Invalid 0 ns T AP Timing and T est Conditions [12] Identification Register Definitions Instruction Field Va l u e Description CY7C1302DV25 Revision Number (31:29) 000 V ersion number .
CY7C1302DV25 Document #: 38-05625 Rev . *A Page 1 1 of 18 Scan Register Sizes Register Name Bit Size Instruction 3 Bypass 1 ID 32 Boundary Scan 107 Instruction Codes Instruction Code Description EXTEST 000 C aptures the Input/Output ring contents. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO.
CY7C1302DV25 Document #: 38-05625 Rev . *A Page 12 of 18 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 27 11 H 54 7B 81 3G 1 6P 28 10 G 55 6B 82 2G 2 6N 29 9G 56 6A .
CY7C1302DV25 Document #: 38-05625 Rev . *A Page 13 of 18 Maximum Ratings (Above which the useful life may be impaired.) S torage T e mperature .............. .............. ..... – 65°C to + 150°C Ambient T emperature with Power Applied ..........
CY7C1302DV25 Document #: 38-05625 Rev . *A Page 14 of 18 Thermal Resist ance [20] Parameter Description T est Conditions 165 FBGA Package Unit Θ JA Thermal Resistance (Junction to Ambient) T est conditions follow standard test methods and procedures fo r measuring thermal impedance, per EIA/JESD51.
CY7C1302DV25 Document #: 38-05625 Rev . *A Page 15 of 18 Output Times t CO t CHQV C/ C Clock Rise (or K/K in single clock mode) to Data V alid 2.5 ns t DOH t CHQX Dat a Output Hold after Output C/C Clock Rise (Active to Active) 1.2 ns t CHZ t CHZ Clock (C and C ) Rise to High-Z (Active to Hig h-Z) [23, 24] 2.
CY7C1302DV25 Document #: 38-05625 Rev . *A Page 16 of 18 Switching W aveforms [25, 26, 27] Notes: 25. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0 i.e., A0+1 . 26. Outputs are disabled (High- Z) one clock cycle after a NOP .
CY7C1302DV25 Document #: 38-05625 Rev . *A Page 17 of 18 © Cypress Semi con duct or Cor po rati on , 20 06 . The information con t a in ed he re i n is su bject to change wi t hou t n oti ce. C ypr ess S em ic onduct or Corporation assumes no resp onsibility f or the u se of any circuitry o ther than circui try embodied i n a Cypress prod uct.
CY7C1302DV25 Document #: 38-05625 Rev . *A Page 18 of 18 Document History Page Document Title:CY7C1302DV25 9-Mb Burst o f 2 Pipelined SRAM wi th QDR ™ Architecture Document Number: 38-05625 REV .
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