Cypress SemiconductorメーカーCYS25G0101DX-ATCの使用説明書/サービス説明書
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Cypress Semicond uctor Corporati on • 3901 North First S treet • San Jose • CA 95134 • 408-9 43-2600 March 19, 2002 CYS25G0101DX-A TC Evaluation Board User ’ s Guide [+] Feedback.
CYS25G0101DX-A TC Evaluation Board User’s Guide 2 T able of Contents 1. Introduction ........................................................................... .................................... ........................ 4 2. Features ............
CYS25G0101DX-A TC Evaluation Board User’s Guide 3 List of Figures (continued) Figure 23. Reference Clock Blo ck Schematic Diagram ............................................................. ...... 31 Figure 24. CYS25G0101DX Evaluation Board PCB Mechanica l Drawing .
CYS25G0101DX-A TC Evaluation Board User’s Guide 4 1. Introduction Cypress's CYS25G0101DX SONET OC-48 Transce iver is a communications buildin g bl ock for high -speed SONET data communica- tions.
CYS25G0101DX-A TC Evaluation Board User’s Guide 5 Figure 1. The Block Diagram of th e CYS25G0101DX TXD 15: 0 TX PLL x16 /1 6 RXD 15:0 ( 155. 52MH z ) REFCLK ( 155. 52MH z ) RXCLKOUT SHI FT ER RX CDR PLL TXCLKO I nput Regi st er Ou t p ut Regist er FIFO (5 by te ) SH I FTER ( 155.
CYS25G0101DX-A TC Evaluation Board User’s Guide 6 Figure 2. The CYS25G0101DX Evaluation Board T able 1. Functional Description of the Connec tors Jumpers and Connectors Name Description J1 RxD BUS 16-bit RxD Data Bus interface header (see T able 2 for details).
CYS25G0101DX-A TC Evaluation Board User’s Guide 7 J5 SD This jumper is used to set the SD signal. When o pen (default), SD signal will b e driven by the optical module. When 1-2 are shor ted, SD is forced to HIGH. W hen 2-3 are sho rted, SD is forced to LO W.
CYS25G0101DX-A TC Evaluation Board User’s Guide 8 5 RXD13 HSTL output Parallel receive data outp ut RXD13. The outputs change following RXCLK ↓ 7 RXD12 HSTL output Parallel receive data outp ut RXD12. The outputs change following RXCLK ↓ 9 RXD11 HSTL output Parallel receive data outp ut RXD11.
CYS25G0101DX-A TC Evaluation Board User’s Guide 9 8 TXD12 HSTL input Parallel transmit data input TXD12. The input data is sampled by TX- CLKI ↑ 10 TXD11 HSTL input Parallel transmit data input T XD10. The input data i s sampled by TX- CLKI ↑ 12 TXD10 HSTL input Parallel transmit data input TX D9.
CYS25G0101DX-A TC Evaluation Board User’s Guide 10 5 LOOPT IME ON The transmission will be using the extracted receive bit-clo ck for the transmitted bit clock OFF* The transmission will be using t he REFCLK i nput (155.
CYS25G0101DX-A TC Evaluation Board User’s Guide 11 Figure 3. The Jumper Orientations of the CYS25G0101DX J7 J8 LFI GND GND FIFO_ERR RXCLK GND J1 Pin 1 Pin 1 GND GND TXCLKO TXCLKI J2 1 2 3 J5 5B 1B 1.
CYS25G0101DX-A TC Evaluation Board User’s Guide 12 5. Diagnostic Modes The CYS25G0101DX Evaluation Boa rd provides four differen t diagnostic modes—Diagnostic Loopb ack mode, Line Loopback mode, Analog Loopback mode and “P arall el Line L oopback” mode.
CYS25G0101DX-A TC Evaluation Board User’s Guide 13 5.2 Line Loopback In the Line Loopback mode, seria l data (from IN±) will loop through the serial input buffer and CDR block to the serial ou tput buffer (OUT±). Figure 5 shows the data path (bold line) of the Line Loopback mode .
CYS25G0101DX-A TC Evaluation Board User’s Guide 14 5.3 Analog Line Loopback In the Analog Line Lo opback mode, serial data (from IN±) will lo o p through directly from serial inp ut buffer to the serial outp ut buffer (OUT±). Figure 6 shows the data path (bold line) of the Analog Line Loopback mode.
CYS25G0101DX-A TC Evaluation Board User’s Guide 15 5.4 “Parallel Line Loopback” (TEST0) Mode In Parallel Line Loo pback mode, the parallel output buffers are internally linked to the paral lel input buffers. Figure 7 shows the data path (bold line) of the Parallel Line Loopback m ode.
CYS25G0101DX-A TC Evaluation Board User’s Guide 16 6. T esting Hookup 6.1 Set-up for BERT T est Figure 8 illustrates the set-up for the BERT test. The equipment li st: 1. Evaluation Board – Cypress CYS25G0101DX Evaluation Board 2. Pattern Generator – Tektronix D 3186 Pattern Generator 3.
CYS25G0101DX-A TC Evaluation Board User’s Guide 17 6.2 Set-up for Eye Diagram T est Figure 9 illustrates the set-up for testing the Eye Diagram. Th e equipment list : 1. Evaluation Board – Cypress CYS25G0101DX Evaluation Board 2. Pattern Generator – Tektronix D 3186 Pattern Generator 3.
CYS25G0101DX-A TC Evaluation Board User’s Guide 18 6.3 SONET Jitter T ran sfer and Jitter T olerance T est Figure 10 illustra tes the set-up for testi ng the jitter. The equip ment list: 1. Evaluation Board – Cypress CYS25G0101DX Evaluation Board 2.
CYS25G0101DX-A TC Evaluation Board User’s Guide 19 6.4 Set-up for T esting the TX PLL in Parallel Line Loopback Mode Figure 1 1 illustrates the set-up for testing the TX PLL in Parallel Line Loopback Mode. The equipment list : 1. Evaluation Board – Cypress CYS25G0101DX Evaluation Board 2.
CYS25G0101DX-A TC Evaluation Board User’s Guide 20 7. Eye Diagram T esting Result Figure 12 is the Eye Diagram measurement fr om CYS25G0101DX Evaluation Board by using the test set-up as in Figure 9 . In this measurement, the evaluation board i s c onfigured to parallel loop back mo de ( Figure 7 ) and with no SONET filter at the oscil loscope.
CYS25G0101DX-A TC Evaluation Board User’s Guide 21 8. Jitter T ransfer T esting Result Figure 13 and Figure 14 show the Jitter Transf er measurem ent by using the test set-up as in F igure 10 . Figure 13 is the measurement result of the GR-253 (B ellcore) standard and Figure 14 is the measurement resul t of the G958 (ITU) standard.
CYS25G0101DX-A TC Evaluation Board User’s Guide 22 9. Jitter T olerance T esting Result Figure 15 and Figure 16 show the Jitter Tolerance mea surement by using the test set-up as in Figure 10 . Figure 15 is the measurement result of the GR-253 (B ellcore) standard and Figure 16 is the measurement resul t of the G825 (ITU) standard.
CYS25G0101DX-A TC Evaluation Board User’s Guide 23 10. Schematic Diagram, PCB Layout and BOM (Bill of Material) Figure 17 to Figure 23 in Appendix A shows the schematic diagram of the CYS25G0101DX evalu ation board. Figure 17 i s the top level diagram for the schem atic diagrams for Figure 18 to Figure 23 .
CYS25G0101DX-A TC Evaluation Board User’s Guide 24 Appendix A: Schematic Diagrams of the CYS25G0101DX Evaluation Board [+] Feedback.
CYS25G0101DX-A TC Evaluation Board User’s Guide 25 Figure 17. T op Level of CYS25G0101DX Evaluation Board Schematic Dia gram Parallel Input Block Parallel Output Block Power Supply Block Control Blo.
CYS25G0101DX-A TC Evaluation Board User’s Guide 26 Figure 18. Parall el Output Block Schematic Diagra m [+] Feedback.
CYS25G0101DX-A TC Evaluation Board User’s Guide 27 Figure 19. Parallel Inpu t Block Schematic Diagram [+] Feedback.
CYS25G0101DX-A TC Evaluation Board User’s Guide 28 Figure 20. Signals Bloc k Schematic Diagram [+] Feedback.
CYS25G0101DX-A TC Evaluation Board User’s Guide 29 Figure 21. Powe r Supply Block Schematic Diagram [+] Feedback.
CYS25G0101DX-A TC Evaluation Board User’s Guide 30 Figure 22. Control Blo ck Schematic Diagram [+] Feedback.
CYS25G0101DX-A TC Evaluation Board User’s Guide 31 Figure 23. Reference Clock Blo ck Schematic Diagram [+] Feedback.
CYS25G0101DX-A TC Evaluation Board User’s Guide 32 Appendix B: PCB Layout Diagrams of the CYS25G0101DX Evaluation Board [+] Feedback.
CYS25G0101DX-A TC Evaluation Board User’s Guide 33 Figure 24. CYS25G0101DX Evaluation Board PCB Mechanical D rawing [+] Feedback.
CYS25G0101DX-A TC Evaluation Board User’s Guide 34 Figure 25. CYS25G0101DX Evaluation Bo ard PCB T op Layer Silk Scre en [+] Feedback.
CYS25G0101DX-A TC Evaluation Board User’s Guide 35 Figure 26. CYS25G0101DX Evalu ation Board PCB T o p Layer Layout [+] Feedback.
CYS25G0101DX-A TC Evaluation Board User’s Guide 36 Figure 27. CYS2 5G0101DX Evaluation Boa rd PCB T op Layer Solder Mask [+] Feedback.
CYS25G0101DX-A TC Evaluation Board User’s Guide 37 Figure 28. CYS25G0101DX Evalu ation Board PCB Power Plane Layout [+] Feedback.
CYS25G0101DX-A TC Evaluation Board User’s Guide 38 Figure 29. CYS2 5G0101DX Evaluation Boa rd PCB Ground Plane Layout [+] Feedback.
CYS25G0101DX-A TC Evaluation Board User’s Guide 39 Figure 30. CYS25G0101D X Evaluation Board PCB Bottom Silk Screen [+] Feedback.
CYS25G0101DX-A TC Evaluation Board User’s Guide 40 Figure 31. CYS25G0101DX Evaluation Bo ard PCB Bottom Layer Layout [+] Feedback.
CYS25G0101DX-A TC Evaluation Board User’s Guide 41 Figure 32. CYS25G0101DX Evaluation Board PCB Bottom Solder Mask [+] Feedback.
CYS25G0101DX-A TC Evaluation Board User’s Guide 42 Appendix C: CYS25G0101DX Evaluation Board L VPECL BOM (Bill of Material) [+] Feedback.
CYS25G0101DX-A TC Evaluation Board User’s Guide 43 T able 8. CYS25G0101DX Evalua tion Board L VPEC L BOM - Page 1 of 4 [+] Feedback.
CYS25G0101DX-A TC Evaluation Board User’s Guide 44 T able 9. CYS25G0101DX Evalua tion Board L VPEC L BOM - Page 2 of 4 [+] Feedback.
CYS25G0101DX-A TC Evaluation Board User’s Guide 45 T able 10. CYS25G0101D X Evaluation Board L VPECL BOM - Page 3 of 4 [+] Feedback.
CYS25G0101DX-A TC Evaluation Board User’s Guide 46 T able 1 1. CYS25G0101DX Evaluati on Board L VPECL BOM - Page 4 of 4 [+] Feedback.
CYS25G0101DX-A TC Evaluation Board User’s Guide 47 Appendix D: CYS25G0101DX Evaluation Board HSTL BOM (Bill of Material) [+] Feedback.
CYS25G0101DX-A TC Evaluation Board User’s Guide 48 T able 12. CYS25G0101DX Evaluation Boa rd HSTL BOM - Page 1 of 4 [+] Feedback.
CYS25G0101DX-A TC Evaluation Board User’s Guide 49 T able 13. CYS25G0101DX Evaluation Boa rd HSTL BOM - Page 2 of 4 [+] Feedback.
CYS25G0101DX-A TC Evaluation Board User’s Guide 50 T able 14. CYS25G0101DX Evaluation Boa rd HSTL BOM - Page 3 of 4 [+] Feedback.
CYS25G0101DX-A TC Evaluation Board User’s Guide © Cypress Semico nductor Corporation, 200 2. The information contai ned herein is subject to chang e without notice. Cypress Semico nductor Corporation assumes no respo nsibility for the use of any circui try other than circuitr y embodied in a Cypr ess Semiconductor product.
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