Freescale Semiconductorメーカー56F8322の使用説明書/サービス説明書
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56F8300 16-bit Hybrid Controllers freescale. com 56F8322/56F8122 Data Sheet Pr eliminary T echnical Data MC56F832 2 Rev. 10.0 10/20 04.
56F8322 T echncia l Dat a, Rev . 10.0 2 Free scal e S emic ondu cto r Preliminar y Document Revision History Version History Description of Cha nge Rev 1.0 Pre-Rele ase version, Alpha customers onl y Rev 2.0 Initial Public Rel ease Rev 3.0 Corrected typo in Table 10- 4 , Flash En durance i s 10,000 cy cles.
56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 3 Prelimin ary 56F832 2/56F8122 Block Diagram Program Controlle r and H ard wa re Looping Unit Data ALU 16 x 16 + 36 -> 36-Bit MAC T.
56F8322 T echncia l Dat a, Rev . 10.0 4 Free scal e S emic ondu cto r Preliminar y Part 1: Ov erv iew . . . . . . . . . . . . . . . . . . . . . . 5 1.1. 56F8322/56F812 2 Features . . . . . . . . . . . . . 5 1.2. Device Desc ription . . . . . . . . . .
56F8322/56F8122 Features 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 5 Prelimin ary Part 1 Overview 1.1 56F8322/56F8122 Featu res 1.
56F8322 T echncia l Dat a, Rev . 10.0 6 Free scal e S emic ondu cto r Preliminar y 1.1.3 Mem ory Note: Features in italics are NOT available in the 56F8122 device.
Device Descr iption 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 7 Prelimin ary 1.1.5 Energy In formation • Fa bricated in high-dens ity CMOS with 5V -t olerant, TTL-compatib le digit al inputs • On-boa rd 3.
56F8322 T echncia l Dat a, Rev . 10.0 8 Free scal e S emic ondu cto r Preliminar y is programmable to support a continuously variable PWM frequency. Edge -aligned and center-aligned synchronous pulse width control (0% to 100% modulation) is supported.
Architecture Block Diagram 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 9 Prelimin ary 1.4 Architecture Blo ck Diagram Note: Features in italics are NOT available in the 56F8122 device and are shaded in the following figures. The 56F8322/56F8122 architecture is shown in Figure 1-1 and Figure 1-2 .
56F8322 T echncia l Dat a, Rev . 10.0 10 Free scal e S emic ondu cto r Preliminar y Figure 1-1 S ystem Bus Interfac es Note: Flas h memories are e ncapsulated with in the Fla sh Memory Modu le (FM).
Architecture Block Diagram 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 11 Prelimin ary Figure 1-2 Peripheral Subsystem IPBus Time r A SPI 0 ADCA 2 6 SPI 1 GPIO A 4 Interrupt Contr.
56F8322 T echncia l Dat a, Rev . 10.0 12 Free scal e S emic ondu cto r Preliminar y Table 1-2 Bus Signal Na mes Name Function Progra m Memory I nterface pdb_m[15 :0] Program d ata bus fo r instruct ion word fetc hes or rea d operatio ns. cdbw[1 5:0] Primary core da ta bus used for prog ram memory writes.
Product Documentation 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 13 Prelimin ary 1.5 Product Documen tation The documents listed in Table 1-3 are required for a complete description and proper design with the 56F8322 and 56F8122 devices.
56F8322 T echncia l Dat a, Rev . 10.0 14 Free scal e S emic ondu cto r Preliminar y Part 2 Signal/Co nnection Description s 2.1 Introduct ion The input and output signals of the 56F8322 and 56F8122 devices are organized into functional groups, as detailed in Table 2-1 and as illust rated in Figure 2-1 and Figure 2-2 .
Introduction 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 15 Prelimin ary Figure 2-1 56F8322 Signals Identified by Functiona l Group (48-Pin LQFP) V DD_IO V DDA_AD C V SSA_AD C EXT.
56F8322 T echncia l Dat a, Rev . 10.0 16 Free scal e S emic ondu cto r Preliminar y Figure 2-2 56F8122 Signals Identified by Functiona l Group (48-Pin LQFP) V DD_IO V DDA_AD C V SSA_AD C EXT AL (GPIOC.
Signal Pins 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 17 Prelimin ary 2.2 Signal Pins After reset, eac h pin is configured for its primary function (lis ted first). In the 56F8122, after reset, each pin mus t be configured for the desired function.
56F8322 T echncia l Dat a, Rev . 10.0 18 Free scal e S emic ondu cto r Preliminar y EXTAL (GPIOC0) 32 Input/ Schmitt Input/ Outp ut Inpu t Inpu t External Crys tal Oscillator Inp ut — This input can be connec ted to an 8MHz external crystal. If an exte rnal clock i s used, XTAL must b e used as the inp ut and EXTAL connected to V SS .
Signal Pins 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 19 Prelimin ary PHASEA0 (TA0) (GPIOB7) (oscillator_ clock ) 38 Schmitt Inpu t Schmitt Input/ Outp ut Schmitt Input/ Outp ut.
56F8322 T echncia l Dat a, Rev . 10.0 20 Free scal e S emic ondu cto r Preliminar y INDEX0 (TA2) (GPIOB5) (SYS_CLK) 36 Schmitt Inpu t Schmitt Input/ Outp ut Schmitt Input/ Outp ut Outp ut Inpu t Inpu .
Signal Pins 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 21 Prelimin ary MOSI0 (GPIOB2) 18 Schmitt Input/ Outp ut Schmitt Input/ Outp ut Tri- stat ed Inpu t SPI 0 M aster Out/Slave In — Thi s serial dat a pin is an output f rom a maste r device and an inp ut to a sl ave devi ce.
56F8322 T echncia l Dat a, Rev . 10.0 22 Free scal e S emic ondu cto r Preliminar y PWMA1 (GPIOA1) 4S c h m i t t Outp ut Schmitt Input/ Outp ut Tri- stat ed Inpu t PWM A1 — This is one o f six PWM A output pin s. Port A GPIO - Th is GPIO pin can b e individua lly progra mmed as an input o r output pi n.
Signal Pins 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 23 Prelimin ary PWMA4 (MOSI1) (GPIOA4) 8O u t p u t Schmitt Input/ Outp ut Schmitt Input/ Outp ut Tri- stat ed Tri- stat ed Inpu t PWM A4 — This is one o f six PWM A output pin s.
56F8322 T echncia l Dat a, Rev . 10.0 24 Free scal e S emic ondu cto r Preliminar y V REFP 28 Input/ Outp ut Input/ Outp ut V REFP , V REF MID & V REFN — Inter nal pins for voltage ref erence w hich are brou ght off-chip so that they c an b e b ypassed .
Signal Pins 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 25 Prelimin ary IRQA (V PP ) 11 Schmitt Inpu t Inpu t N/A Ex te rn al I n te r ru pt R eq u es t A — T he IRQA input is an a synchronous externa l interrupt request durin g Stop and Wait mode operati on.
56F8322 T echncia l Dat a, Rev . 10.0 26 Free scal e S emic ondu cto r Preliminar y Part 3 On-Chip Clock Synth esis (OCCS) 3.1 Introduct ion Refer to the OCCS chapter of the 56F8300 Per ipheral User Manual for a full descri ption of the OCCS. The material contained here identifies the spe cific features of the OCCS design.
External Clock Operation 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 27 Prelimin ary 3.2.2 Ceramic Resonator (Default) It is also possible to drive the internal oscillator with a ceramic resonator, assuming the overall system design can toler ate the r educed signal integrity.
56F8322 T echncia l Dat a, Rev . 10.0 28 Free scal e S emic ondu cto r Preliminar y 3.3 Use of On-Ch ip Relaxation Oscillat or An inter nal relaxtion oscillator can s upply the refer ence fr equency whe n a n external freque ncy source of crystal is not used.
Registers 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 29 Prelimin ary Figure 3-4 Internal Clock Operation 3.5 Registers When referring to the re gister definitions for the O CCS i.
56F8322 T echncia l Dat a, Rev . 10.0 30 Free scal e S emic ondu cto r Preliminar y Part 4 Memory Map 4.1 Introduct ion The 56F8322 and 56F8122 devices are 16-bit m otor-control chips based on the 56800E core. These parts use a Harvard-style architecture with two independent memory spaces for Data and Program.
Interrupt Vector Table 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 31 Prelimin ary Note: Program RAM is NOT available on the 56F8122 device. 4.3 Interrupt Vector Tab le Tabl e 4-3 provides the device’s reset and interrupt priority structure, including on-chip p eripherals.
56F8322 T echncia l Dat a, Rev . 10.0 32 Free scal e S emic ondu cto r Preliminar y core 6 1-3 P:$0C OnCE Step Counter core 7 1 -3 P: $0E O nCE Br eak point U nit 0 Rese rved core 9 1-3 P:$12 OnCE Tra.
Interrupt Vector Table 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 33 Prelimin ary Rese rved TMRC 56 0-2 P:$70 Timer C Ch annel 0 TMRC 57 0-2 P:$72 Timer C Ch annel 1 TMRC 58 0-2 .
56F8322 T echncia l Dat a, Rev . 10.0 34 Free scal e S emic ondu cto r Preliminar y 4.4 Data Map Note: Data Flash is NOT available on the 56F8122 device. 4.5 Flash Memory Map Figure 4-1 illustrates the Flash Memory (FM) m ap on the system bus. Flash Memory i s divided into three functional blocks.
Flash Memory Map 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 35 Prelimin ary Figure 4-1 Flash Array Memory Maps Tabl e 4-5 shows the pa ge and sector sizes used within each Flash memory block on the chip. Note: Data Flash is NOT available on the 56F8122 device.
56F8322 T echncia l Dat a, Rev . 10.0 36 Free scal e S emic ondu cto r Preliminar y 4.6 EOnCE Memory Map 4.7 Peripheral Memory Mapped Registers On-chip periphera l registers are pa rt of the da ta memory map on the 56800E series.
Peripheral Memory M apped Registers 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 37 Prelimin ary The following tables list all of the peripheral registers required to control or access the per ipherals. Note: Features in italics are NOT available on the 56F8122 device.
56F8322 T echncia l Dat a, Rev . 10.0 38 Free scal e S emic ondu cto r Preliminar y TMRA0_ CMPLD2 $9 Comparat or Load Regi ster 2 TMRA0_ COMSCR $A Comparator Sta tus and Co ntrol Regis ter Reserved TM.
Peripheral Memory M apped Registers 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 39 Prelimin ary Table 4-9 Quad Timer C Re gisters Address Map (TMRC_BASE = $00 F0C0) Register A cro.
56F8322 T echncia l Dat a, Rev . 10.0 40 Free scal e S emic ondu cto r Preliminar y TMRC3_CM P2 $31 Compa re Register 2 TMRC3_CA P $32 C apture Regi ster TMRC3_LO AD $33 Load Register TMRC3_HO LD $34 .
Peripheral Memory M apped Registers 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 41 Prelimin ary Table 4-11 Quadrature Decoder 0 Registers Address Map (DEC0_BAS E = $00 F1 80) Quad.
56F8322 T echncia l Dat a, Rev . 10.0 42 Free scal e S emic ondu cto r Preliminar y IRQP 0 $11 IRQ Pendin g Register 0 IRQP 1 $12 IRQ Pendin g Register 1 IRQP 2 $13 IRQ Pendin g Register 2 IRQP 3 $14 .
Peripheral Memory M apped Registers 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 43 Prelimin ary ADCA_HLMT 1 $1A High Limit Register 1 ADCA_HLMT 2 $1B High Limit Register 2 ADCA_HL.
56F8322 T echncia l Dat a, Rev . 10.0 44 Free scal e S emic ondu cto r Preliminar y Table 4-16 Serial Communication Interface 1 Registers Address Map (SCI1 _BASE = $00 F290) Register Ac ronym Address .
Peripheral Memory M apped Registers 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 45 Prelimin ary Table 4-20 Clock Generation Module Registers Address Map (CLKGEN_BASE = $00 F2D0) R.
56F8322 T echncia l Dat a, Rev . 10.0 46 Free scal e S emic ondu cto r Preliminar y Table 4-23 GPIOC Re gisters Address Map (GPIOC _BASE = $00F310) Registe r Acronym Address Offset Register D escripti.
Peripheral Memory M apped Registers 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 47 Prelimin ary Table 4-26 Flash Module Registers Address Map (FM_B ASE = $00 F400) Register Ac ron.
56F8322 T echncia l Dat a, Rev . 10.0 48 Free scal e S emic ondu cto r Preliminar y FCRX14MASK_H $A Receive Buffer 14 Mas k High Registe r FCRX14MASK_L $B Receive Buffer 14 Mas k Low Register FCRX15MA.
Peripheral Memory M apped Registers 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 49 Prelimin ary FCMB3_CON TROL $58 Message Buffe r 3 Control / Status Re gister FCM B3_I D_HI GH $5.
56F8322 T echncia l Dat a, Rev . 10.0 50 Free scal e S emic ondu cto r Preliminar y FCMB7_DATA $7C Message Buffe r 7 Data Registe r FCMB7_DATA $7D Message Buffe r 7 Data Registe r FCMB7_DATA $7E Messa.
Peripheral Memory M apped Registers 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 51 Prelimin ary FCMB12_ ID_HIGH $A1 Message Buffe r 12 ID Hig h Register FCMB12_ID_LO W $A2 Message.
56F8322 T echncia l Dat a, Rev . 10.0 52 Free scal e S emic ondu cto r Preliminar y 4.8 Factory-Program med Memory The Boot Flash memory block is programmed during manufacturing with a default Serial Bootloader program.
Functional Description 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 53 Prelimin ary 5.3.2 Interrupt Nes ting Interrupt e xceptions may be nested to allow an IRQ of higher priority than the curr ent exce ption to be serviced. The following tables define the nesting requirements for ea ch priority level.
56F8322 T echncia l Dat a, Rev . 10.0 54 Free scal e S emic ondu cto r Preliminar y 5.4 Block Diagram Figure 5-1 Interrupt Controller Block Diagram 5.5 Operating Mode s The ITCN module design contains two major modes of operation: • Functional Mode The ITCN i s in this mode by default.
Register Descriptions 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 55 Prelimin ary 5.6 Register Descriptions A re gister a ddress is the sum of a base address and an address offset. The base address is defined at the system level and the address offset is defined at the module level.
56F8322 T echncia l Dat a, Rev . 10.0 56 Free scal e S emic ondu cto r Preliminar y Figure 5-2 ITCN Register Map Summary Add. Offset Regist er Name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 $0 IPR 0 R 0 0.
Register Descriptions 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 57 Prelimin ary 5.6.1 Interrupt P riority Regi ster 0 (IP R0) Figure 5-3 Interrupt Prior ity Register 0 (IPR0 ) 5.6.1.1 Rese rved—Bits 15–1 4 This bit field is reserved or not implemented.
56F8322 T echncia l Dat a, Rev . 10.0 58 Free scal e S emic ondu cto r Preliminar y 5.6.2.1 Rese rved—Bits 15–6 This bit field is reserved or not implemented.
Register Descriptions 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 59 Prelimin ary 5.6.3.1 Flash Memory Comman d, Data, Address Buffers E mpty Interrupt Priority Level (FMCBE IP L)—Bits 15–14 This field is used to set the interr upt priority level for IRQs.
56F8322 T echncia l Dat a, Rev . 10.0 60 Free scal e S emic ondu cto r Preliminar y 5.6.3.5 Low V oltage Detector I nterrupt Priority Le vel (LVI IPL)—Bits 7–6 This field is used to set the interr upt priority level for IRQs. This IRQ is l imited to priorities 0 through 2.
Register Descriptions 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 61 Prelimin ary 5.6.4.3 FlexC AN Wake Up Inter rupt Priority Leve l (FCWKUP IPL)— Bits 7–6 This field is used to set the interr upt priority level for IRQs. This IRQ is l imited to priorities 0 through 2.
56F8322 T echncia l Dat a, Rev . 10.0 62 Free scal e S emic ondu cto r Preliminar y 5.6.5.1 SPI0 Receiver Full Interrupt Priority Level (SPI0_RCV IPL)— Bits 15–14 This field is used to set the interr upt priority level for IRQs. This IRQ is l imited to priorities 0 through 2.
Register Descriptions 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 63 Prelimin ary 5.6.5.6 GPIO _B Interrupt Prior ity Level (GPIOB IPL)—Bits 3–2 This field is used to set the interr upt priority level for IRQs. This IRQ is l imited to priorities 0 through 2.
56F8322 T echncia l Dat a, Rev . 10.0 64 Free scal e S emic ondu cto r Preliminar y 5.6.6.3 SCI1 Receiver Error I nterrupt Priority L evel (SCI1_RERR IPL)— Bits 9–8 This field is used to set the interr upt priority level for IRQs. This IRQ is l imited to priorities 0 through 2.
Register Descriptions 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 65 Prelimin ary 5.6.7 Interrupt P riority Regi ster 6 (IP R6) Figure 5-9 Interrupt Prior ity Register 6 (IPR6 ) 5.6.7.1 Timer C, Channel 0 Interrupt Priority Level (TMRC_0 IPL)— Bits 15–14 This field is used to set the interr upt priority level for IRQs.
56F8322 T echncia l Dat a, Rev . 10.0 66 Free scal e S emic ondu cto r Preliminar y 5.6.8 Interrupt P riority Regi ster 7 (IP R7) Figure 5-10 Interrupt Priority Register (IPR7) 5.6.8.1 Timer A, Channel 0 Interrupt Priority Level (TMRA0 IPL)— Bits 15–14 This field is used to set the interr upt priority level for IRQs.
Register Descriptions 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 67 Prelimin ary 5.6.8.5 Timer C, Channel 1 Interrupt Priority Level (TMRC1 IPL)—Bits 1–0 This field is used to set the interr upt priority level for IRQs. This IRQ is l imited to priorities 0 through 2.
56F8322 T echncia l Dat a, Rev . 10.0 68 Free scal e S emic ondu cto r Preliminar y 5.6.9.4 SCI0 Transmitter Idle Interrupt Priority L evel (SCI0_TIDL IPL)— Bits 9–8 This field is used to set the interr upt priority level for IRQs. This IRQ is l imited to priorities 0 through 2.
Register Descriptions 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 69 Prelimin ary 5.6.9.8 Timer A, Channel 1 Interrupt Priority Level (TMRA1 IPL)—Bits 1–0 This field is used to set the interr upt priority level for IRQs. This IRQ is l imited to priorities 0 through 2.
56F8322 T echncia l Dat a, Rev . 10.0 70 Free scal e S emic ondu cto r Preliminar y 5.6.10.5 ADC A Zero Crossing or Limit Error Interru pt Priority Leve l (ADCA_ZC IPL)—Bits 7–6 This field is used to set the interr upt priority level for IRQs. This IRQ is l imited to priorities 0 through 2.
Register Descriptions 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 71 Prelimin ary 5.6.12 Fast Interrupt 0 Match Register (FIM0) Figure 5 -14 Fa st Interrupt 0 Match Register ( FIM0) 5.6.12.1 Rese rved—Bits 15–7 This bit field is reserved or not implemented.
56F8322 T echncia l Dat a, Rev . 10.0 72 Free scal e S emic ondu cto r Preliminar y 5.6.14.2 Fast Interrupt 0 Vector Address High (FIVAH0)—Bit s 4–0 The upper f ive bi ts of the vector address used for Fast Interrupt 0. This register i s combined with F IVAL0 to form the 21-bit vector address for Fast Interrupt 0 def ined in the FIM0 register.
Register Descriptions 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 73 Prelimin ary 5.6.17.1 Rese rved—Bits 15–5 This bit field is reserved or not implemented.
56F8322 T echncia l Dat a, Rev . 10.0 74 Free scal e S emic ondu cto r Preliminar y 5.6.20 IRQ Pending 2 Registe r (IRQP2) Figure 5-22 IRQ Pending 2 Register (IRQP2) 5.6.20.1 IRQ P ending (PENDING) —Bits 48–33 This re gister combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81.
Register Descriptions 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 75 Prelimin ary 5.6.23 IRQ Pending 5 Registe r (IRQP5) Figure 5-25 IRQ Pending Register 5 (I RQP5) 5.6.23.1 Rese rved—Bits 96–8 2 This bit field is reserved or not implemented.
56F8322 T echncia l Dat a, Rev . 10.0 76 Free scal e S emic ondu cto r Preliminar y 5.6.30.2 Interr upt Priority Level (IPIC)—Bits 14–1 3 These read-only bits reflect the state of the new interrupt priority level bits being pre sented to the 56800E core at the time the last IRQ was taken.
Resets 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 77 Prelimin ary 5.7 Resets 5.7.1 Reset Handshake Timi ng The ITCN provides the 56800E c ore wi th a reset vector address whenever R ESET is asserted. The reset vector will be presented until the second rising clock edge after RESET is released.
56F8322 T echncia l Dat a, Rev . 10.0 78 Free scal e S emic ondu cto r Preliminar y 6.2 Features The SIM has the following features: • Flas h security f eature pr events unaut horized acce ss to cod.
Operating Mode Register 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 79 Prelimin ary 6.4 Operating Mode Register Figure 6-1 OMR The reset state for the MB bit will depend on the Flash secured state.
56F8322 T echncia l Dat a, Rev . 10.0 80 Free scal e S emic ondu cto r Preliminar y Figure 6-2 SIM Register Map Summary 6.5.1 SIM Contro l R egist er (SIM _C ONTRO L) Figure 6-3 SIM Control Register (SI M_CONTROL) 6.5.1.1 Rese rved—Bits 15–6 This bit field is reserved or not implemented.
Register Descriptions 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 81 Prelimin ary 6.5.1.2 OnCE Enable (ONCE EBL)—Bit 5 • 0 = OnCE clock to 56800E c ore enable d when core T AP is enabled • 1 = OnCE clock to 568 00E core is al ways enable d 6.
56F8322 T echncia l Dat a, Rev . 10.0 82 Free scal e S emic ondu cto r Preliminar y 6.5.2.3 COP Reset (COPR)—Bit 4 When 1, the COPR bit indicates the Computer Operating Prope rly (COP) timer-genera ted re set has occurred. This bit will be cleared by a Power-On R eset or by software.
Register Descriptions 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 83 Prelimin ary 6.5.4 Most S ignif ican t Half of J TAG I D (SIM _MSH_ ID) This read-only re gister displays the most significant half of the JTAG ID for the chip. This register reads $01F4.
56F8322 T echncia l Dat a, Rev . 10.0 84 Free scal e S emic ondu cto r Preliminar y 6.5.6.3 IRQ— Bit 10 This bit controls the pull-up resistors on the IRQA pin. 6.5.6.4 Rese rved—Bits 9–4 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
Register Descriptions 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 85 Prelimin ary 6.5.7.4 INDEX 0 (INDEX )—Bit 7 • 0 = Peripheral out put funct ion of GPIOB[5] i s defined t o be INDEX0 • 1 = Peripheral out put funct ion of GPIOB[5] i s defined t o be SYS_CLK 6.
56F8322 T echncia l Dat a, Rev . 10.0 86 Free scal e S emic ondu cto r Preliminar y Note: PWM is NOT available in the 56F8122 device. As shown in Figure 6- 10 , the GPIO has the final control ove r which pin controls the I/O. SIM_GPS simply decides which peripheral will be routed to the I/O.
Register Descriptions 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 87 Prelimin ary 6.5.8.4 GPIO B1 (B1)—Bit 5 This bit selects the alternate function for GPIOB1. • 0 = MISO0 ( default) • 1 = RXD1 6.5.8.5 GPIO B0 (B0)—Bit 4 This bit selects the alternate function for GPIOB0.
56F8322 T echncia l Dat a, Rev . 10.0 88 Free scal e S emic ondu cto r Preliminar y 6.5.9.1 Rese rved—Bits 15–1 4 This bit field is reserved or not implemented. It is read as 1 and cannot be modified by writing. 6.5.9.2 Analo g-to-Digital Conver ter A Enable (ADCA )—Bit 13 Each bit controls clocks to the indicated peripheral.
Register Descriptions 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 89 Prelimin ary 6.5.9.10 Seria l Communications Interface 1 Enable (SCI1 )—Bit 5 Each bit controls clocks to the indicated peripheral. • 1 = Clocks are en abled • 0 = The clock is not provid ed to the p eripheral ( the periphe ral is di sabled) 6.
56F8322 T echncia l Dat a, Rev . 10.0 90 Free scal e S emic ondu cto r Preliminar y Figure 6-13 I/O S hort Address Determination With this register set, an interrupt driver can set the SIM_ISALL register pair to point to its peripheral registers and then use the I/O Short addressing mode to reference them.
Clock Generation Overview 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 91 Prelimin ary 6.5.10.2 Input/ Output Short Addres s Low (ISAL[21:6])—Bit 15– 0 This field represents the lower 16 address bits of the “hard coded” I/O short addr ess.
56F8322 T echncia l Dat a, Rev . 10.0 92 Free scal e S emic ondu cto r Preliminar y 6.8 Stop and Wait Mode Disable Fu nction Figure 6-16 Internal Stop Disable Circuit The 56800E core contains both STOP and WAIT instructions. Both put the CPU to sleep.
Operation with Security Enabled 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 93 Prelimin ary Part 7 Security Features The 56F8322/56F8122 offer security featur es intended to prevent unauthorized users from reading the contents of the Flash Memory (FM) array.
56F8322 T echncia l Dat a, Rev . 10.0 94 Free scal e S emic ondu cto r Preliminar y Proper implementation of Flash security requires that no access to the EOnCE port is provided w hen security is enabled. The 56800E core has an input which disables rea ding of internal memory via the JTAG/EOnCE.
Flash Access Blocking Mechanism s 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 95 Prelimin ary EXAMPLE 1: If the system clock is the 8M Hz crystal freque ncy bec ause the PLL has not be en set up, the input clock will be below 12.8MHz, so PRDIV8=FM_CLKDIV[6]=0.
56F8322 T echncia l Dat a, Rev . 10.0 96 Free scal e S emic ondu cto r Preliminar y Part 8 General Purpose Inp ut/Output (GPIO) 8.1 Introduct ion This section is intende d to supplement the GPIO information f ound in the 56F8300 Peripheral User Manual and contains only chip-specific information.
Configuration 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 97 Prelimin ary Table 8-3 GPIO E xternal Signals Map Pins in shaded rows are not available in 56F8322 / 56F8122 Pins in i.
56F8322 T echncia l Dat a, Rev . 10.0 98 Free scal e S emic ondu cto r Preliminar y 8.3 Memory Maps The width of the GPIO port defines how many bits are implemented in each of the GPIO registers. Based on this and the default function of each of the G PIO pins, the reset values of the GPIOx_PUR and GPIOx_PER registers c hange from port to port.
General Characterist ics 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 99 Prelimin ary Part 10 Specifications 10.1 General Characteristics The 56F8322/56F8122 are fabr icated in high-density CMOS with 5V-tolerant TTL-compatible digital inputs.
56F8322 T echncia l Dat a, Rev . 10.0 100 Fr eesc ale Semi con duc tor Preliminar y Note: The 56F8122 device is specified to meet Industrial requirements only; PWM, CAN and Quad Decoder are NOT available on the 56F8122 device. Note: Th e o verall life of thi s d evice ma y b e reduce d if subjec ted to e xten ded use ove r 1 10°C jun ction.
General Characterist ics 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 101 Prelimin ary 1. Theta- JA determi ned on 2s2p test boar ds is freque ntly low er than would be obser ved in an application. Determined on 2 s2p the r- mal te st b oa rd .
56F8322 T echncia l Dat a, Rev . 10.0 102 Fr eesc ale Semi con duc tor Preliminar y Note: The 56F8122 device is guaranteed to 40MHz and specified to meet Indus trial requirements only; PWM, CAN and Quad Decoder are NOT available on the 56F8122 device.
DC Electrical Characteristi cs 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 103 Prelimin ary 10.2 DC Electrical C haracteristics Note: The 56F8122 device is specified to meet Industrial requirements only; PWM, CAN and Quad Decoder are NOT available on the 56F8122 device.
56F8322 T echncia l Dat a, Rev . 10.0 104 Fr eesc ale Semi con duc tor Preliminar y Table 10-6 Power-On Reset Low Voltage Parameters Charac teristic Symbol Min Typ Max Units POR Trip Point Ri sing 1 1. Both V EI 2.5 and V EI3. 3 thresho lds m ust be met for PO R to be relea sed on po wer-u p.
DC Electrical Characteristi cs 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 105 Prelimin ary 10.2.1 Voltage Regulator Specifi cations The 56F8322/56F8122 have two on-chip regulators.
56F8322 T echncia l Dat a, Rev . 10.0 106 Fr eesc ale Semi con duc tor Preliminar y Table 10-9. Re gulator Parameters Cha ract eri stic Symb ol M in Typi cal Ma x Unit Unloaded Output Voltag e (0mA Loa d) V RNL 2.25 — 2.75 V Loaded Output Voltage (200m A load) V RL 2.
AC Electri cal Characte ristics 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 107 Prelimin ary 10.2.2 Temperature Sense Note: Temperature Sensor is NOT available in the 56F8122 device. 10.3 AC Electrical Charact eristics Tests are conducted using the input levels specif ied in Table 10-5 .
56F8322 T echncia l Dat a, Rev . 10.0 108 Fr eesc ale Semi con duc tor Preliminar y Figure 10-1 Input Signal Measurement References Figure 10-2 shows the definitions of the following signal states: .
External Clock Operat ion Timing 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 109 Prelimin ary 10.5 External Clock Operat ion Timing Figure 10-3 Exter nal Clock Timing Table 10-13 External Clock Operation Timing Requirements 1 1. Param eters listed are gu arante ed by design.
56F8322 T echncia l Dat a, Rev . 10.0 110 Fr eesc ale Semi con duc tor Preliminar y 10.6 Phase Locked Loop Timin g 10.7 Oscillator Parameters Table 10-14 PLL Timing Charac teristic Symbol Min Typ Max Unit External re ference c rystal frequen cy for the PLL 1 1.
Oscillator Parameters 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 111 Prelimin ary Note: An LSB change in the tuning code results in an 82ps shift in the frequency period, while an MS B change in the tuning code results in a 4 1ns shif t in the frequ ency pe riod.
56F8322 T echncia l Dat a, Rev . 10.0 112 Fr eesc ale Semi con duc tor Preliminar y Figure 10-4 Frequency versus Temperature Frequency in MHz Temper ature - 50 - 30 - 10 + 10 + 30 + 50 + 70 + 90 + 110 + 130 + 150 7.
Reset, Stop, Wait, Mode Select, and Interrupt Timing 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 113 Prelimin ary 10.8 Reset, Stop, Wait , Mode Select, and Interrupt T iming Note: All address and data buses described he re are internal.
56F8322 T echncia l Dat a, Rev . 10.0 114 Fr eesc ale Semi con duc tor Preliminar y Figure 10-7 External Le vel-Sensitive Interrupt Tim ing Figure 10-8 Recovery from Stop State Using Asynchronous Inte.
Serial Peripheral Interface (SPI) Timing 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 115 Prelimin ary 10.9 Serial Peripheral Interfac e (SPI) Timing Table 10-18 SPI Timing 1 1.
56F8322 T echncia l Dat a, Rev . 10.0 116 Fr eesc ale Semi con duc tor Preliminar y 1 Figure 10 -9 SPI Maste r Timing (CPHA = 0) Figure 10-10 SPI Master Timing (CPHA = 1) SCLK ( CPOL = 0) (Output) SCL.
Serial Peripheral Interface (SPI) Timing 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 117 Prelimin ary Figure 10-11 SPI Slave Timing (CPHA = 0) Figure 10-12 SPI Slave Timing (CPHA .
56F8322 T echncia l Dat a, Rev . 10.0 118 Fr eesc ale Semi con duc tor Preliminar y 10.10 Quad Timer Tim ing Figure 10-13 Timer Timing 10.11 Quadratur e Decoder Timing Note: The Quadrature Decoder is NOT available in the 56F8122 device. Table 10-19 Timer Timing 1, 2 1.
Serial Communication Inter face (SCI) Timing 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 119 Prelimin ary Figure 10-14 Quadrature Decoder Timing 10.12 Serial Commun ication Interface (SCI) Tim ing Figure 10-15 RXD Pulse Width Figure 10-16 TXD Pulse Width Table 10-21 S CI Timing 1 1.
56F8322 T echncia l Dat a, Rev . 10.0 120 Fr eesc ale Semi con duc tor Preliminar y 10.13 Controller Area N etwork (CAN) Tim ing Note: CAN is NOT available in the 56F8122 device. Figure 10-17 Bus Wakeup Detect ion 10.14 JTAG Timing Table 10-22 CAN Timing 1 1.
JTAG Timing 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 121 Prelimin ary Figure 10-18 Test Clock Input Timing Diagram Figure 10-19 Te st A cces s Po rt Ti ming Diagr am TCK (Input.
56F8322 T echncia l Dat a, Rev . 10.0 122 Fr eesc ale Semi con duc tor Preliminar y 10.15 Analog-t o-Digital Converter ( ADC) Parameters Table 10-24 ADC Parameters Characteri stic Symbol M in Typ Max U nit Input vol tages V ADIN V REFL —V REFH V Resolution R ES 12 — 12 Bits Integral N on-Linearity 1 INL — +/- 2.
Analog-to-Digital Converter (ADC) Parameters 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 123 Prelimin ary Signal- to-noise plus distorti on ratio SI NA D — 5 9.1 — db Total Ha rmonic Dis tortion THD — 60.6 — db Spurious F ree Dyna mic Range SF DR — 6 1.
56F8322 T echncia l Dat a, Rev . 10.0 124 Fr eesc ale Semi con duc tor Preliminar y Figure 10-20 ADC Absolute Error Over Processing and Temperature Extremes Before and After Calibration for VDC in = 0.60V and 2.7 0V Note: The absolute error data shown in the graphs above r eflects the effects of both gain error and offset error.
Equivalent Circuit for ADC Inputs 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 125 Prelimin ary 10.16 Equivalent Circ uit for ADC Inp uts Figure 10-21 illustrates the ADC input circuit during sample and hol d. S1 and S2 are always open/closed at the same time that S3 is closed/open.
56F8322 T echncia l Dat a, Rev . 10.0 126 Fr eesc ale Semi con duc tor Preliminar y B, the internal [state-depe ndent component], reflects the supply current required by certain on-chip resources only when those resources are in use. These include RAM, Flash memory and the ADCs.
56F8322 Package and Pin-Out Informa tion 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 127 Prelimin ary Part 1 1 Packaging 11.1 56F8322 Package an d Pin-Out Informati on This section contains package and pin-out information for the 56F8322.
56F8322 T echncia l Dat a, Rev . 10.0 128 Fr eesc ale Semi con duc tor Preliminar y Table 11-1 56F8322 48-Pin LQFP Package Identification by P in Number Pin No.
56F8122 Package and Pin-Out Informa tion 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 129 Prelimin ary 11.2 56F8122 Package an d Pin-Out Informati on This section contains package and pin-out information for the 56F8122. This device comes in a 48-pin Low-profile Quad F lat Pack (LQFP).
56F8322 T echncia l Dat a, Rev . 10.0 130 Fr eesc ale Semi con duc tor Preliminar y Table 11-2 56F8122 48-Pin LQFP Package Identification by P in Number Pin No.
56F8122 Package and Pin-Out Informa tion 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 131 Prelimin ary Figure 11-3 48 -Pin LQFP Mechanica l Information A A1 Z 0.200 AB T-U 4X Z 0.200 AC T -U 4X B B1 1 12 13 24 25 36 37 48 S1 S V V1 P AE AE T, U , Z DET AIL Y DET AIL Y BASE MET AL N J F D T- U M 0.
56F8322 T echncia l Dat a, Rev . 10.0 132 Fr eesc ale Semi con duc tor Preliminar y Part 12 Design Co nsiderations 12.1 Thermal Desig n Considerations An estimation of the chip junction temperature, T.
Electrical Design Considerations 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 133 Prelimin ary The thermal c haracterization parame ter is measured per JESD51-2 specific ation using a 40-gauge t ype T thermocouple epoxied to the top center of the package case.
56F8322 T echncia l Dat a, Rev . 10.0 134 Fr eesc ale Semi con duc tor Preliminar y • Becaus e the devi ce’ s output si gnals have fast rise a nd fall ti mes, PCB trace lengths shoul d be minimal • Con sider all device loads as well as par asitic c apacitan ce due t o PCB tra ces when calculatin g capaci tance.
Power Distribution and I/O Ring Implementation 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 135 Prelimin ary Part 13 Ordering In formation Table 13-1 lists the pertinent information ne eded to place an order. Consult a Freescal e Semiconductor sales office or authorized distributor to determine availability and to order parts.
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