Freescale Semiconductor MPC8260取扱説明書

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MPC8260 P o werQ U ICC™ II F a mil y R ef eren ce Man u al Supports MPC8 250 MPC8 255 MPC8 260 MPC8 264 MPC8 265 MPC8 266 MPC826 0RM Re v . 2 , 12/2005.

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F r eescale™ and the Fr eescal e logo are trademark s of F rees cale Semicondu ctor, In c. The descri bed produc t contains a P owerP C processor core. The P owerPC na me is a t rademark of IBM Cor p. and used und er license. Al l other pr oduct or s ervic e names ar e the pro perty of their r espec tiv e own ers.

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P ar t I—Overview I Over view 1 G2 Cor e 2 Me mor y Ma p 3 P art II—Con f igur ation and Reset II System Interf ace U nit (SIU) 4 Reset 5 P art III—T h e Ha rd war e In t erf ace III External Si.

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I Part I —Overview 1 Over view 2 G2 Co re 3 Memor y Map II P art II—Configurat i o n and R eset 4 System Interf ace U nit (SIU) 5 Reset III P a rt II I—T he H ardware I nte rfa c e 6 External Signals 7 60x Signals 8 The 60x Bus 9 PCI Bridge 10 Cloc ks and P o wer Control 11 Memor y Con trol ler 12 Secondary (L2) Cache S uppor t 13 IEEE 1149.

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F ast Ethernet Controller 35 FCC HD LC Co nt rolle r 36 FCC T ranspar ent Controlle r 37 Serial P eripheral Interf ace ( S PI) 38 I 2 C Con tr olle r 39 P arall el I/ O P or ts 40 Register Qui ck R ef.

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35 F ast Ethernet Controller 36 FCC HDLC Controller 37 FCC T ransparent Controller 38 Serial P eripheral Interf ace (SPI) 39 I 2 C Controller 40 P arall el I/ O P or ts A Register Quic k Ref erence Gu.

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or v Co nte nts Par a g ra p h Number Title Pag e Number About This Book Reference Manual R evision History . ...................................................

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 vi F reescal e Semicondu ctor Co nte nts Par a g ra p h Number Title Pag e Number 1.7.2.5 PCI with 155-Mbps A TM .........................................................................

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or vii Co nte nts Par a g ra p h Number Title Pag e Number 2.5. 1 Po werPC E xcep tio n M odel . .. .... .... .. .... .... .. .... ..... .. .... .... .. .... ...

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 vi ii F reescal e Semi conducto r Co nte nts Par a g ra p h Number Title Pag e Number 4.3. 1.7 SIU Ex t e r nal In t e r ru p t Con t ro l Re g i st e r (S IEX R) ... .. .. .. .. .. .. .

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or ix Co nte nts Par a g ra p h Number Title Pag e Number 5. 4 .2 .2 S i ngl e Po w e rQUI CC II Con f igu re d f r o m Bo o t E P RO M ... .... .. .... .. .... .

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 x F reescal e Semicondu ctor Co nte nts Par a g ra p h Number Title Pag e Number 7.2.4.4.2 Global (GBL)—Input ..........................................................................

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or xi Co nte nts Par a g ra p h Number Title Pag e Number 8.2.2 60x-Compatible Bus Mode .........................................................................

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 xi i F reescal e Semicondu ctor Co nte nts Par a g ra p h Number Title Pag e Number 9.6 60x Bus Arbitration Priority . ... ............ .......... ..... ........ .......... ............ .

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or xiii Co nte nts Par a g ra p h Number Title Pag e Number 9.1 1.1.5 PCI Outbound Comparison M as k Registers (POCM Rx) ....... . ............................. 9-31 9.

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 xi v F reescal e Semicondu ctor Co nte nts Par a g ra p h Number Title Pag e Number 9.1 1.2 .27 P CI Con fig ura tion Reg ist er Acce ss in B ig-E nd ian M od e .. .. .... .... .. .... .

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or xv Co nte nts Par a g ra p h Number Title Pag e Number 9.13.1.6.2 DMA S tatus Register [0–3] ( DM ASRx) ....................................................

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 xvi F reescal e Semicondu ctor Co nte nts Par a g ra p h Number Title Pag e Number 10.6 Po werQ UIC C I I Int ern al Cl oc k Si gna ls . .... .... .. ..... .. .... .... .. .... .... .. .

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or xvi i Co nte nts Par a g ra p h Number Title Pag e Number 1 1 .4 S DRA M Ma ch i n e . .. .. .. .. .. .... .. .. .. .. .... .. .. .. .. .... .. .. .. ... .. .

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 xvi ii F reescal e Semicondu ctor Co nte nts Par a g ra p h Number Title Pag e Number 1 1 .6 . 1.4 Exce pt ion Re q u e sts ... .. .. .. .. .. .. .... .. .. .. .. .... .. .. ... .. .... .

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or xix Co nte nts Par a g ra p h Number Title Pag e Number Ch apter 13 IEEE 1 149.1 T es t Acce ss P or t 13.1 O ver vie w . .... .... .. .... .... .. .... .... .

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 xx F reescal e Semicondu ctor Co nte nts Par a g ra p h Number Title Pag e Number 14.6.7 RISC T imer Initialization Exa mple ... ...... .... ... .. ...... .... ...... .... ...... .... ..

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or xxi Co nte nts Par a g ra p h Number Title Pag e Number 16. 4.3 C MX SI 2 Cloc k Ro ute Reg iste r ( CMXSI 2C R) .... .... .. .. .... .... .... .. .. .... ...

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 xxi i F r e escale Semicondu ctor Co nte nts Par a g ra p h Number Title Pag e Number 19.5 . 2 Memo r y to/ fro m P erip h e r al T ra n s fe rs .. .. .. .. .. ... .. .... .. .. .. .. ..

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or xxiii Co nte nts Par a g ra p h Number Title Pag e Number 20.1 . 3 D a t a Syn c hro n i z at io n Reg i s te r (DS R ) .... .. .. .. ... .. .. .... .. .. .. .

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 xxi v F r e escale Semicondu ctor Co nte nts Par a g ra p h Number Title Pag e Number 21.18 SC C UAR T T ransmit Buff e r Descriptor (TxBD) ................... ...... ...... ........ ...

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or xxv Co nte nts Par a g ra p h Number Title Pag e Number 23.5 SCC BI SY NC C o m m a nd s .... .... .. .. .. .. .... .. .. .. .. .... ... .. .. .. .... .. .. .

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 xxvi F r e escale Semicondu ctor Co nte nts Par a g ra p h Number Title Pag e Number Ch apter 25 SCC Et her net Mode 25.1 Eth er net o n th e Po we rQU I CC I I . .... .. .. .. .. .... .

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or xxvii Co nte nts Par a g ra p h Number Title Pag e Number Ch apter 27 Ser ial Mana gement Contr oller s (SM Cs) 27. 1 Fea tures .... .... ...... .... .... .. .

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 xxvi ii F reescal e Semicondu ctor Co nte nts Par a g ra p h Number Title Pag e Number 27. 4.1 1 SM C T ran spare nt NMSI Pro gra mming Exa mpl e ... .... .. .... .... .... .. .. .... ..

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or xxix Co nte nts Par a g ra p h Number Title Pag e Number 28.3 . 4.3 SS7 Con f i gura t i o n Re g i s ter— S S 7 Mo d e .... .. .. .. .. .... .. .. .. .. ..

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 xxx F reescal e Semicondu ctor Co nte nts Par a g ra p h Number Title Pag e Number Ch apter 29 F as t Commun ica ti ons C ontrol lers ( FCC s) 29.1 O ver vie w . .... .... .. .... .... .

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or xxxi Co nte nts Par a g ra p h Number Title Pag e Number 30.2.1.4 AAL2 T ransmitter Overview ...................... . ........................................

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 xxxi i F r e escale Semicondu ctor Co nte nts Par a g ra p h Number Title Pag e Number 30.6.1 A TM-Layer OAM Definitio ns ........................ . ......................... ...........

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or xxxi ii Co nte nts Par a g ra p h Number Title Pag e Number 30.1 0 . 2.3 . 5 AAL2 P roto c o l - Sp e ci f ic TCT .. .... .. .. .. .. ..... .. .. .. .. .... .

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 xxxi v F r e escale Semicondu ctor Co nte nts Par a g ra p h Number Title Pag e Number 30.12.2.3 UT O PIA Loop-Back M odes . ................ ................................. ..........

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or xxxv Co nte nts Par a g ra p h Number Title Pag e Number 31.8 AAL- 1 Mem o r y Stru ct ure ... .. .. .. .. .... .. .. .. .. .. .. .... .. ... .. .. .... .. ..

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 xxxvi F r e escale Semicondu ctor Co nte nts Par a g ra p h Number Title Pag e Number 32.4 . 1 R ec e iv e r O v er vi ew . .. .. .. .. .. .... .. .. .. .. .... .. .. .. .. .. .. ..... .

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or xxxvii Co nte nts Par a g ra p h Number Title Pag e Number 33.3 . 2.4 Differ en c e s in CT C O p era tio n .. .... .. .. .. .. .. .. ... .. .. .... .. .. .. .

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 xxxvi ii F reescal e Semi conducto r Co nte nts Par a g ra p h Number Title Pag e Number 33.4 . 6.2 Delay Co m p e n sa tion Bu ff ers (D CB ) .. .. .. ..... .. .. .. .. .... .. .. .. ..

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or xxxi x Co nte nts Par a g ra p h Number Title Pag e Number 33.5.4.3.2 As Responder (RX) ............................ .........................................

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 xl F reescal e Semicondu ctor Co nte nts Par a g ra p h Number Title Pag e Number 34.4 . 2.1 TC Lay er Gene ral Ev e nt Reg i s te r ( TCG ER) ... .. .. .. .. .... .. .. .. .. .... .. ..

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or xli Co nte nts Par a g ra p h Number Title Pag e Number 35.1 5 Han dli ng C olli si ons .. .. .... .... .. .... .. .... .... .. .... .... .. ..... .... .. ...

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 xl ii F reescal e Semi conducto r Co nte nts Par a g ra p h Number Title Pag e Number 38.3 . 1 Th e S P I as a Mas te r De v i c e .. .. .. .. .. .. .... .. .. .. .. ..... .. .. .. .. ..

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or xlii i Co nte nts Par a g ra p h Number Title Pag e Number Ch apter 40 P arallel I/O P orts 40. 1 Fea tures .... .... ...... .... .... .. .... .... .... .. ..

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 xl iv F reescal e Semi conducto r Co nte nts Par a g ra p h Number Title Pag e Number.

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or xlv Figures Fig ur e Number Title Pag e Number 1-1 P owerQ UIC C I I B loc k Di agr am .. .... .. .... .... .. .... .... .. ..... .... .. .... .... .. .... ..

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 xl vi F r e escale Semicondu ctor Figures Fig ur e Number Title Pag e Number 4-19 Int err upt T ab le Han dli ng E xam ple . .... .... .. .... .... .. .... .. ..... .... .. .... .... .. .

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or xlvii Figures Fig ur e Number Title Pag e Number 8-9 2 8-Bi t E xte nded T ransf er to 32 -Bit Po rt Siz e .... .. .... ..... .. .... .. .... .... .. .... ...

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 xlv iii F reescal e Semiconducto r Figures Fig ur e Number Title Pag e Number 9-36 PCI Bus Statu s Re gis ter ... .. .... .... .. .... .... .. .... .... .. .... .... ... .... .... .. ...

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or xl ix Figures Fig ur e Number Title Pag e Number 9-77 Inbound Message Inter rupt S ta t us Register (I MISR)..................................................

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 l F reescal e Semicondu ctor Figures Fig ur e Number Title Pag e Number 1 1-22 CL = 2 (2 Cl ock Cy cles) .. .. .... .... .. .... .. .... .... .. .... .... .. ..... .... .. .... .... .. .

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or li Figures Fig ur e Number Title Pag e Number 1 1-63 CS Si gnal Se lec tio n .. .... .. .... .... .. .... .... .. .... .... .. .... .... .. ..... .. .... ....

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 lii F reescal e Semicondu ctor Figures Fig ur e Number Title Pag e Number 14-8 Dua l-Po rt R AM Mem ory Map . .... .. .... .. .... .... .. .... .... .. ..... .... .. .... .... .. .... ..

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or liii Figures Fig ur e Number Title Pag e Number 17-2 Baud -Rat e Gener ato r C on figur ati on R eg ister s (BRGC x) . .. .... .... .. .... .... .. .... .... .

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 liv F reescal e Semicondu ctor Figures Fig ur e Number Title Pag e Number 21-5 Asynchronous UAR T T rans mitter ... ................................................... ..................

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or lv Figures Fig ur e Number Title Pag e Number 25-4 Ethernet Address Recognition F lowc hart ..................................................... ............

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 lvi F r e escale Semicondu ctor Figures Fig ur e Number Title Pag e Number 28-1 4 T ra n s mi tte r Sup e r Cha n n e l Ex a mple . .. .. .. .. .. .. .. .... .. .. ... .. .... .. .. .. .

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or lvi i Figures Fig ur e Number Title Pag e Number 30-22 VC I Filterin g En able Bits ............. ...... .... ...... .... ...... ... .. .... ...... .... .....

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 lviii F r e escale Semicondu ctor Figures Fig ur e Number Title Pag e Number 30-6 3 COM M_I NFO Fie ld .. .. .... .... .. .... .... .. .... .... .. .... .... .. .... ..... .. .... .... .

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or lix Figures Fig ur e Number Title Pag e Number 32-7 CPS Tx Queu e Des cri ptor (T xQD ) .... .. .... .... .. .... .... .. ..... .... .. .... .. .... .... .. .

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 lx F reescal e Semicondu ctor Figures Fig ur e Number Title Pag e Number 33-23 I M A T r ansmit Inte rrupt Sta tus ( ITINTST A T) ......... ........... .................... .............

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or lxi Figures Fig ur e Number Title Pag e Number 36-9 FCC Sta t u s Re g i st e r (FCC S) .... .. .. .... .. .. .. .. .. .. .... .. .. .. .. ..... .. .. .. .. .

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 lxii F r e escale Semicondu ctor Figures Fig ur e Number Title Pag e Number.

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or lxii i Ta b l e s Ta b l e Number Title Pag e Number i Changes to M PC8260 Fami ly Reference Manual, Rev . 1 .................................................

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 lxiv F r e escale Semicondu ctor Ta b l e s Ta b l e Number Title Pag e Number 4-23 PIT R Fie l d D e s crip t i ons . .. .. .. .. .. .... .. .. .. .. .. .. .... .. .. .. .. .. .. ..... .

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or lxv Ta b l e s Ta b l e Number Title Pag e Number 9-16 PIT ARx Fi el d D e s crip t ion s .... .... .. .. .. .. .. .. .... .. .. .. .. .... .. ... .. .. .... .

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 lxvi F re escale Sem icondu ctor Ta b l e s Ta b l e Number Title Pag e Number 9-57 OP TP R F ie ld Des c r ip t i o n s . .. .. .. .. .... .. .. .. .. .... .. .. .. .. .... .. ... .. ..

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or lx vii Ta b l e s Ta b l e Number Title Pag e Number 1 1-21 SDRAM Address Mult iplexing (A16–A31) .. ......................................... .............

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 lxv iii F reescal e Semiconducto r Ta b l e s Ta b l e Number Title Pag e Number 15-4 SIx G M R Fiel d D esc ri p t i o n s . .. .. .. .. .. .... .. .. .. .. .. .. .... .. .. .. ... .. .

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or lxix Ta b l e s Ta b l e Number Title Pag e Number 20-2 GS MR_L F iel d Desc rip tio ns . .... .... .. .... .... .. .... .... .. .... ..... .. .... .. .... ..

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 lxx F r e escale Semicondu ctor Ta b l e s Ta b l e Number Title Pag e Number 23-1 0 PSM R Fie l d D e s crip t ion s . .. .. .. .. .. .. .. .... .. .. .. .. .... .. .. .. .. .. ... ....

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or lxxi Ta b l e s Ta b l e Number Title Pag e Number 27-1 7 S MC GC I Para m eter RAM Me mory Map .. .... .. .... .. ..... .... .. .... .... .. .... .... .. ...

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 lxxi i F reescal e Semicondu ctor Ta b l e s Ta b l e Number Title Pag e Number 30-7 Fie lds a n d th eir Posi tio ns in R M Cells . .... .. .... .... .. .... ..... .. .... .... .. .... .

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or lxxi i i Ta b l e s Ta b l e Number Title Pag e Number 30-4 8 FCCE /FC CM Fie ld De scr ip tions . .. .... .... .... .. .... .... .. ..... .... .. .... .... .

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 lxxi v F reescal e Semicondu ctor Ta b l e s Ta b l e Number Title Pag e Number 33-9 ICP Ce ll T emp lat e ... .. .... .... .. .... .... .. .... .... .. .... .... .. .... ..... .. .... .

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or lx xv Ta b l e s Ta b l e Number Title Pag e Number 35-9 FCCE /FC CM F iel d De scr ipt ions . .... .. .... .... .... .. .... .... ... .... .... .. .... .... .

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 lxxv i F r e escale Semicondu ctor Ta b l e s Ta b l e Number Title Pag e Number A-2 User- Leve l P owe rP C SPRs .... .... .. .... .. .... .... .. .... .... .. ..... .... .. .... .... .

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or lxxv ii About This Book The prima ry object ive of this manua l is to help co mmuni cations system designer.

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 lxxv iii F reescale Sem icondu ctor Us Some descri ptions in this manual pertain only to sp ecific devices or to all devices in a specific silicon revision. T able ii pr ovides examples of how t he se descriptions are indicated.

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or lxxi x Be f or e Us ing th is Manu al— Imp or tan t Note Before us ing this manual, de termine whe ther i t is the latest revision and if ther e are errata or addenda.

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 lxxx F re escale Sem icondu ctor • Part III, “The Hardware Inter f ace, ” des cribes exter nal signals, cl ocking, memory control, and power manage m ent of the PowerQUICC II.

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or lxxxi — Chapter 22, “ SCC HDLC M ode,” describes the PowerQUICC II imple mentation of HDLC protocol.

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 lxxx ii F reescal e Semicondu ctor MC68360, the MC68302, the M68HC1 1, and M68HC05 microcontro ller families, and peripheral devices such as EE PROMs, real-time clocks, A/D converters, and ISDN devices.

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or lx xxi ii • Application notes—These short documents contain us eful i nf ormation about specific design issues useful to programmer s and engineers wor king with Free scale’ s pr ocessors.

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 lxxx iv F reescal e Semicondu ctor BIST Buil t-in se lf tes t BPU Br anch proce ssing unit BR I Ba sic rate inte rface.

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or lxxx v IEEE Inst itute of El ectrical and Electro ni c s Engineers IrD A Infr ared Dat a Associ ati on ISDN.

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 lxxx vi F r e escale Semicondu ctor SCC Serial c ommuni cati on control ler SCP Seri al c ontrol por t SDLC Synchro nous Data Link Cont.

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or lxxx vii P o werPC Ar chit ectu re T erminolo g y Con venti ons T able iv lists certain te r ms used in this manual that differ from the ar chitecture terminology conve nt ions.

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 lxxx viii F reescale Sem icondu ctor.

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or I-1 Pa r t I Over v iew Intended A udi ence Part I is intended for r eaders who ne ed a high-level understanding of the PowerQUI CC II.

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 I-2 F reescal e Semicondu ctor Acron yms and Abbr e v iations Ta b l e I - 1 contains a cronyms and abbreviations that are used in this document.

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or I-3 MII Media-in dependent i nterf ace MMU M emory man agement un it MSR Mach ine st ate reg ister NMSI Non.

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 I-4 F reescal e Semicondu ctor.

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 1-1 Chapter 1 Over v iew The Powe rQUICC I I ™ is a ve rsatile communi c ations pr oce ssor t hat integra.

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Ov ervie w MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 1-2 F re escale Sem icondu ctor — Floating-point unit (FPU) supports floating-point arithmetic. — Support for ca che locking. • Low-power consumption • Separate powe r supply for inter nal logic (2.

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Ov ervie w MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 1-3 — Three user programmable machines, general-pur pose chip -select machi ne, and page mode .

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Ov ervie w MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 1-4 F re escale Sem icondu ctor – T ranspar ent – UAR T (low-speed oper ation) — One serial per ipheral interface iden.

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Ov ervie w MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 1-5 – Performing HEC erro r detection and single bit error correction (p rogrammable by user) .

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Ov ervie w MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 1-6 F re escale Sem icondu ctor — Supports the I 2 O standar d — Hot-Swap friendly ( s upports the Hot Swap Sp ecification as defined by PI CMG 2.1 R1. 0 August 3, 1998) — Support for 66 MHz, 3.

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Ov ervie w MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 1-7 Figure 1-1. P owerQUICC II Block Diag ram Both the system core and the CPM have an in terna l PLL, which allows independent optimization of the frequencies at which they run.

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Ov ervie w MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 1-8 F re escale Sem icondu ctor The G2 core has an internal common on- chip (COP) debug processor . This pr ocessor allows ac cess to internal scan chains for debugging pur poses.

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Ov ervie w MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 1-9 1. 2.3 Co mmun ica tion s Pr oces sor Mo dule (CPM ) The CP M contains features that al low t he PowerQUI CC II to exce l in a variety of a pplicati ons targeted mainly for ne tworkin g and telec ommunication markets.

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Ov ervie w MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 1-10 F re escale Sem icondu ctor PowerQUICC II initialization c ode requires changes from the M PC860 initialization code (F r eescale provides refer ence code). 1.3.1 S igna ls Figure 1- 2 shows PowerQUICC II s i gnals grouped by f unc ti on.

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Ov ervie w MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 1-11 F igu re 1 -2 . Pow erQ UI CC II Ex te rn al Si gna ls VCCSYN/GNDSYN/VCCSYN1//VDDH/ VDD/ VSS ⎯⎯⎯> 100 6 0 x B U S 32 <⎯ ⎯> A [0– 31] PC I_P AR 1 / L_A 14 1 MPC825 0, MPC8265, and MPC8 266 only .

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Ov ervie w MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 1-12 F re escale Sem icondu ctor 1.4 Diff erences betw een MPC860 and P ow erQUICC II The following M PC860 features are not included in the PowerQUICC II.

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Ov ervie w MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 1-13 1.6 P owe rQUIC C II Co nfi gur atio n s The Powe rQUICC I I offe rs f lexibility in conf iguring the device for specific appl ications.

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Ov ervie w MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 1-14 F re escale Sem icondu ctor Ta b l e 1 - 3 shows serial performance for t he MP C8250, which does not support A TM (155- Mbps). FCCs can also be used to run slower HDLC or 10 BaseT , for example.

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Ov ervie w MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 1-15 Figure 1-3. Remote Access Server Co nfi gur ati on In this application, eight TDM ports are connec ted to external frame rs. In the PowerQUICC II, e ach group of fou r ports sup port up to 128 channels .

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Ov ervie w MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 1-16 F re escale Sem icondu ctor 1.7.1.2 Regional Office Router Figure 1- 4 shows a regional office router configur ation (refer to note at the beginning of Sec tion 1. 7, “Application E xamples” ).

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Ov ervie w MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 1-17 Figu re 1-5. LA N-to -W A N Bridg e Ro uter Con figura tion 1.7.1.4 Cellular Base Station Figure 1- 6 shows a cellular ba se station c onfiguration (refer to note at the beginning of Section 1.

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Ov ervie w MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 1-18 F re escale Sem icondu ctor Here the PowerQUICC II c hannelizes two E1s (up to 256, 16- Kbps channels).

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Ov ervie w MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 1-19 Fi gure 1-8 . SON ET T ran smis s i on C ont r ol ler Con fig ura ti on In this application, the PowerQUICC II im plemen ts super channeling with the MCC.

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Ov ervie w MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 1-20 F re escale Sem icondu ctor core. The CP can store large data frames in the local memory without interfering with the operation of the system core. (Refer to not e at the beginning of Section 1.

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Ov ervie w MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 1-21 Serial thr oughput is enhanced by conne cting one P owe r QUICC II in mas ter or s lave mode ( wit h system core ena bled or disabled) to a nother PowerQUICC II in master mode with the cor e enabled.

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Ov ervie w MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 1-22 F re escale Sem icondu ctor Figure 1-12. PCI Configu ration In this system the local bus is configured as PCI (33-MHz 32-bit data bus version 2.1). The PowerQUI CC II can be configured as a host or a s an agent on the PCI bus.

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Ov ervie w MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 1-23 to store A T M connection tables. T herefore, an ext ernal PCI bridge is necessar y .

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Ov ervie w MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 1-24 F re escale Sem icondu ctor.

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 2-1 Chapter 2 G2 Core The PowerQUICC II contains a n embedded version of the MPC603e™ micr oprocessor . This cha pt er provides an overview of the basic functionality of th e pr ocessor core.

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G2 Core MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 2-2 F re escale Sem icondu ctor Figure 2-1. Po w erQUICC II I ntegrated Processo r Core Bloc k Di agram 64- Bi t 64-Bit (T wo I.

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G2 Core MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 2-3 The pr ocessor cor e is a supe r scalar pr ocessor t hat can issue and r etire as m any as three instr u cti ons per clock.

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G2 Core MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 2-4 F re escale Sem icondu ctor — LSU for da t a transfer betwe en data cac he and GPRs and FPRs — SRU that execute s condi.

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G2 Core MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 2-5 Figure 2- 1 shows how the e xecution units—IU, BPU, L S U, and SRU — ope rate independently and in parallel.

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G2 Core MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 2-6 F re escale Sem icondu ctor The BPU contains an adder to compute branch target addresses and three user - control registers—the link register (LR), the count register (CTR), and the CR .

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G2 Core MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 2-7 Load and store instructions ar e issued and transl ated in program order; however , the actual memory accesse s c an occur out of order . S ync hronizing instructions are provided to enf orc e strict ordering where needed.

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G2 Core MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 2-8 F re escale Sem icondu ctor and data. T he MMUs also control access pri v ilege s for these s paces on block and page granularities.

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G2 Core MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 2-9 Note that there may be regist e rs common to other proc essors that implement the PowerPC arc hitecture that are not im pleme nted in the PowerQUICC II’ s pr oc essor core.

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G2 Core MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 2-10 F re escale Sem icondu ctor Fig ure 2-2. P ow erQUI CC I I Progra mmi ng M odel —Re giste r s DSISR SPR 18 DSISR Data Ad.

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G2 Core MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 2-11 2.3.1.2 P owerQUICC II-Specific Registers The set of registers specific to the MPC603e are also shown in Figure 2-2 .

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G2 Core MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 2-12 F re escale Sem icondu ctor 7 P AR Disab le prechar ge of ARTR Y . 0 Precharge of ART R Y ena bled 1 Alters b us protoc ol sl ightl y by pre v ent ing the proce ssor from driving AR T R Y to high (neg ated) stat e, allowi ng multiple ARTR Y signals to be tied to get h er.

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G2 Core MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 2-13 18 IL O CK Inst ructio n cache l ock 0 Nor mal operati on 1 Instructio n cache i s l oc ked. A lo cked cache su pplie s data normally on a hit, b ut an access i s trea t ed as a cache- inhibit ed tran saction o n a mi ss.

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G2 Core MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 2-14 F re escale Sem icondu ctor 2. 3.1.2. 2 Hard ware Impl ementa tion-De pendent Re gist er 1 (HID1) The Powe rQUICC I I impleme ntation of HI D 1 is shown in Figure 2-4 . Ta b l e 2 - 2 shows the bit definitions for HID1.

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G2 Core MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 2-15 2. 3.1.2. 4 Pro cessor V er sion R egister (PVR) Software can i dentify the PowerQUICC II’s pr oce ssor core by reading the pr oces sor version register (PVR).

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G2 Core MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 2-16 F re escale Sem icondu ctor 2.3.2.2 P owerPC Instruction Set The PowerPC instructions are divided into the following categories: • Integer instructions—These include arithmetic and logical instructions.

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G2 Core MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 2-17 Integer instructions o pe rate on byte, half -word, and word ope r ands. The Power PC architecture uses instructions that are f our bytes long and wor d-al igne d.

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G2 Core MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 2-18 F re escale Sem icondu ctor 2.4. 1 P owe rPC Cach e Mo del The Pow erPC archit ecture does not define hardwar e aspects of cache imp lementations .

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G2 Core MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 2-19 Figure 2-6. Data Cache Organization Because the processor co re data cache tags are si ngle-ported, simultaneous load or store and snoop accesses caus e r esource contention.

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G2 Core MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 2-20 F re escale Sem icondu ctor tenures of a read oper ation). Because the processor can dynamically optimize run-time ordering of load/store traffic, over all performance is im proved.

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G2 Core MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 2-21 2.5 Excepti on Model This section describes the PowerPC exception model and implementation-s pe cific details of the Powe r Q UI CC II core . 2.5 .

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G2 Core MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 2-22 F re escale Sem icondu ctor exception is taken due to a trap or system call inst ruction, execution r esumes at an addr ess provided by the handler .

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G2 Core MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 2-23 Machine chec k 00200 A machine che c k is caused b y t he assertion of th e TEA signa l during a data bus tr ansaction , asse r tion of MCP , or an addres s or data parity er r or .

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G2 Core MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 2-24 F re escale Sem icondu ctor Progr am 00700 A progr am exc eption is caus ed by one of t he fol lowing e xcepti on conditio.

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G2 Core MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 2-25 2.5. 3 E xcep tion Prio riti es The e xception pr iorities for the proces s or core a re unchanged fr om those desc ribed in the G2 Core r efer enc e Manual exc ept for th e alignment exception, whos e causes ar e priori tized as follows: 1.

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G2 Core MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 2-26 F re escale Sem icondu ctor TLB with memory . In the PowerQUI CC II, the processor c ore’ s TLBs ar e 64-entry , two-way set-as sociative caches th at contai n instruction and da t a addr ess tr anslations.

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G2 Core MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 2-27 2.7 Instructio n Timing The process or core is a pipelined s uperscalar process or . A pipelined processor is one in whic h the processi ng of an i nstruction is broken into dis crete stages.

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G2 Core MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 2-28 F re escale Sem icondu ctor 2.8 Diff erences betw een the P o werQUI CC II’ s G2 Core and the MPC603e Mic r opr ocessor The PowerQUICC II’ s pr oc essor core is a deriva tive of the MPC603e microprocessor design.

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 3-1 Chapter 3 Mem ory Map The PowerQUIC C II’ s inter nal memory resources ar e mapped within a contiguous block of memor y . The size of the internal s pace is 128 Kbytes.

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Memo ry Map MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 3-2 F re escale Sem icondu ctor 0x10029 Reserved — 24 bits — — 0x1002C 60x b us ar bitr ati on-le vel r egister high (first 8 client s) (PPC_ALRH) R/W 32 bits 0x0126_34 57 4.

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Memo ry Map MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 3-3 0x1012C Option regist er bank 5 ( OR5) R/W 32 bi t s undefined 11.3.2/ 11-15 0x10130 Base r egister bank 6 (BR6) R/W 32 bi ts 0x0000_00 00 11 .

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Memo ry Map MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 3-4 F re escale Sem icondu ctor 0x101A5 Reserved — 24 bits — — 0x101A8 Internal memo r y map reg ister (I M MR) R/W 32 bits reset conf i g uration 4.3. 2. 7/ 4-36 0x101A C PCI base register 0 (PCIBR0) 2 R/W 32 bits 0x0 000_00 00 4.

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Memo ry Map MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 3-5 0x10458 Outbound m ess age regis t er 0 (OMR0) 2 R/W 32 bits undefi ned 9. 12. 1.2 /9- 66 0x1045C Outbound mess age register 1 (OMR1 ) 2 R/W 32 bits undefi ned 9.

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Memo ry Map MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 3-6 F re escale Sem icondu ctor 0x10608 DMA 2 cu rrent descri pt o r addr ess regi ster (DMA CD AR2) 2 R/ W 32 bits 0x0 000_00 00 9.13.1.6 .3/9-91 0x10610 DMA 2 so urce ad dress register ( DMASAR2) 2 R/W 32 bits 0x0 000_00 00 9.

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Memo ry Map MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 3-7 0x108E0 PCI inbou nd compari son mask r egist er 1 (PIC MR1) 2 R/W 32 bits 0x0000_00 00 9.11. 1.17/9-43 0x108E8 PCI inbou nd tr anslat ion addr ess registe r 0 (PIT AR0) 2 R/W 32 bits 0x0000_00 00 9.

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Memo ry Map MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 3-8 F re escale Sem icondu ctor 0x10D0C P or t A open drain re gi s t er (PODRA) R/W 32 bits 0x0000_00 00 40.2.1/40 - 1 0x10D10 P or t A data regist er (PD A T A) R/W 32 bits 0x0000_00 00 40.

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Memo ry Map MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 3-9 0x10D98 Timer 1 captur e regi ster (TCR1) R/W 16 bits 0x0000 18.2.5 / 18 - 7 0x10D9 A Timer 2 capt ure regi ster ( TCR2) R/W 16 bits 0x0000 18.

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Memo ry Map MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 3-10 F re escale Sem icondu ctor 0x11030 IDMA 3 e ven t register (I DSR3) R/W 8 b its 0x00 19 .8.4/ 19-24 0x11031 Reserved — 24 bits — — 0x11034 IDMA 3 mask re gister (I DM R3) R/W 8 bit s 0x00 19.

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Memo ry Map MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 3-11 0x11319 Reserved — 24 bits — — 0x1131C FCC1 tran smi t internal rat e regis ters f or PHY0 (FTIRR1_ PHY0) R/W 8 b i t s 0x00 30.13.4/30 -91 (A TM) 3 3.

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Memo ry Map MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 3-12 F re escale Sem icondu ctor 0x1133C FCC2 tran smi t internal rat e regis ters f or PHY0 (FTIRR2_ PHY0) R/W 8 b i t s 0x00 30.

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Memo ry Map MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 3-13 TC Lay er 1 4 0x11400 TC1 mode regis t er (TCMODE1) 4 R/W 16 bits 0x0 000 3 4.4.1 . 1/ 34-7 0x11402 TC1 cel l deli neati on state machine regi ster (CDSMR1) 4 R/ W 16 bits 0x0000 34.

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Memo ry Map MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 3-14 F re escale Sem icondu ctor 0x1144C TC3 correcte d cells counte r (TC_CCC3 ) 4 R/W 16 bits 0x0 000 34.4. 3. 4/ 34-12 0x1144E TC3 idle cells coun ter (TC_ICC3) 4 R/W 16 bits 0x0000 34.

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Memo ry Map MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 3-15 0x114A2 TC6 cel l deli neati on state machine r egister ( CDSMR6) 4 R/W 16 bits 0x0000 34.4 .1.2 / 34- 9 0x114A4 TC6 ev ent regis ter (TCER6) 4 R/W 16 bits 0x0 000 34.

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Memo ry Map MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 3-16 F re escale Sem icondu ctor 0x114F2 TC8 error cells cou nter (TC_ ECC8) 4 R/W 16 bits 0x0 000 34.4. 3.3/34- 12 0x114F4 Reser v ed — 12 b ytes — — TC Lay er—General 4 0x11500 TC general status regist er ( TCGSR) 4 R 16 bits 0x0 000 34.

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Memo ry Map MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 3-17 0x119D6 CP timers ev ent regi ster (R TER) R/W 16 bits 0x0000_00 00 14 .6.4/ 14-24 0x119D A CP timers mask regi ster ( RTMR) R/W 16 bits 0x0 000_0000 0x119DC CP time-stamp t i mer cont r ol regi ster (R TSCR) — 16 bits 0x0 000 14.

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Memo ry Map MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 3-18 F re escale Sem icondu ctor 0x11A17 SCC1 status regist er (SCCS1) R/W 8 bits 0x 00 21.

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Memo ry Map MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 3-19 0x11A37 SCC2 status regist er (SCCS2) R/W 8 bits 0x 00 21.

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Memo ry Map MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 3-20 F re escale Sem icondu ctor 0x11A57 SCC3 status regist er (SCCS3) R/W 8 bits 0x 00 21.

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Memo ry Map MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 3-21 0x11A78– 0x11A7F Reserved — 8 bytes — — SMC1 0x11A82 SMC1 mode r egist er ( SMC MR1) R/W 16 bits 0x0000 27.2.1/27 - 2 0x11A84 Rese r ved — 16 bits — — 0x11A86 SMC1 ev ent regi ster (SMCE1) R/W 8 bits 0x00 27.

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Memo ry Map MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 3-22 F re escale Sem icondu ctor 0x11B03 Reserved — 8 b i t s — — 0x11B04 CPM m ux FCC cloc k rout e regist er ( CM X FCR) R/W 32 bits 0x0 000_00 00 16.4. 4/16- 13 0x11B08 CPM m ux SCC cloc k rout e regist er (CMXSCR) R/W 32 bi ts 0x0000_00 00 16.

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Memo ry Map MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 3-23 SI2 Register s 0x11B40 SI2 TDMA2 mode regi st e r (SI2AM R) R/W 16 bits 0x0 000 15.

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Memo ry Map MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 3-24 F re escale Sem icondu ctor 0x12C00– 0x12DF F SI 2 receiv e rout i n g RAM (SI2RxRAM) R/W 512 byt es undefi ned 15.

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or II-1 Pa r t I I Conf iguration an d Reset Intended A udi ence Part II is intended for system de signers and programmers who ne ed to understand the operation of the PowerQUICC II at start up.

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 II-2 Fre escale Semi conducto r example , MSR[LE] refer s to the little-e ndian mode e nable bit i n the machine state register . x In certain contexts, such as in a signal encoding or a bi t f ield, indicates a don’t care.

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 4-1 Chapter 4 System Interface Unit (SIU) The system i nterface unit (SIU) consists of s e veral func tions that control s ystem start-up and initialization, as well a s operation, protection, and t he external system bus.

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Sy ste m Inte rfac e Unit ( SIU) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 4-2 F re escale Sem icondu ctor generates the clock signals used by the SIU and other Power QUICC II modules. The SIU clocking s cheme supports stop and nor mal modes.

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Sy st em In terf ace Uni t (S IU ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 4-3 Figure 4- 2 is a block diagr am of the s ys tem configur ation and protection logi c .

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Sy ste m Inte rfac e Unit ( SIU) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 4-4 F re escale Sem icondu ctor Figure 4-3. Timers Clock Generation For deta ils, see Section 40.

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Sy st em In terf ace Uni t (S IU ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 4-5 Figure 4-4. TMCNT Block Di agram Section 4.3.2.15, “Ti me Counter Register (TMCNT),” describes the time counter reg ister .

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Sy ste m Inte rfac e Unit ( SIU) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 4-6 F re escale Sem icondu ctor This gives a range from 122 µ s (PITC = 0x0000) to 8 seconds (PITC = 0xFFFF).

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Sy st em In terf ace Uni t (S IU ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 4-7 Figure 4-7. Software W atchdog Time r Block Diagra m In Figure 4-7 , the ra nge is de termined by SYP C R[S WTC]. The value in SW TC is then loaded into a 16- bit decrementer clocke d by the s ystem clock.

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Sy ste m Inte rfac e Unit ( SIU) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 4-8 F re escale Sem icondu ctor 4. 2.1 Inte rrupt Co nfigura tion Figure 4- 8 shows the PowerQUI CC I I interr upt structure.

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Sy st em In terf ace Uni t (S IU ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 4-9 If the s oftware watchdog timer is programmed to g ene r ate an interrupt, it always generates a ma chine check i nterrupt to the core.

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Sy ste m Inte rfac e Unit ( SIU) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 4-10 F re escale Sem icondu ctor relati ve orderi ng of the interrupts, but, in ge ner al , relative priorities are as shown. A single interrupt priority number is assoc ia ted with each table entry .

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Sy st em In terf ace Uni t (S IU ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 4-11 27 YCC8 (Groupe d) Y es 28 XSIU4 ( Spread) No (TMCNT ,PIT ,PCI 1 = .

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Sy ste m Inte rfac e Unit ( SIU) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 4-12 F re escale Sem icondu ctor Notice the lack of SDMA interrupt sources, which are reported through each individual FCC, S CC, SMC, SPI, or I 2 C channel.

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Sy st em In terf ace Uni t (S IU ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 4-13 • Spread. In the spread scheme , prioritie s are spread over the table so other sou rces can have lower interrupt latencies.

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Sy ste m Inte rfac e Unit ( SIU) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 4-14 F re escale Sem icondu ctor Figure 4-9. Interrup t Request Masking 4. 2.4 Inte rrupt V ector Genera tion an d Calc ulati on Pending unmasked interrupts ar e presented to the core in order of priority .

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Sy st em In terf ace Uni t (S IU ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 4-15 6 IDMA1 0b00 _0110 7 IDMA2 0b00 _0111 8 IDMA3 0b00 _1000 9 IDMA4 0b.

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Sy ste m Inte rfac e Unit ( SIU) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 4-16 F re escale Sem icondu ctor Note that the interrupt vector ta ble diff ers fr om the interr upt p.

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Sy st em In terf ace Uni t (S IU ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 4-17 Requests can be masked independently in the i nte rrupt ma sk register (SIMR). Notice that the global SI MR is cleared on system reset s o pins left floating do not cause false interrupts.

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Sy ste m Inte rfac e Unit ( SIU) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 4-18 F re escale Sem icondu ctor The SI CR register bits ar e described in Ta b l e 4 - 4 .

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Sy st em In terf ace Uni t (S IU ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 4-19 4.3.1.3 CPM Interrupt Priority Registers (SCPRR_H an d SCPRR_L) The CPM high inter rupt priority register (SC PRR_H) , shown in Figure 4-12 , define prioritie s between the FCCs and MCCs.

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Sy ste m Inte rfac e Unit ( SIU) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 4-20 F re escale Sem icondu ctor The CPM low interrupt priority re gister (SCPRR_L), shown in Figure 4-13 , defines pr ioritization of SCCs and TC layer .

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Sy st em In terf ace Uni t (S IU ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 4-21 4.3.1.4 SIU Interrupt Pe nding Registers (SIPNR _H and SIPNR_L) Each bit in the interrupt pending regist er s (SIPNR_H and SIPNR_L), shown in Figur e 4-14 and Figure 4- 15 , corr esponds to an interrupt source.

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Sy ste m Inte rfac e Unit ( SIU) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 4-22 F re escale Sem icondu ctor When a pending inter r upt is handled, the user clears the c orresponding SI PNR bit.

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Sy st em In terf ace Uni t (S IU ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 4-23 Figure 4- 17 shows SIM R_L. Note the following: • SCC/TC/MCC/FC C SI MR bit pos itions are not aff ec ted by t heir relative priority .

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Sy ste m Inte rfac e Unit ( SIU) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 4-24 F re escale Sem icondu ctor 4.3.1.6 SIU Interrupt V ector Regis ter (SIVEC) The SIU int errupt vector register (SIVEC), shown in Figur e 4- 18 , contains an 8-bit code representing the unmasked interrupt s ource of t he highest prio rity level.

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Sy st em In terf ace Uni t (S IU ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 4-25 Figu re 4-1 9. Inter rup t T a ble Hand ling Exa mp le NO T E The PowerQUICC II differs from previous MPC8xx implementations in that when an i nt errupt reques t occurs, S IVEC c an be r ead.

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Sy ste m Inte rfac e Unit ( SIU) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 4-26 F re escale Sem icondu ctor Ta b l e 4 - 8 describes SIEXR fields. 4. 3.2 Sys tem Conf igurat ion a nd Pr ote ction Re gist er s The system configuration and protection r e gisters are descri bed in the following sections.

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Sy st em In terf ace Uni t (S IU ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 4-27 Figure 4- 9 describes BCR fields.

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Sy ste m Inte rfac e Unit ( SIU) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 4-28 F re escale Sem icondu ctor 11 E A V E nable addre ss visib ility . No rm ally , w hen the P ower QUICC II is in single-P ower QUICC II b us mode, the bank selec t si gnals f or SDRAM accesses ar e mu lti ple xed on the 60x bus addr ess lines .

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Sy st em In terf ace Uni t (S IU ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 4-29 4.3.2.2 60x Bus Arbiter Configuration R egister (PPC_A CR) The 60x bus a rbiter configuration register ( PPC_AC R), shown in Figure 4- 22 , defines the arbiter modes and parked mas ter on the 60x bus .

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Sy ste m Inte rfac e Unit ( SIU) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 4-30 F re escale Sem icondu ctor 4.3.2.3 60x Bus Arbitration-Level Registers (PPC_ALRH/PPC_ALRL) The 60x bus arbitration-level registers, s hown in Figure 4- 23 and Figure 4-24 , define arbitr ation priority of PowerQUICC II bus mas ter s.

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Sy st em In terf ace Uni t (S IU ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 4-31 PPC_ALRL, shown in Figur e 4-24 , defines arbitration pr iority of 60x bus masters 8–15. Priority fi e ld 0 is the highest-priority ar bi tration level.

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Sy ste m Inte rfac e Unit ( SIU) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 4-32 F re escale Sem icondu ctor 4.3.2.5 Local Bus Arbitration Level Registers (LCL_ALRH and LCL_ACRL).

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Sy st em In terf ace Uni t (S IU ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 4-33 4.3.2.6 SIU Module Configuration Registe r (SIUMCR) The SIU module c onfiguration register (SIUMCR), s hown in Figure 4-28 , conta i ns bits that configure various features in the SIU module.

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Sy ste m Inte rfac e Unit ( SIU) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 4-34 F re escale Sem icondu ctor 2 PBSE P ar i ty byt e select enable. 0 P arity byte sel ect is di sabl ed. GPL4 outp ut of UPM is av ail able f or memory cont r o l .

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Sy st em In terf ace Uni t (S IU ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 4-35 10–11 APPC Address p ari t y pin s configur ati on. Note t hat du r ing po wer on reset th e MODCK pins are use d f or PLL c onfigur ation.

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Sy ste m Inte rfac e Unit ( SIU) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 4-36 F re escale Sem icondu ctor 4.3.2.7 Internal Memory Map Register (IMMR) The internal memory ma p register (IMMR) , shown in F igure 4-29 , contains identification of a specific device as well as the base address for the internal memory ma p.

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Sy st em In terf ace Uni t (S IU ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 4-37 4.3.2.8 System Protection Control Register (SYPCR) The system pr otection control register , shown in F igure 4-30 , controls the system monitors, software watchdog period, and bus monitor timing.

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Sy ste m Inte rfac e Unit ( SIU) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 4-38 F re escale Sem icondu ctor T able 4-14 des cribes SYPCR fi e lds. 4.3.2.9 Software Service Re gister (SWSR) The software service register (SWSR) is t he loca tion to which the s oftware watchdog timer servicing sequence is wr itten.

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Sy st em In terf ace Uni t (S IU ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 4-39 T able 4-15 describes T E SCR1 fields.

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Sy ste m Inte rfac e Unit ( SIU) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 4-40 F re escale Sem icondu ctor 4.3.2.11 60x Bus T ransfer Error Status and Control Register 2 (TESCR2) The 60x bus transfer error sta t us and contr ol register 2 ( T ESCR2) is shown in Figure 4-32 .

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Sy st em In terf ace Uni t (S IU ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 4-41 The TESCR2 r egis ter is des cri bed in T able 4-16 .

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Sy ste m Inte rfac e Unit ( SIU) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 4-42 F re escale Sem icondu ctor 4.3.2.12 Local Bus T ransfer Error Status and Control Register 1 (L_TESCR1 ) The local bus t rans fer error status and control r egiste r 1 (L_TE SCR1) is shown in Figure 4-33 .

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Sy st em In terf ace Uni t (S IU ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 4-43 4.3.2.13 Local Bus T ransfer Error Status and Control Register 2 (L_TESCR2 ) The local bus t rans fer error status and control r egiste r 2 (L_TE SCR2) is shown in Figure 4-34 .

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Sy ste m Inte rfac e Unit ( SIU) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 4-44 F re escale Sem icondu ctor 4.3.2.14 Time Counter Status and Contr ol Register (TMCNTSC ) The tim.

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Sy st em In terf ace Uni t (S IU ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 4-45 4.3.2.16 Time Counter Alarm Register (TMCNT AL) The time counter alarm r egister (TMCNT AL), shown in Fi gur e 4- 37 , holds a value (ALA RM ).

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Sy ste m Inte rfac e Unit ( SIU) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 4-46 F re escale Sem icondu ctor 4.3. 3 Perio dic I nter rup t Re giste rs The periodic interr upt registers are described in the following sections. 4.3.

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Sy st em In terf ace Uni t (S IU ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 4-47 T able 4-22 des cribes PITC fi e lds.

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Sy ste m Inte rfac e Unit ( SIU) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 4-48 F re escale Sem icondu ctor T able 4-23 des cribes PITR fi e lds. 4.3.4 PCI Co ntr ol R egist ers NO T E This section applies only to the MPC8250, the MPC8265, and the MPC8266.

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Sy st em In terf ace Uni t (S IU ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 4-49 T able 4-24 des cribes PCIBR x fields. 4.3.4.2 PCI Mask Register (PCIMSKx) Figure 4- 42 shows the PCI mas k register .

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Sy ste m Inte rfac e Unit ( SIU) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 4-50 F re escale Sem icondu ctor T abl e 4-26. S I U P ins Multiplexing Contr o l Pin Name Pin Conf ig.

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 5-1 Chapter 5 Reset The PowerQUICC II ha s s ever al inputs to t he reset logic: • Power - on reset (PORE.

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Reset MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 5-2 F re escale Sem icondu ctor 5.1. 1 R eset Act ions The reset block has a reset control logic tha t determines the cause of reset, synchronizes it if nece ssary , and resets the appr opriate l ogic modules.

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Reset MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 5-3 Figure 5- 4 shows the power -on reset flow . Figu re 5-1 . P owe r - on R ese t Flow 5.1.3 HRESET Flow The H R E SET flow may be i nitiated exte rnally by asserting HRESE T or internally when the chip dete cts a reas on to assert HRE SET .

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Reset MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 5-4 F re escale Sem icondu ctor 5.2 Reset Stat us Registe r (RSR) The reset s t atus register (R SR), shown in F igur e 5- 2 , is memory-mapped into the PowerQUICC II’ s SIU register map.

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Reset MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 5-5 NO T E The Reset Status Register accum ul ate s r eset event s.

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Reset MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 5-6 F re escale Sem icondu ctor 5.4 Res et Configu r a tion V arious features may be config ured during hard rese t or power-on reset.

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Reset MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 5-7 The configuration words for all PowerQ UI CC IIs are assumed to reside in an EPROM conne cted to C S0 of the configuration m a ster .

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Reset MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 5-8 F re escale Sem icondu ctor 5. 4.1 Ha rd Rese t Co nfig urat ion W o rd The contents of the har d reset configuration wor d are shown in Figure 5- 4 . Ta b l e 5 - 7 describes har d reset configuration wor d fields.

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Reset MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 5-9 13–15 ISB I n i t ial inte r nal spa ce base select. Defi nes the ini tial v alue of IMMR[0–14 ] and determines the base addres s of the internal memory space.

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Reset MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 5-10 F re escale Sem icondu ctor 5. 4.2 Ha rd Rese t Co nfig urat ion Examp les This section prese nts some examples of hard rese t configurations in di f ferent systems. 5.4.2.1 Single P owerQUICC II with Default Config uration This is the simplest configura tion scenario.

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Reset MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 5-11 Fig ure 5- 6. Configur ing a Sing le Ch ip fr om EPR OM 5.

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Reset MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 5-12 F re escale Sem icondu ctor Fig ure 5-7. Configur ing Multip le Chips In this sys t e m, the configura tion maste r initia lly r e ads its own conf iguration w o rd.

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Reset MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 5-13 shows, this com plex configuration is done without additional glue logic. The configuration master contr o ls the whole pr ocess by ass erting the E PROM control si gnals and the system’ s a ddress signals as needed.

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Reset MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 5-14 F re escale Sem icondu ctor.

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or III- 1 Pa r t I I I The Har dware Interface Intended A udi ence Part III is intended for system designers who ne ed to understand how each PowerQUI CC II s ignal works and how thos e signals interact.

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 III-2 F reescal e Semicondu ctor MPC8 2x x Docu men tatio n Supporting doc umentation for the PowerQUICC II can be accessed t hrough the world-wide web at www .

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or III- 3 CPM Communicat ions process or module CRC Cyclic r edundanc y chec k DM A Dir ec t me mo r y ac ce s.

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 III-4 F reescal e Semicondu ctor PRI Primary r ate in te rf ace Rx Receiv e SCC Ser i al commu nicat i on s cont roll er SC P Se ria l .

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 6-1 Chapter 6 External Signal s This chapter describes the e xt ernal signals. A more detailed desc r iption of 60x bus signals is provided in Chapter 8, “ The 60x B us.

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Externa l Sign als MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 6-2 F re escale Sem icondu ctor F igu re 6 -1 . Pow erQ UI CC II Ex te rn al Si gna ls 6.2 Signal Descri ptions The PowerQUICC II s ystem bus, shown in Ta b l e 6 - 1 , consis t s of all the signals that inte rface wit h the external bus.

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Externa l Sign als MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 6-3 T a ble 6-1 . Externa l Sign als Signal De script ion BR 60x b us reque st —Thi s is an output when an e xter na l arb i t er i s us ed and an input when an internal arbit er i s u sed.

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Externa l Sign als MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 6-4 F re escale Sem icondu ctor DBB IRQ 3 60x data bu s busy—(I nput/ out p ut ) As an output th e P o werQUI CC II asser t s this pin f or the durat i on of the da t a b us t e nure.

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Externa l Sign als MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 6-5 IRQ 3 DP[3] CKSTP_OUT EXT_BR3 Inter rupt reque st 3—Thi s input is on e of the ei ght e xter na l l ines tha t can reque st (by means of the internal int errupt contr olle r ) a ser vi ce routi ne from the core .

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Externa l Sign als MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 6-6 F re escale Sem icondu ctor IRQ 7 DP[7] CSE[1] Inter rupt reque st 7—Thi s input is on e of the ei ght e xter na l l ines tha t can reque st (by means of the internal int errupt contr olle r ) a ser vi ce routi ne from the core .

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Externa l Sign als MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 6-7 WT BADDR30 IRQ 3 Write through— Outp ut used f o r L2 cache con t r ol.

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Externa l Sign als MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 6-8 F re escale Sem icondu ctor CS[11] AP[0] Chip se lect—Out put t hat enab le sp ecifi c m emory de vices or periph erals connec ted t o Power QU IC C II buse s.

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Externa l Sign als MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 6-9 PSDCAS PGPL3 60x bus SDRAM CAS—Output from the 60x bus SDRAM contro ller . Shoul d be conne cted to SDRAMs’ CAS in p u t. 60x b us UPM ge neral pu r pose l ine 3—One of si x general pur po se output lines f r om UPM.

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Externa l Sign als MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 6-10 F re escale Sem icondu ctor LSD WE LGPL1 PCI_MODCK_H1 1 Local b us SDRAM write ena ble— Output f rom the loca l bus SDRAM contr oller . Should be connecte d to th e WE inp uts of the SDRAMs .

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Externa l Sign als MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 6-11 L_A15 SMI PCI_FRAME 1 Local b us addr ess 15—L ocal bus a ddress b it 15 o ut pu t pin. I n the l ocal addres s bus b it 14 i s mos t signi fican t and bit 31 is least signi ficant.

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Externa l Sign als MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 6-12 F re escale Sem icondu ctor L_A22 PCI_SERR 1 Local b us addr ess 22—L ocal bus a ddress b it 22 o ut pu t pin. I n the l ocal addres s bus b it 14 i s mos t signi fican t and bit 31 is least signi ficant.

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Externa l Sign als MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 6-13 L_A27 PCI_GNT2 1 CPCI_HS_ENUM 1 Local b us addr ess 27—L ocal bus a ddress b it 27 o ut pu t pin. I n the l ocal addres s bus b it 14 i s mos t signi fican t and bit 31 is least signi ficant.

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Externa l Sign als MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 6-14 F re escale Sem icondu ctor LCL_DP[0– 3] PCI_C / BE [3-0] 1 Local b us data parity—Loca l b us data parity input / o ut p ut pi ns. I n loca l b us wr i te operat ions t he P ow erQUICC I I driv es t hese pins .

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Externa l Sign als MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 6-15 RSTCONF RSTCONF —Input used d uring r ese t conf igurat ion s equence of t h e chip . Find detaile d expl anation of its func tion in Sec tion 5.

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Externa l Sign als MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 6-16 F re escale Sem icondu ctor P A[0–31] Gener al-purpose I/ O por t A bits 0–31—CPM port mul tiple xing is described i n Chapter 40 , “P ar allel I/O P or ts.

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 7-1 Chapter 7 60x Si gnals This chapter describe s the PowerQUI CC II pr ocessor ’ s exter nal signals.

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60x S ign als MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 7-2 F re escale Sem icondu ctor 7.1 Signal Configura tion Figure s hows the grouping of the PowerQUICC I I’ s 60x bus signal configuration. NO T E The PowerQUICC II har dware specifi cations pr ovides a pinout showing pin numbers.

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60 x S ign als MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 7-3 7.2. 1 A ddre ss B us Ar bitr ation Sig na ls The address a rbitration signals are a col.

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60x S ign als MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 7-4 F re escale Sem icondu ctor a snoop copyback; may also be negated if t he externa l m aster cance ls a bus request internally before receiving a qualifi ed BG . High Impedance—O ccurs during a har d reset or c heckstop condition.

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60 x S ign als MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 7-5 7.2.1.3 Address Bus Busy ( ABB ) The address bus busy ( ABB ) s ignal is both an input and an output signal. 7. 2.1.3. 1 Addres s Bus Busy (ABB )—Outpu t Following a re the state me aning and timing comments for the ABB output signal.

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60x S ign als MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 7-6 F re escale Sem icondu ctor bus request if the tr ansfer attributes TT[0–4] indicate that a data tenure i s required f or t he tra ns act io n. Negated—Has no special meani ng during a nor mal transaction.

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60 x S ign als MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 7-7 S t at e Meaning Asserted—Indicates t hat another de vice has be gun a bus trans action and that the address bus and transfer attribute s i gna ls are valid for snooping and in slave mode.

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60x S ign als MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 7-8 F re escale Sem icondu ctor High Impedance—Same as A[0–31]. 7.2.4.3 T ransfe r Bu r st (TBST ) The transfer burst (TBS T ) signal is an input/output signal on the PowerQUI CC II.

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60 x S ign als MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 7-9 S t at e Meaning Asserted—Indicates that the t ransaction in progress should not be ca ched. CI reflects the I bit (WIM bits) from the MMU except during certain transactions.

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60x S ign als MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 7-10 F re escale Sem icondu ctor S t at e Meaning Asserted—Indicates that a 60x bus slave is terminating the address tenure.

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60 x S ign als MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 7-11 T iming C ommen ts Assertion—May occur as early as the second cycle following the assertion of TS and must occur by the bus clock cycle immediately following the assertion of AACK if an address retr y is required.

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60x S ign als MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 7-12 F re escale Sem icondu ctor Negated—Indicates that an ext e rnal device i s not granted mastership of the data bus.

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60 x S ign als MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 7-13 S t at e Meaning The data bus hold s 8 byte lanes assigned as shown in Ta b l e 7 - 2 .

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60x S ign als MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 7-14 F re escale Sem icondu ctor S t at e Meaning Asserted/Negated—Re pr esents odd parity fo r each of 8 bytes of data write transactions. Odd parity means that an odd number of bits , including the parity bit, are driven high.

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60 x S ign als MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 7-15 asser ted for eac h data beat in a burst tr ansaction. F or more i nformation, s ee Sectio n 8 .5.3, “ Da t a Bus T r ansfers and Normal T er mination.

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60x S ign als MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 7-16 F re escale Sem icondu ctor Negation—Occurs after the clock cycle of the final (or only) data beat of the transf er . For a burst transfe r , T A may be negated between beats to insert one or more wait states before the completion of the next beat.

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60 x S ign als MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 7-17 tran saction,. F or more inf ormation, se e Section 8.

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60x S ign als MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 7-18 F re escale Sem icondu ctor.

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 8-1 Chapter 8 Th e 60x B us The 60x bus , which is used by proc essors that imp lement the PowerPC architecture, pr ovides flexible support for t he on-chip MPC603 proces sor as well as other internal and external bus devices.

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Th e 60x Bu s MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 8-2 F re escale Sem icondu ctor 8.2 Bus Co nfiguration The 60x bus supports separate bus conf igurations fo r internal mas ters and exte rnal bus masters. • Single-PowerQUICC II bus mode c onnects external devices by using only the memory controller .

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Th e 60x Bu s MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 8-3 Figur e 8-1. Single-Po werQUI CC II Bu s Mode NO T E In single-Power QUI CC II bus mode, the PowerQUICC II us es the a ddr ess bus as a memory address bus.

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Th e 60x Bu s MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 8-4 F re escale Sem icondu ctor operations and maintains coherency bet ween the primary cache s and mai n m emo r y . Figur e 8-2 shows how an external process o r is attached to the PowerQU ICC II.

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Th e 60x Bu s MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 8-5 require data transfer termination signals for each beat of data.

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Th e 60x Bu s MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 8-6 F re escale Sem icondu ctor system reset by sampling configuration pins. S ee Section 4. 3.2.2, “60x Bus Arbiter Configuration Register (PPC _AC R), ” f or mo re info rmation.

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Th e 60x Bu s MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 8-7 Externa l arbitration (as provided by the PowerQUICC II) is required in systems in which multiple devices share the system bus. The Power QUI CC II uses the address acknowledge (AACK ) signal to control pipelining.

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Th e 60x Bu s MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 8-8 F re escale Sem icondu ctor with BG INT - asserte d (note tha t BG INT is an internal signal not seen by the user at the pins), which lets it s t a rt an address bus t e nure by a sserting TS .

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Th e 60x Bu s MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 8-9 Figure 8-5. Addres s Pipelining 8. 4.3 Ad dres s T r ansf er At trib ut e Si gnals During the addr ess transfer , the a ddress is placed on the address signals, A[ 0–31].

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Th e 60x Bu s MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 8-10 F re escale Sem icondu ctor Ta b l e 8 - 2 . Tr a n s f e r Ty p e E n c o d i n g TT[0–4 ] 1 60x Bus Specificati on 2 P owerQUI CC II as Bus Master PowerQ UI CC I I as Snooper P owerQUICC II as Sl ave Command T ransact ion Bus T rans.

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Th e 60x Bu s MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 8-11 NO T E Regarding Ta b l e 8 - 2 : 1XX01 Re ser v ed fo r cust omer — Not appli c ab le.

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Th e 60x Bu s MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 8-12 F re escale Sem icondu ctor • For reads, the processor cleans or fl ushes during a snoop based on the TB ST input. The proc essor cleans for single-beat reads (TBST negated) to emulate read-with-no- intent-to- cache oper ati ons.

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Th e 60x Bu s MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 8-13 The PowerQUICC II supports cr itical-word-first burst trans actions (double-word-aligned) f rom the processor .

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Th e 60x Bu s MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 8-14 F re escale Sem icondu ctor Each data bea t is te rminated with an assertion of T A . 8.4.3.5 Effect of Alignment on Data T ransfers Ta b l e 8 - 6 l ists th e ali gned transfer s tha t can occur to and from the Powe rQUICC II.

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Th e 60x Bu s MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 8-15 The PowerQUICC II supports misa li gned memory operations, a lthough they may degrade performance substanti ally .

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Th e 60x Bu s MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 8-16 F re escale Sem icondu ctor 8.4.3.6 Effect of P or t Size on Data T ransfers The PowerQUICC II can transfer operands through its 64-bit dat a port.

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Th e 60x Bu s MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 8-17 Figur e 8-6. Interface to Different P o rt Size Devices 0 31 63 OP0 OP1 OP2 OP3 OP4 OP5 .

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Th e 60x Bu s MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 8-18 F re escale Sem icondu ctor 8.4.3.7 60x-Compatible Bus Mode—Siz e Calculation T o comply wit h the requirements li.

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Th e 60x Bu s MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 8-19 calculation st ate machine. Note that the addres s and size state s are for internal use and are not transfe rred on the addr ess or TSIZ pins .

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Th e 60x Bu s MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 8-20 F re escale Sem icondu ctor 16-, or 24-byte extended transfers. These transactions are compatible with the 60x bus, but s ome slaves or masters do not support thes e features.

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Th e 60x Bu s MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 8-21 T able 8-12. Address and S ize State for Extended T r ansfers Size State [0–3] Ad dres.

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Th e 60x Bu s MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 8-22 F re escale Sem icondu ctor Extended transfer mode is enabled by setting the B CR [ETM].

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Th e 60x Bu s MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 8-23 Figure 8-7. Retry Cycle As a bus master , the PowerQUI CC II r ecognizes either an early or qualified AR TR Y and prevents the data tenure associate d with the r etr ied address tenur e.

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Th e 60x Bu s MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 8-24 F re escale Sem icondu ctor TA / A RT RY relationship is not met, the master ma y enter an undefined state. Users may use PPC_ACR[ DBGD] to ensure correct oper ation of the s ystem.

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Th e 60x Bu s MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 8-25 one-level pipelining). When the inter nal arbiter c ounts a pipeline depth of two (two a ss ertions of AACK befor e the a ssertio n of the c urrent da ta tenure) it ne gates all address bus grant (BG ) signals .

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Th e 60x Bu s MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 8-26 F re escale Sem icondu ctor • External masters connec ted to the 60x bus must as sert DBB only for the dur ati on of its data tenur e. External masters should no t use DBB to prevent other mas ters from using the data bus after their data tenure has ended.

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Th e 60x Bu s MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 8-27 Figure 8- 8 shows both a s ingle-beat and burst data transfer . The PowerQUICC II a sserts T A to mar k the cycle i n which da ta is acce pted.

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Th e 60x Bu s MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 8-28 F re escale Sem icondu ctor Figure 8-9. 28-Bit Extended T ransfer to 32-Bi t P ort Si ze Figure 8- 10 shows a burst trans fer to a 32-bit por t.

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Th e 60x Bu s MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 8-29 Figure 8-10. Bu rst T ra nsfer t o 32-Bit P ort S i ze 8.

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Th e 60x Bu s MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 8-30 F re escale Sem icondu ctor Figu re 8-1 1. Data T e nure T er min ated by Ass er tion of TE A The PowerQUICC II interprets the following bus transactions as bus errors: • Direct-store tr ansactions, as indicated by the as s ertion of XA TS .

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Th e 60x Bu s MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 8-31 snooping condition) . No snoop updat e to the PowerQUICC II processor cache occurs if the transaction is not marked globa l . This includes invalidation cycles.

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Th e 60x Bu s MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 8-32 F re escale Sem icondu ctor 8.7. 1 S upp or t for the l war x/stw cx. Inst ruct ion Pair The load word and res erve indexed ( lwar x ) and the s tore word conditional indexed ( st wcx.

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 9-1 Chapter 9 PCI Bridge NO T E The functionalit y described in this chapter is a vailable only on the MPC8250, the M P C8265, and the MPC8266.

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PCI Bridg e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 9-2 F re escale Sem icondu ctor Fi gure 9-1 . P CI Br idge in the P o wer QUI CC II Figu re 9-2.

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PCI Brid ge MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 9-3 9.1 Signals T o avoid the need for additional pins, the PCI br idge is designed to make use of the local bus si gnals. Therefore, many of thes e pins pe rform dif ferent functions, depending on how the user configures them.

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PCI Bridg e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 9-4 F re escale Sem icondu ctor NO T E Although the user can direct the SDMA to the 60x bus, tr ansactions can be redirected to t he PCI bridge if they f all in one of the PC I windows of the 60x bus memory map (PCIBR0 or PCIBR1; refer to S ec tion 4 .

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PCI Brid ge MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 9-5 9.8 Compa c tPCI Hot Swap Specification Suppo rt CompactPCI is an open specification s upported by the PCI I ndustrial Computer Manufacturers Group (PICMG) and is i ntended for embedded applications us ing PCI.

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PCI Bridg e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 9-6 F re escale Sem icondu ctor • Address translation u nits for address mapping between hos t and agent. Ef forts were made t o keep the t erminology in this ch apter consistent with the PCI Specif ication, revision 2.

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PCI Brid ge MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 9-7 9.9.1.2 PCI Protocol Fundamentals The bus transfer mechanism on the PCI bus is called a burst. A burst is comprised of an address pha se and one or m or e data phases.

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PCI Bridg e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 9-8 F re escale Sem icondu ctor 9. 9.1.2. 1 Bas ic T ran sfer Contro l PCI data tr ans f ers are controlled with thr ee funda mental signals: •F R A M E is driven by an initiator to indicate the beginning and end of a transaction.

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PCI Brid ge MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 9-9 line, and dis connects after r eading one cac he line. If AD[ 1-0] is 0bx1 (a reserved encoding) and the PCI _C/BE [3- 0] s ignals indicate a memory transaction, it e xecu tes a t arget dis connect after the first data phase is completed.

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PCI Bridg e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 9-10 F re escale Sem icondu ctor A read transaction st ar ts when FRA ME is asserted for the f irst time and the PC I_C/B E [3-0 ] sig na ls indicate a read command. Figure 9-3 shows an example of a single beat read transaction.

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PCI Brid ge MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 9-11 Figure 9-5. Single Beat Wri te E xample Figure 9- 6 shows an example of a burst write transa ction.

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PCI Bridg e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 9-12 F re escale Sem icondu ctor When the PCI bridge as a target needs to suspend a transaction, it asser ts S TOP . Once asserte d, STOP remains asserte d until FRAME is negated.

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PCI Brid ge MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 9-13 • AD[1-0] is 0bx 1 ( a reserved burst ordering encoding) during the address phase and one data phase has co mpleted.

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PCI Bridg e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 9-14 F re escale Sem icondu ctor target qualif ies the address/data lines with FRAME before asserting DEVSEL . DEVSE L i s asse rt e d at or before the c lock edge at which the PCI bridge enables i ts TRDY , ST OP , or data (fo r a re a d ).

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PCI Brid ge MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 9-15 For core- or DMA-initiated transfers, the PCI bridge streams over cache line boundaries if.

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PCI Bridg e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 9-16 F re escale Sem icondu ctor the AD l ines, reaches a s table value . This me ans that a valid addres s and command a re driven on the AD and PCI_C/B E lines one cycl e before the assertion of FRAME .

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PCI Brid ge MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 9-17 When the CONFIG_ADDRESS regis ter gets written with a value such that the bus number match.

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PCI Bridg e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 9-18 F re escale Sem icondu ctor 9. 9.1.5. 2 Error Reporting Except for setting t he detected-parity-error bit, all parity error repor ting and response i s controlled by the parity-error -r esponse bit (see Section 9.

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PCI Brid ge MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 9-19 As a t arget t hat as serts SERR o n an address parity , the PCI bridge comple tes the transa ction on the PCI bus, aborting interna lly if the transac tion is a write to s yst em memory .

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PCI Bridg e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 9-20 F re escale Sem icondu ctor is the master that is currently using the bus, and the highest priority devic e is the next one to follow the current master .

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PCI Brid ge MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 9-21 completes one m ore data phase a nd relinquishes the bus. Th e master late ncy timer can be disabled if needed (see Section 9.1 1. 2.22, “PCI Bus Function Regis ter” ).

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PCI Bridg e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 9-22 F re escale Sem icondu ctor • If the transaction a ddr ess is within one of the two inbound PCI translation windows, the transa ctio n is se nt to the cor e s ide of the PCI bridge with a ddress translation.

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PCI Brid ge MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 9-23 NO T E When a transacti on is performed by a P C I maste r , the bridge checks the address aga i nst inbound A TUs and if it does not hit, it then checks against PIMMR; if it is a hit, the bridge translates it to a 60x cycle.

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PCI Bridg e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 9-24 F re escale Sem icondu ctor Figure 9-14. A ddress M ap Exam ple 9.10.1 Addre ss Map Progr amm ing The address map has a number of programmable ranges to determine t he PCI bridge’ s response to all transactions.

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PCI Brid ge MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 9-25 are routed to the PCI bus wit h address transl ation disabled. T he reset configuration for inbound transactions are that all inbound requests from the PCI bus are disa bled.

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PCI Bridg e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 9-26 F re escale Sem icondu ctor 9.10.2.2 PCI Outbound T ranslation Outbound address tr anslation is provided to allow th e outbound tr ansactions to acc ess any address over the PCI memory or I/O space.

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PCI Brid ge MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 9-27 9.11 Config uration Registers There are two types of configura t ion registers i n th e PCI br idge: P CI-specified and memory-mapped.

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PCI Bridg e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 9-28 F re escale Sem icondu ctor 0x10458 Outbound me ssage regist er 0 (OMR0) R/W undef i n ed 9.12. 1. 2 / 9- 66 0x1045C Outbou nd m essage regi ster 1 (OMR1) R/W undef i n ed 9.

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PCI Brid ge MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 9-29 0x10608 DMA 2 current desc r iptor addres s regist er (DMA CDAR2) R/W 0x0000_000 0 9.13. 1. 6 . 3/ 9-91 0x10610 DMA 2 source address regi ster (DMASAR2) R/W 0x0000_000 0 9.

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PCI Bridg e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 9-30 F re escale Sem icondu ctor 9.11.1.1 Message Uni t (I 2 O) Registers Message unit regis t ers are described in Section 9.12, “Message Unit (I2O),” on page 9- 65 . 9.

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PCI Brid ge MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 9-31 9.11.1.4 PCI Outbound Base Ad dress Registers (POB AR x ) The PCI outbound base address re.

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PCI Bridg e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 9-32 F re escale Sem icondu ctor Figure 9-19. P CI O utb oun d Compari son Mask Registers (P OCM R x ) T able 9-6.

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PCI Brid ge MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 9-33 Figure 9-20. Discard Timer Control register (PTCR) T able 9-7.

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PCI Bridg e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 9-34 F re escale Sem icondu ctor Fi gure 9 -21 . Gene ra l Pu rpo se C on tr ol R egi st er ( GP CR) T able 9-8.

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PCI Brid ge MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 9-35 9.11.1.8 PCI General Contr ol Register (PCI_GCR) The PCI general contr ol register (PCI_GCR), shown in Figure 9-22 , contains a bit f or controlling the PCI reset signal when in host mode .

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PCI Bridg e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 9-36 F re escale Sem icondu ctor Figure 9-23. Error Status Register (ESR) T able 9-10.

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PCI Brid ge MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 9-37 9.11.1.10 Error Mask Register (EMR) Th e er ro r m ask reg i s t e r (E MR) re g i ste r ,.

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PCI Bridg e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 9-38 F re escale Sem icondu ctor 9.11.1.11 Error Contr ol Reg ister (ECR) The error control r egis t er (ECR) register , shown in Figur e 9-25 , deter mine s whether the IOU asser ts an interrupt or a m achine check f or the error condi tions listed in T able 9-10 .

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PCI Brid ge MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 9-39 9.11.1.12 PCI Error Address Capture Register (PCI_EACR) The PCI error addre ss capture register (PCI_EACR), shown in Figure 9-26 , stor es t he ad dr e ss as so ciat ed with the firs t PCI err or captur e d.

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PCI Bridg e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 9-40 F re escale Sem icondu ctor 9.11.1.13 PCI Error Data Capture Register (PCI_EDCR) The PCI e rror data capture r egister ( PCI_EDCR), shown in F i gure 9-27 , stores t he data asso ciated wi th the firs t PCI e r ror ca ptured.

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PCI Brid ge MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 9-41 Figure 9-28. P CI Err or Co ntr o l Capture Register (PCI _ECCR) T able 9-15 des cribes PCI_ECCR fi e lds.

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PCI Bridg e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 9-42 F re escale Sem icondu ctor 9.11.1.15 PCI Inbound T ranslation Address Registers (PIT AR x ) The P CI inbound tr ans l.

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PCI Brid ge MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 9-43 in a PI BAR x register causes a change in t he GPLABAR x in the base addres s bits that are non-masked by PICM R x , and vice versa.

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PCI Bridg e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 9-44 F re escale Sem icondu ctor Figu re 9-3 1. PCI Inbo und C omp arison Mask Regis ters (PIC MR x) T able 9-18.

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PCI Brid ge MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 9-45 9.11.2 PCI Bri dge Conf i g uratio n Regi ster s The PCI Loc al Bus Specific ation defines t he configuration registe r s fr om 0x00 through 0x3F .

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PCI Bridg e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 9-46 F re escale Sem icondu ctor Fi gure 9-3 2 . P C I Bri dge P CI C onf ig urat ion Regi ster s The PCI configur atio n registers are accessible f rom the cor e through an indirect method discussed in “Section 9.

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PCI Brid ge MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 9-47 Figu re 9-33 . V end or ID Reg iste r 9.11.2.2 Device ID Register Figure 9- 34 and T able 9-21 describes the device ID register . Figure 9 - 34.

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PCI Bridg e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 9-48 F re escale Sem icondu ctor 9.11.2.4 PCI Bus Statu s Register The PCI bus status register , shown in Figur e 9-36 , is use d to rec ord status infor mation for PC I bus -relate d events.

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PCI Brid ge MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 9-49 Figure 9-36. P CI Bus S tatus Reg i ster T able 9-23. describes the PCI bus status r egister fields. 9.11.2.5 Revision ID Register Figure 9- 37 and T able 9-24 describe the revision ID register .

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PCI Bridg e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 9-50 F re escale Sem icondu ctor Figure 9-37. Revision ID Register 9.11.2.6 PCI Bus Programming Interface Register Figure 9- 38 and T able 9-25 descr ibe the PCI bus pr ogr amming i nt erface register .

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PCI Brid ge MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 9-51 Figure 9-39. Subclass Code Register 9.11.2.8 PCI Bus Base Class Code Register Figure 9- 40 and T able 9-27 describe the PCI bus clas s code re gister .

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PCI Bridg e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 9-52 F re escale Sem icondu ctor Figure 9-41. P CI Bus C ache Line Size Register 9.11.2.10 PCI Bus Latency Timer Register Figure 9- 42 and T able 9-29 describe the PCI bus latency timer registe r .

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PCI Brid ge MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 9-53 Figure 9-43. Heade r T ype Register 9.11.2.12 BIST Control Register Figure 9- 44 and T able 9-31 describe the BIST contr ol register . Figure 9-44.

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PCI Bridg e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 9-54 F re escale Sem icondu ctor Figur e 9-45 . P CI Bu s Internal Memor y-Mapped Registers Base Address Register (PIMMRBAR) T able 9-32 des cribes PIMMRBAR fi e lds. 9.11.2.

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PCI Brid ge MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 9-55 Figure 9-46. General Purpose L ocal Access Bas e Address Reg isters (GPLABAR x ) T able 9-33 des cribes GPLABAR x f ields. 9.11.2.15 Subsystem V endor ID Re gister Figure 9- 47 and T able 9-34 describe the subsystem vendor ID register .

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PCI Bridg e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 9-56 F re escale Sem icondu ctor 9.11.2.16 Subsystem Device ID Register Figure 9- 48 and T able 9-35 describe the subsystem I D register . Figure 9-48. Subsystem Device ID Register 9.

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PCI Brid ge MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 9-57 Figure 9-50. PCI Bus Interru pt Line Register 9.11.2.19 PCI Bus Interrupt Pin Register Figure 9- 51 and T able 9-38 describe the PCI bus interrupt pin register .

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PCI Bridg e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 9-58 F re escale Sem icondu ctor 9.11.2.21 PCI Bus MAX LA T Figure 9- 53 and T able 9-40 describe the PCI bus MAX L A T r egis ter .

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PCI Brid ge MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 9-59 9.11.2.23 PCI Bus Arbiter Configuration Re gister The PCI bus arbiter configuration register , shown in F igure 9-55 , is used to dete rmine the configuration of the PC I bus arbiter .

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PCI Bridg e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 9-60 F re escale Sem icondu ctor T able 9-42. describes the PCI bus arbiter configuration r egister fields. 9.11.2.24 PCI Hot Swap Register Block The PCI Hot Swap register block, shown i n Figure 9-56 , is a set of registers in a capability structur e .

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PCI Brid ge MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 9-61 9.11.2.25 PCI Hot Swap Control Status Register Figure 9- 57 and T able 9-44 describe the Hot Swap contr ol status register . Figure 9-57 . Hot Swap Control St atus Register T able 9-43.

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PCI Bridg e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 9-62 F re escale Sem icondu ctor 9.11.2.26 PCI Configuration Register Acce ss from the Core The 60x bus master cannot directly access the P CI conf iguration registers because they ar e not i n the internal m emory-mapped configuration r egister ’ s s pace.

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PCI Brid ge MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 9-63 9. 11.2.27.1 Add itional Inf ormat ion on E n dia ness The endianess of both the MPC826x&a.

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PCI Bridg e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 9-64 F re escale Sem icondu ctor Therefore, to set CTM in PCI DMA0 mode register , 0x00000004 is written to 0x04710504.

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PCI Brid ge MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 9-65 • Accesses to PCI configuration r egisters ar e indirect ( through PCI CFG_ADD R and P CI CFG_DA T A).

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PCI Bridg e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 9-66 F re escale Sem icondu ctor turn c auses an inte rrupt to the local pr oce ssor t ha t imple ments the PowerPC a rchi tecture bec ause th e register indirectly dr ives an interrupt line to the loc al processor .

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PCI Brid ge MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 9-67 Figure 9-61. Outbo und Message Registers (OMR x ) 9.12.2 Door Bell Re gisters The PCI bridge c ontains an inbound a nd an outbound door bell register .

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PCI Bridg e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 9-68 F re escale Sem icondu ctor Fig ure 9-62 . Ou t bou nd Doorb ell Regi ster (ODR) 9.12.2.2 Inbound Doorb ell Register (IDR) IDR, described in Figure 9-63 and T able 9-49 , is acc essible from the P CI bus and the 60x bus in both host and agent modes .

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PCI Brid ge MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 9-69 9.12.3 I 2 O U nit The Int elligent Input Output s pecif ication (I 2 O) was established in the indus try to allow architecture-independent I/ O subsystems to communicat e w ith an O S through an a bstraction laye r .

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PCI Bridg e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 9-70 F re escale Sem icondu ctor Figur e 9-6 4. I 2 O Messag e Q ueue I 2 O defines extensions f or the PCI bus hardware thro u gh which message queues are ma naged in hardware.

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PCI Brid ge MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 9-71 The following registers s hould be accessed only from the 60x bus and only in agent mode. Accesses wh i l e in host mode or from the PC I bus have undefined res ults.

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PCI Bridg e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 9-72 F re escale Sem icondu ctor Figu re 9-66 . Inboun d Fre e_FIFO T a il P oin ter Re gister (IFTP R) 9.

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PCI Brid ge MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 9-73 Figure 9-67. Inb ound P ost_FIF O H ead P oi nter Regi ster (IPHPR) MF As posted by PCI hosts are picked up by the local processor via the inbound post_FIFO tail pointer register , described in Figur e 9-68 and T able 9 - 53 .

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PCI Bridg e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 9-74 F re escale Sem icondu ctor 9.12.3.3 Outbound FIFO s The outbound queues ar e used to send message s from the local processor to a remote host processor . I 2 O defines two outbound FI FOs—an outbound post FIFO and an outbound free FI FO.

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PCI Brid ge MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 9-75 Free MF As are picked up by the local processor point ed to by the outbound free_FIFO tail pointer re gister , described in Figure 9-70 and T able 9-55 .

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PCI Bridg e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 9-76 F re escale Sem icondu ctor An ex ternal PCI mast er reads the outbound queue port register . T his caus es the PCI bridge’ s I 2 O unit to read the MF A from l ocal memory pointed to by t he OP TPR+QBAR.

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PCI Brid ge MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 9-77 Figur e 9-72. Outbou nd P o st_FIFO T ail Pointer Register (OPTPR ) 9.12.3.4 I 2 O Registers 9. 12.3.4. 1 Inboun d FIFO Queue P ort Regist er ( IFQPR) IFQPR is us ed by PCI masters to access inbound m essages in local memory .

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PCI Bridg e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 9-78 F re escale Sem icondu ctor 9.1 2. 3. 4.2 Out bo und F IFO Qu eu e P or t Re gi ste r ( OFQPR ) OFQPR is used by P CI masters to access outb ound mess ages in l ocal memory .

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PCI Brid ge MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 9-79 Figure 9-75. O utbound Messag e Interrupt Status Register (OMIS R) T able 9-60 des cribes OMISR fields.

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PCI Bridg e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 9-80 F re escale Sem icondu ctor Figure 9-76. Outb ound Messag e I nterrup t Mask Reg ister (OMIMR ) T able 9-61 describes OM IMR fields.

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PCI Brid ge MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 9-81 Figure 9-77. Inbound Messag e Interrup t Status Reg ister (IMIS R) T able 9-62 des c rib e s IM ISR field s . 31 16 Field — Reset 000 0_0000_0000_ 0000 R/ W R efer t o Ta b l e 9 - 6 2 .

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PCI Bridg e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 9-82 F re escale Sem icondu ctor 9. 12.3.4. 6 Inboun d Messa ge Interr upt Mask R egister ( IMIMR) This regis ter contains t he interrupt mask of the I 2 O, door bell, and message register events generated by the PCI master .

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PCI Brid ge MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 9-83 9.12.3.4 .7 Messa ging U n it Contro l Register ( M UCR) This register a ll ows software to e nable and setup the size of the inbound and outbound FIFOs.

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PCI Bridg e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 9-84 F re escale Sem icondu ctor 9. 12.3.4. 8 Queue Base Ad dress Reg ister (QB AR) This register specifies the beginning of the circular queue structure in local memory . T he following QBAR should be ac cessed only f r om the 60x bu s and only in agent mode.

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PCI Brid ge MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 9-85 9.13 DMA C ont r oller The PCI bridge’ s DMA contr oller transfers blocks of da ta independent of the local core or PC I hosts. Data movement occurs on the PCI and/or 60x bus.

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PCI Bridg e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 9-86 F re escale Sem icondu ctor address . The DMA contro lle r assu mes that the source and destination addres ses are valid PCI or 60x memory addres ses.

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PCI Brid ge MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 9-87 • First clear then set the CS (channe l start) bit in the mode regi ster to start the DMA transf er .

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PCI Bridg e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 9-88 F re escale Sem icondu ctor 60x bus, or when no data is left to trans fer .

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PCI Brid ge MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 9-89 Ta b l e 9 - 6 6 . D M A M R x Field Descrip t i ons Bit s Name Des cription 31–24 — Reserv ed, shoul d be c leared . 23–21 BWC Bandwi dth contr ol.

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PCI Bridg e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 9-90 F re escale Sem icondu ctor 9. 13.1.6 .2 DMA St atus Regi ster [0 –3] (DMA SR x ) The status register reports various DMA conditi ons during and after the DMA tr ans fer .

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PCI Brid ge MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 9-91 9. 13.1.6. 3 DMA Curr ent D es cripto r Add r es s Registe r [ 0–3] (DMA CD AR x ) The current descriptor address register contains th e addr ess of the current segment des criptor being tra nsferre d.

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PCI Bridg e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 9-92 F re escale Sem icondu ctor 9. 13.1.6 .4 DMA So urce A dd ress Regi ster [0–3] (DMASA R x ) The source address register , shown in Figure 9-85 , i ndicates the addres s where the DM A controller will be reading data from.

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PCI Brid ge MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 9-93 The choice between PCI or 60x is done according to t he following rule: If the address hits one of the PC I outbound windows, then the destination data is wr it ten to the PCI memory .

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PCI Bridg e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 9-94 F re escale Sem icondu ctor 9. 13.1.6. 7 DMA Ne xt D esc ripto r Add r es s Register [0–3] (DMAND AR x ) The next descriptor address r egister (NDAR ) contains the address for the next s egment desc riptor in t he chain.

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PCI Brid ge MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 9-95 9. 13.2 DMA Se gm ent D e s c r iptor s DMA segment descriptors contain the source and destination addresses of the data s egment, the segment byte count, a nd a link to the next descriptor .

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PCI Bridg e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 9-96 F re escale Sem icondu ctor Figure 9-89. DMA Chain of Segmen t Descrip tors 9.13.2.1 Descriptor in Big Endian Mode In big endian mode, the descriptor in 60x memory should be progra mm ed such that data appear s in ascending significant-byte order .

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PCI Brid ge MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 9-97 Byte Co un t = 0x 67 45 230 1 <M SB .. LS B> 9.13.2.2 Descriptor in Little Endian Mode In litt le endian mode, the de scriptor in PCI memory should be pr ogrammed such that data appears in descending significant byt e order .

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PCI Bridg e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 9-98 F re escale Sem icondu ctor 9. 14.1.1. 1 System Erro r (SERR ) The S ERR signal is used to r eport PCI addr ess parity errors. It is dr iven for a single P C I clock cycle by the agent that is r eport ing the error .

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PCI Brid ge MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 9-99 9. 14.1.3. 1 Addres s Par ity Erro r If t he PCI bridge is acting as a PCI mast er and the.

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PCI Bridg e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 9-100 F re escale Sem icondu ctor 9. 14.1.3 .4 T arget -Abort Err or If a PCI tra nsaction initiated by the PCI br idge is .

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 10-1 Chapter 1 0 Cloc ks and P ow e r Con trol The PowerQUICC II’ s clocking a rchitecture includes two PLLs—the main PLL and the core P LL.

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Clocks and Power Control MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 10-2 F re escale Sem icondu ctor 10 .4 Main PL L The ma in PLL pe rforms fr equency multiplic ation a nd skew e limination.

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Cl ocks and Po w er C ontrol MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 10-3 output frequency is twice the C PM frequency . This double frequency is r equir ed to genera t e the CPM_CLK and C PM_CLK_90 clocks.

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Clocks and Power Control MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 10-4 F re escale Sem icondu ctor Figur e 10 -2. P CI Bridge as an Agent, Operating from the PCI System Cloc k 10.

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Cl ocks and Po w er C ontrol MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 10-5 NO T E If a clock buff er is us ed in the f ee dback path fr om DLLOUT to.

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Clocks and Power Control MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 10-6 F re escale Sem icondu ctor 10.7 PL L Pins T able 10-1 shows dedica t ed PLL pins. T able 10-1. Dedicated PLL Pins Signal Des cription VCCSYN 1 Drain v ol t age —Analog VDD dedicated to core anal og PLL circuit s.

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Cl ocks and Po w er C ontrol MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 10-7 Figure 10- 4 shows the filtering circuit for VCCSYN and VC CSYN1, described in T able 10-1 .

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Clocks and Power Control MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 10-8 F re escale Sem icondu ctor 10.8 System Clock Contr ol Register (SCCR) The system cloc k control register ( SCCR), shown in Figure 10- 5 , is memory-mapped into the Powe rQUI C C II’ s i nternal s pace.

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Cl ocks and Po w er C ontrol MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 10-9 10.9 System C loc k Mode Regist er (S CMR) The system clock mode regist er (SCMR), shown in Figure 10-6 , holds the para meters which determine the output clock f r equenc ies.

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Clocks and Power Control MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 10-10 F re escale Sem icondu ctor The relationships among these para meters are described in the f or mulas in Figure 10-7 . Figu re 10- 7. Relat ions hips of SC MR Para meters SCMR[CORECNF] bit values are shown in T able 10-4 .

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Cl ocks and Po w er C ontrol MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 10-11 10 .1 0 Bas ic P o wer Str uctu re The I/O b uf fers, logic, and clock block are fed by a 3. 3-V power supply that allows them to function in a TTL-compatible voltage r ange.

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Clocks and Power Control MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 10-12 F re escale Sem icondu ctor The PowerQUICC II supports the two following power mode s: • Full mode—B oth the chip PLL and cor e PLL work. • Stop mode—M ain PLL is working, core PLL is s topped, and i nternal clocks ar e disabled.

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 11-1 Chapter 1 1 Memo r y Cont r oller The memory controller is responsible for controlling a maximum of tw.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 11-2 F re escale Sem icondu ctor • 18-bit addr e ss and 32- bit local data bus memor y controller .

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 11-3 11.1 Featur es The mem ory contr oller ’ s main features are as follows : • T.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 11-4 F re escale Sem icondu ctor — User -specified control-signal patterns run when an inter nal or ext ernal master request s a single-beat or burst read or write access .

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 11-5 Figure 11-2. Memo ry Controller Machine Selection Some f eatures are common to all machines.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 11-6 F re escale Sem icondu ctor Figure 11-3. Simple S ystem Configuration Implementation dif ferences betwe en th.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 11-7 Figure 11-4. Basic Me mor y Controller O peration The SDRAM mode registers (LSDMR and PSDM R) defi ne the global parameters f or the 60x and local SDRAM devices.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 11-8 F re escale Sem icondu ctor register ea ch time a bus -cycle access is reques t ed. If a match is f ound together with bank match, the bus cycle is defined as a page hit.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 11-9 • An ECC double- bit error • An ECC single bi t error when the maximu m number of ECC erro r s has be en reache d 11.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 11-10 F re escale Sem icondu ctor Note that this fea ture cannot be used with L2 cach eable banks and that in sys .

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 11-11 11.2.1 3 P ar t ial Dat a V alid In dica tion (PSD V AL ) The 60x a nd local bus es have an internal 64-bi t data bus. According to the 60x bus specification, T A is asserted when up to a double word of data is transferred.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 11-12 F re escale Sem icondu ctor 11.2.14 B ADDR[ 27:31] Signal Connections The memory controller uses BADDR[ 27:31] to in terface m emory and peripheral devices on the 60x bus in 60x-compatible mode.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 11-13 11.3.1 Bas e Regi ste rs (BR x ) The base registers (BR0–BR1 1) contain the base addres s and address types that the memory controller uses to compare the address bus valu e with the cur r e nt address ac cessed.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 11-14 F re escale Sem icondu ctor 23 WP Write pr otect . Can re st rict write acce sses within t he address r ange of a BR.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 11-15 11.3.2 Optio n Reg isters (O R x ) The O R x r egis ters define the sizes of memory ba nks and acc ess attributes. The OR x a t tr ibutes bits support the following thr ee modes of operation as def ined by BR[MS].

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 11-16 F re escale Sem icondu ctor T able 11-5. OR x Fi eld Descripti ons (SDRAM Mode) Bits Name Descripti on 0–11 SD AM SDRAM ad dr es s mask. Provi des mask ing f or corres ponding BR x bit s.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 11-17 Figure 1 1-8 shows OR x as it is formatted for GPCM mode. T able 1 1-6 desc r ibes ORx f ields in GPCM mode. 26 PMSEL Pag e mode sele ct.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 11-18 F re escale Sem icondu ctor 19 BCTLD Dat a bu ffer contr ol di sab le. Disab l e s t he assertion of BCTL x (60x bu s) and L WR (l ocal b us) during an access to t he current memory bank.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 11-19 NO T E GPCM produces a glitch on the BSx lines when the f ollowing memory controller settings are used: SET A = 1, CSNT = 1, ACS = 01, T RLX = 1, and SCY = 0000.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 11-20 F re escale Sem icondu ctor 11.3.3 60x SDRAM M ode Register ( PSDMR) The 60x SDR AM mode register (PSDM R), shown in Figure 1 1-10 , is used to configure opera t ions pertaining to SDRA M.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 11-21 T able 11-8. PSDMR Field Descriptions Bits Name Descript ion 0 PBI P age-based interl ea ving. Selects t h e address multipl exing method.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 11-22 F re escale Sem icondu ctor SDRAM Devi ce–Specific P aramet ers: 14–16 RFRC Refre sh recov er y . Defi nes the e arl ies t timi ng for an acti v ate command af t e r a REFRESH command .

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 11-23 11.3.4 Lo cal Bu s SD RAM Mo de Re gister ( LSDMR) The LSDMR, shown in Figure 1 1-10 , has th e same fi elds as the P SDMR . T able 11- 9 describes LSDMR fie lds .

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 11-24 F re escale Sem icondu ctor 2–4 O P SDRAM oper ation. Select s th e oper at i on that occur s when the SDRAM de vice is acces sed. 000 Normal operati on 001 CBR refresh, used in SDRAM init i ali zation.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 11-25 SDRAM Devi ce–Specific P aramet ers: 14–16 RFRC Refre sh recov er y . Defi nes the e arl ies t timi ng f or a n a ctiv ate command af t e r a R EFRESH co mmand.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 11-26 F re escale Sem icondu ctor 11.3.5 Machine A/B/C Mode Re gisters ( M x MR) The machine x mode registers (M x MR), shown in Fi gur e 1 1-1 1 , contain the configur ation for the three UPMs.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 11-27 T able 11-10. Machi ne x M ode Registers (M x MR) Bits Name Descr iptio n 0 BSEL Bus sel ect. Assigns banks t hat s elect UPM x to the 60x or local b us.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 11-28 F re escale Sem icondu ctor 11.3.6 Mem ory Data Register ( MDR) The memor y data register ( MDR), s hown i n Fig ure 1 1-12 , contains da t a written to or read from the RAM ar ra y f or U P M RE A D or WRIT E commands.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 11-29 T able 1 1-1 1 describes MDR f ields. 11.3.7 Me mor y Addr ess Re giste r (MAR ) The memory addr ess register (MAR) is shown in Figure 1 1-13 .

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 11-30 F re escale Sem icondu ctor 11.3.8 60x B us- Ass igne d U PM Re fres h Tim er ( PURT) The 60x bus assigned UPM refresh timer r egister (PUR T ) is shown in Figure 1 1-14 .

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 11-31 11.3.10 60x Bus-Ass igned SDRAM Refresh Timer (PSRT ) The 60x bus assigned SDRAM refresh timer register (PSR T ) is shown in Figure 1 1-16 .

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 11-32 F re escale Sem icondu ctor T able 1 1-16 describes LSR T fiel ds. 11.3.1 2 Me mory Re fres h Ti mer P res caler Re giste r (M PTP R) Figure 1 1-1 8 shows the memory refre sh timer pres c aler re gis te r (MP T PR).

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 11-33 11.3.1 3 60 x Bus Error Sta tus an d Con trol Reg isters (TE SCR x ) These regist ers indic ate the source of a n error that caus ed TEA or M CP to be asserted on the 60x bus.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 11-34 F re escale Sem icondu ctor y Figure 11-19. 12 8-Mbyte S D RAM (Eight-Bank Configuration, Banks 1 and 8 Show.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 11-35 11.4.1 Suppor ted SDRAM Configurations The PowerQUICC II memory controller suppo.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 11-36 F re escale Sem icondu ctor 11. 4.4 P age -Mode Support a nd Pipe line A cce sse s The SDRAM inter face supports ba ck-to-back page m ode. A page remains open as long as back-to-back accesse s that hit the page are generated on the bus.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 11-37 11.4.5 Ban k Inter leaving The SDRAM interface supports ban k interleaving.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 11-38 F re escale Sem icondu ctor Note that i n 60x-compatible mode, the 60x address must be latched and multiplexed by glue l ogic that is controlle d by ALE and SDAMUX, however , the user still has to configure PSDMR[SDAM].

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 11-39 • Last data out to precharge (P/LSDMR[LDOTOPR E]). Section 1 1.4.6.4, “Last Data Out to Prechar ge .” • W ri te rec overy , l ast d ata in to prechar ge (P/LSDMR[W RC]).

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 11-40 F re escale Sem icondu ctor Figure 11-21. A CTTOR W = 2 (2 Cloc k Cyc les) 11.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 11-41 11.4.6.4 Last Data Ou t to Prec harge As shown in Figure 1 1-23 , this par a meter , controlle d by P/LSDMR[ LDOTOPRE ], defines the earliest timing for the PRECHAR GE command after the las t da ta wa s rea d f rom the SDR AM.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 11-42 F re escale Sem icondu ctor 11.4.6.6 Refresh Recovery Inte rv al (RFRC) As represented in Figur e 1 1-25 , this pa ra meter , controlled by P/LSDMR[RFRC], defines the earliest timing f or an ACTIVA TE comm and after a REF RE SH command.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 11-43 P/LSDMR[BUF CMD] should be set. Setting this bit caus es the memory contr oller to add one cycle for each SDRAM command. Figure 1 1-27 illustrate s the timing when BUFCMD equals 1.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 11-44 F re escale Sem icondu ctor Figure 11-29. SDRAM Si ngle-Beat Read, P ag e Hi t, CL = 3 Figure 11-30 . S DRAM T wo-Beat Bur st Read, Pag e Closed, CL = 3 Figure 11-31.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 11-45 Figure 1 1-32. SDRAM Singl e-Beat Write, P age Hit Figure 11-33.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 11-46 F re escale Sem icondu ctor Figure 11-35. SDR AM Write-after-Write Pipelined, P a ge Hit Figure 11-36.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 11-47 11.4.9 SDRAM M ODE -S ET Command T iming The PowerQUIC C II transfers mode regis t er data (C AS latency , bur st length, burst type) stored in P/LSDMR to the SDRAM ar ray by issuing the MODE - SET c om mand.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 11-48 F re escale Sem icondu ctor There are two levels of r efresh request priority—low and high.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 11-49 11.4.12.1 SDRAM Configuration Example (Pa g e-Based Interleaving) Consider the following SDRAM organization: • 64-bit port size, or ganized as eight 64-Mbit devices, each org a nized as 8M x 8bits.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 11-50 F re escale Sem icondu ctor Because AP alternates with A [7] of the r ow lines, set P SDMR[SDA10] = 011. This outputs A[7] on the SDA10 line dur ing the ACTIVA T E comm a nd and AP during RE AD / WRITE and CBR commands .

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 11-51 Now , fr om the SDRAM device point of view , during an ACTIVATE comm a nd, its addr e ss por t should look like T able 1 1- 27 . T able 1 1-20.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 11-52 F re escale Sem icondu ctor The GP CM allows a gl ueless and flexible interfa ce between th e Power QUICC II, SRAM, EP ROM, FEPROM, RO M devices, and external peripherals.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 11-53 11.5.1 Ti ming Config uratio n If BRx[ MS] selects the GPCM , the at tributes f or the memo ry cycle ar e taken from OR x . These attributes include the C S NT , AC S[0–1], SCY[0–3], TRLX, EHT R, and SET A fields.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 11-54 F re escale Sem icondu ctor • One quarter of a c lock cycle later • One half of a clock cycle later Note.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 11-55 Figure 11-43. GP CM Memory Device Interface As Figure 1 1-45 shows, the timing for CS is the same as for the addres s lines.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 11-56 F re escale Sem icondu ctor Figur e 11-45. GPCM M emory Device Ba si c Timing (A CS ≠ 00, CSNT = 1, TRLX = 0) 11.5.1.3 Relaxed Timing OR x [TRLX] is provided for memory sys tems that require more relaxed timing between signals.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 11-57 Figure 11-47 . GPCM Relaxed-Timing W rite (A CS = 1x, S CY = 0, CSN T = 0 ,TRLX = 1) When TRLX and CSNT are set i n a write-mem ory access, the strobe l ines, WE [ 0–7] are negated one clock earlier t han in the normal case.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 11-58 F re escale Sem icondu ctor Figur e 11 -49. GP CM Relaxed-Timing Writ e (ACS = 00, SCY = 0, CSNT = 1, TRLX = 1) 11.5.1.4 Output Enable (OE ) Tim ing The timing of the OE is affected only by TRLX.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 11-59 11.5.1.6 Extended Hol d Time on Read Accesses Slow memory devices that take a long time to turn off their data bus drivers on read accesses s hould choose some combina tion of OR x [29–30] (TRLX a nd EHTR).

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 11-60 F re escale Sem icondu ctor Figure 11-51 . GPCM Read Follo wed by Read (OR x [29–30] = 01 ) Figure 11-52.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 11-61 Figure 11-53. GP CM Read Followed b y Write (OR x [29–30] = 1 0) 11.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 11-62 F re escale Sem icondu ctor Figure 11-54 . External T erminati on of GPCM Access 11.5.3 Boo t Chi p-Sele ct Op erat ion Boot chip-select operation allows address de coding for a boot ROM before system initialization.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 11-63 11.5.4 Differences between MPC8xx’ s GPCM a nd MPC82xx’ s GPCM Users famili .

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 11-64 F re escale Sem icondu ctor value driv en on the external mem ory control l e r pins for a given cl ock cycle.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 11-65 • Read bur st cy cle pattern (RBS) • W rite single-beat pattern (WSS) • W rite burst c ycle pattern (WBS) These patterns are described in Section 1 1.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 11-66 F re escale Sem icondu ctor 11.6.1.1 Memor y Access Requests When an internal device reque sts a new access to ext ernal memory , the address of transfer is compared to each valid bank defined in BR x .

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 11-67 11.6.1.3 Software Req uests— RUN Command Software can star t a request to the UPM by issuing a RUN comm and to the UPM.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 11-68 F re escale Sem icondu ctor NO T E For int e ger clock r atios, the widths of T1/2/3/4 are equal, for a 1:2. 5 clock ratio, T1 = 4/3*T2 and T3 = 4/3*T4, and for a 1:3.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 11-69 Figure 1 1-6 0 shows how CSx , GPL 1 , and GPL2 can be controlled. A word is r e ad from the RAM that specifies on every clock cycle t he logical b its CST1, CST 2, CST3, CST4 , G1 T1, G1 T3 , G2T1, and G2T3.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 11-70 F re escale Sem icondu ctor Figure 11-61. RAM Array and Signal Generation 11.6.4.1 RAM W or ds The RAM word, shown in Figure 1 1-62 , is a 32-bit microinstruction stored in one of 64 l oc ations i n the RAM array .

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 11-71 T able 1 1-36 desc ri b e s RAM w o rd fi e l d s. T abl e 11-36 . RAM W ord Bit S etti ngs Bit Nam e Descri ption 0 CST1 Chi p- s el e ct timi ng 1.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 11-72 F re escale Sem icondu ctor 12 G1T1 General-p ur pose line 1 ti mi n g 1.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 11-73 20 G5T1 General-p ur pose line 5 ti mi n g 1.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 11-74 F re escale Sem icondu ctor Additional information about some of the RAM wor d fields is pr ovided in the following sections.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 11-75 Figure 11-63. CS Signal Selection 11.6.4.1 .2 Byt e-Select S ignals (B x T x ) BR x [MS] of the acce ssed memory bank s elects a UP M on the current l y reques ted cycle.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 11-76 F re escale Sem icondu ctor 11.6.4.1 .3 Ge neral-Pu rpose Signa ls (G x T x , GO x ) The general-purpose s i.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 11-77 11.6.4.2 Address Multiplexing The address lines can be controlled by th e pattern the user p rovides in the UPM.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 11-78 F re escale Sem icondu ctor Figur e 11 -65. UP M Read A ccess Data S am pling 11.6.4.4 Signals Nega tion When the LAST bit is read in a RAM word, the curren t UP M pattern terminates.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 11-79 Figure 11-66. W ai t Mecha nism Timing for Interna l and E xternal Syn chr ono us Masters 11.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 11-80 F re escale Sem icondu ctor This means that the address bus should be par titi oned as s hown in T able 1 1-39 .

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 11-81 to logic 0) at the end of that cycle, unless there is a back- to-back UPM cycle pe nding. In many cases this allows the UPM routine to finish one cycle ea rlier because it is now possible and desired to assert both UT A and LAST .

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 11-82 F re escale Sem icondu ctor After ti mings are create d, progr amming the UPM continues with translating the se timi ngs into tables representing t he RAM array c o ntents for each pos sible cy cle.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 11-83 Figure 11-68. Single-Beat Read Access to FPM DRAM c s t 1 000 B i t 0 c s t 2 00.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 11-84 F re escale Sem icondu ctor Figure 11-69. Single-Beat W rite Acces s to FPM DRAM c s t 1 000 B i t 0 c s t 2.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 11-85 Figure 11 -70. Bur st Read Access to FPM DRAM (No L OOP) c s t 1 000000000 B i t.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 11-86 F re escale Sem icondu ctor Figure 11-71. B urst Read Access to FPM DR AM (L OOP) c s t 1 000 B i t 0 c s t .

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 11-87 Figure 11-72 . Bur st Write Acc ess to F PM DRAM (No LOO P) c s t 1 000000000 B .

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 11-88 F re escale Sem icondu ctor Figure 11-73. Refresh Cycle (CBR) to F PM DRAM c s t 1 100 B i t 0 c s t 2 100 B.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 11-89 Figure 11-74. Ex ception Cycl e • If GPL_4 is not used as an out put, the performan ce for a page read access can be improved by setting M x MR[GPL_x4DIS].

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 11-90 F re escale Sem icondu ctor The timing diagram in Figure 1 1-75 shows how the burst-r ead acces s shown in Figure 1 1- 70 can be reduced.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 11-91 Figure 11 - 75. FPM DRA M Burst R ead Acces s (Data S ampling on Falling E dge o.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 11-92 F re escale Sem icondu ctor 11.7.0.1 EDO Interface Example Figure 1 1-7 6 shows a memory connection to exte nded data-out type devices. For this connection, GPL 1 is connected to the memory device’ s OE pins.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 11-93 Disab le timer per iod M x MR[ DS x ]0 b 1 0 Burst inhibi t de vice OR x [BI] 0 b 0 T a ble 11-44.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 11-94 F re escale Sem icondu ctor Figure 11-77. Si ngle-Beat Read Access to EDO DRAM c s t 1 00000 B i t 0 c s t 2.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 11-95 Figure 11-78. Si ngle-Beat Write Access to EDO DRAM c s t 1 0001 B i t 0 c s t 2.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 11-96 F re escale Sem icondu ctor Figure 11-79. Single-Beat W rite Access to EDO DRAM Using REDO to I n sert Three.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 11-97 Figure 11 -80. Bur st Read Access to EDO DRAM c s t 1 0000000000 0 B i t 0 c s t.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 11-98 F re escale Sem icondu ctor Figure 11 - 81. Bu rst Write Access to EDO DRAM c s t 1 0000000000 B i t 0 c s t.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 11-99 Figure 11-82. Refr esh Cycle (CBR) to EDO DRAM c s t 1 10001 B i t 0 c s t 2 100.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 11-100 F re escale Sem icondu ctor Figure 11-83. Exception Cycle Fo r EDO DRAM cst 1 1 Bit 0 cst 2 1 Bit 1 cst 3 1.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 11-101 11.8 Handl ing De vic es with Slo w or V ari able Acce ss Times The memory cont.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 11-102 F re escale Sem icondu ctor There are two types of external bus masters: • Any 60x-compatible device with.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 11-103 is sampled in the GPCM or after each RE AD / WR ITE command in the SDRAM machine (the SDRAM machine uses B ADDR only for por t sizes of 16 or 8 bits).

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 11-104 F re escale Sem icondu ctor Figure 11-84 . Pi pelined Bus Op eration and Memor y Ac cess in 60x-Compatible Mode Figure 1 1-8 5 shows the 1-cycle delay f or external mas ter acce ss .

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 11-105 Figure 11-85. Extern al Master Acces s (GPCM) 11.

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Mem ory C ontro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 11-106 F re escale Sem icondu ctor Figure 11-86. External Master Configu rati o n with SDRAM Device SDA MUX TT[0�.

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 12-1 Chapter 1 2 Seconda r y (L 2) Cach e Suppor t The PowerQUICC II has features to support an externally .

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Se con dar y (L2 ) C ache Su ppo rt MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 12-2 F re escale Sem icondu ctor Figur e 12-1. L2 Cache in Copy-Back Mode 12. 1.2 Wr ite- Thr ough Mode In write-through mode, cacheable write operations ar e performed to both the L2 cache and to main memory .

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Se con dar y (L 2) Cach e S upp or t MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 12-3 mode sacrifice s some of t he write pe rfor mance of copy-back mode, but guar a ntees L2 cache coherency with main memory .

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Se con dar y (L2 ) C ache Su ppo rt MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 12-4 F re escale Sem icondu ctor Figure 12-2. External L2 Cache in Write-Through Mode 12.1.3 ECC/P ari ty Mode ECC/parity mode i s a subset of write-through mode with some c onn ection cha nges that allow the L2 cache to support ECC or Parity .

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Se con dar y (L 2) Cach e S upp or t MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 12-5 In ECC/parity mode the L2 ca che can support me mor y regions wit.

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Se con dar y (L2 ) C ache Su ppo rt MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 12-6 F re escale Sem icondu ctor Figure 12-3. External L2 Cache in ECC/P arity Mode 12.

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Se con dar y (L 2) Cach e S upp or t MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 12-7 • BCR[L2D] = 0—L2 re sponse time. In this case, the L2 will claim a bus transaction one clock cycle after TS assertion.

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Se con dar y (L2 ) C ache Su ppo rt MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 12-8 F re escale Sem icondu ctor Figure 12-4. Read Access with L2 Cache CLK BR BG Addr TS ABB A0 &a.

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 13-1 Chapter 1 3 IEEE 114 9.1 T est Acc ess P or t The PowerQUIC C II provides a dedicated user-acces sibl e test acces s port (T AP) that is fully compatib le with the I E EE 1 149.

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IE EE 1149 .1 T es t Ac cess P ort MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 13-2 F re escale Sem icondu ctor Figure 13-1. T est Logic Block Dia gram The T AP consists of the s ignals in T able 13-1.

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IEE E 114 9.1 Te st A ccess Port MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 13-3 Figure 13-2. T AP Co ntroller State M achine 13.

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IE EE 1149 .1 T es t Ac cess P ort MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 13-4 F re escale Sem icondu ctor Figur e 13- 3. Output P in Ce ll (O.

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IEE E 114 9.1 Te st A ccess Port MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 13-5 Fi gure 13- 5. Out put C ontr o l Cel l ( IO .C TL ) Figu re 13-6 . Gener al Arra nge men t of Bidire ctiona l Pin C ell s The contr ol bit value controls the outpu t function of th e bidirectional pin.

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IE EE 1149 .1 T es t Ac cess P ort MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 13-6 F re escale Sem icondu ctor from the shift register to the parallel outputs during the update-I R controller state. The four bits ar e used to decode the five unique ins tructions listed in T able 13-2 .

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IEE E 114 9.1 Te st A ccess Port MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 13-7 The parallel output of the instruction register is set to all ones in the test-logic-reset controller state. Noti ce that this pres et state is equivalent to the BYP ASS instruction.

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IE EE 1149 .1 T es t Ac cess P ort MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 13-8 F re escale Sem icondu ctor.

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or IV -1 Pa r t I V Comm unica tions Pr ocess or Module Intended A udi ence Part IV is i ntended for s ystem designers who need to implement various communications protocols on the PowerQUICC II .

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 IV -2 F reescal e Semicondu ctor • Chapter 23, “ SCC BISYNC M ode,” describes t he PowerQUICC II implementation of byte-oriented BISYNC pr otocol develope d by IBM f or use in networking products.

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or IV -3 • Chapter 40, “Paralle l I/ O Port s,” describes the four general-purpose I/O ports A–D.

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 IV -4 F reescal e Semicondu ctor x In certain contexts, such as in a signal encoding or a bi t f ield, indicates a don’t care.

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or IV -5 T able IV -1. Acron ym s and Abbre viated T erms T erm Meani ng AAL A TM adaptat ion lay er ABR Av ai.

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 IV -6 F reescal e Semicondu ctor GCRA Gener i c cell rat e alg or ithm (l eaky buck et) GPCM General - p ur pose chi p-sel ect mach ine.

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or IV -7 PH Y Physi ca l layer PPM Pulse-posi tion modul ation RM Resour ce manag ement R T Real-ti m e R T OS.

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 IV -8 F reescal e Semicondu ctor.

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 14-1 Chapter 1 4 Comm unica tions Pr oc essor Mo dule Overvi ew The PowerQUICC II’ s communications pr ocessor module (CPM ) is a superset of the MPC860 PowerQUICC CPM, with enhancements in per form ance.

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Co mm un icati ons Pr oces sor Modu le Ov ervi ew MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 14-2 F re escale Sem icondu ctor — Synchronous UAR T (1x clock m ode) — Binary sy.

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Com municat ions P rocesso r Modu le O verv iew MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 14-3 Figure 14- 1 shows the PowerQUICC II ’ s CPM blo ck diagram. Figu re 14-1. P owerQUICC I I CPM Block Dia gram 14.

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Co mm un icati ons Pr oces sor Modu le Ov ervi ew MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 14-4 F re escale Sem icondu ctor 14.

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Com municat ions P rocesso r Modu le O verv iew MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 14-5 • 64-bit dual-port RAM access • Optimi zed for communica tions processing • Performs DMA bur sting of serial data from/to dua l-port RA M to/fro m external memory .

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Co mm un icati ons Pr oces sor Modu le Ov ervi ew MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 14-6 F re escale Sem icondu ctor Figure 14-2.

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Com municat ions P rocesso r Modu le O verv iew MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 14-7 • Many parameters are exchanged through the dual- port RAM. • The CP can execute special commands is sued by the core.

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Co mm un icati ons Pr oces sor Modu le Ov ervi ew MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 14-8 F re escale Sem icondu ctor 14. 3. 6 Ex ecutio n fr om RAM The CP has an option to execute microcode fr om a por tion of user RA M located in the dual-port RAM.

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Com municat ions P rocesso r Modu le O verv iew MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 14-9 RCCR bi t fields are described in T able 14-3 .

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Co mm un icati ons Pr oces sor Modu le Ov ervi ew MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 14-10 F re escale Sem icondu ctor 12 EIE Exter n al interrupt enabl e. When EIE is set, DREQ1 acts as an e xternal inter rupt to the CP .

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Com municat ions P rocesso r Modu le O verv iew MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 14-11 14.3.8 RIS C Tim e-Stam p Co ntr o l R egister (RTSCR) The RISC t ime-sta mp control regis ter (R TS CR), shown in Figure 14-4 , configur es the RISC time-sta mp timer ( R TSR).

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Co mm un icati ons Pr oces sor Modu le Ov ervi ew MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 14-12 F re escale Sem icondu ctor After reset, setting R TSCR[R T E] causes the tim e stamp to s tart counting microseconds from zero. 14.

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Com municat ions P rocesso r Modu le O verv iew MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 14-13 14.4.

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Co mm un icati ons Pr oces sor Modu le Ov ervi ew MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 14-14 F re escale Sem icondu ctor 14.4.1.1 CP Commands The CP command opcodes are shown in T a bl e 14-7 . 6–10 SBC Sub-b loc k code. Set by the c ore to speci fy the su b-bloc k on which t he command i s to ope rate.

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Com municat ions P rocesso r Modu le O verv iew MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 14-15 T a ble 14- 7.

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Co mm un icati ons Pr oces sor Modu le Ov ervi ew MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 14-16 F re escale Sem icondu ctor NO T E If a reserved command is is sued, the C PM enters an unknown state that requires an external res et to re cover .

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Com municat ions P rocesso r Modu le O verv iew MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 14-17 14.4.2 Com mand Registe r Exam ple T o perf orm a complete reset of the CP , the value 0x8001_0000 s hould be written to the CPCR.

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Co mm un icati ons Pr oces sor Modu le Ov ervi ew MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 14-18 F re escale Sem icondu ctor Figure 14-7.

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Com municat ions P rocesso r Modu le O verv iew MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 14-19 Figure 14 - 8 .

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Co mm un icati ons Pr oces sor Modu le Ov ervi ew MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 14-20 F re escale Sem icondu ctor unused par ameter RAM, suc h as, in the area made av ailable when a pe r ipheral controller or s ub-block is not being used.

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Com municat ions P rocesso r Modu le O verv iew MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 14-21 T a ble 14-10.

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Co mm un icati ons Pr oces sor Modu le Ov ervi ew MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 14-22 F re escale Sem icondu ctor 14 .6 RI SC Time r T ab les The CP can contr ol up to 16 software timers that a re separate fr om the four gene ral-pur pose timers and th e BRGs in the CP M.

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Com municat ions P rocesso r Modu le O verv iew MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 14-23 Figure 14-9. R ISC Timer T able RAM Usa g e The RISC t imer table parame ter R AM a rea begins at the R ISC timer bas e addre ss and i s used for the genera l timer pa ra mete rs; see T able 14-1 1 .

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Co mm un icati ons Pr oces sor Modu le Ov ervi ew MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 14-24 F re escale Sem icondu ctor 14.6.2 RISC Timer Comman d Register (T M_CMD) Figure 14- 10 shows the RISC timer com mand register (TM_ C MD).

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Com municat ions P rocesso r Modu le O verv iew MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 14-25 14.6.5 SET TIME R Com mand The SE T TIMER command is used to e nable, disable , and c onfigure the 1 6 timer s in the RISC timer table and is is sued to the CPC R.

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Co mm un icati ons Pr oces sor Modu le Ov ervi ew MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 14-26 F re escale Sem icondu ctor 14.6.7 RISC T imer In itial izatio n Exam ple The following sequence initializes RISC timer 0 to gene rate an interrupt approximately every second using a 133-MHz gene ral system clock: 1 .

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Com municat ions P rocesso r Modu le O verv iew MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 14-27 If a SE T TI ME R command is issued, the CP make s the appropriate modificati ons to the timer table and paramete r R AM, but does not s can the timer table until the next tick of the i ntern al timer .

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Co mm un icati ons Pr oces sor Modu le Ov ervi ew MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 14-28 F re escale Sem icondu ctor.

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 15-1 Chapter 1 5 Seri al In terface with Time-Slo t Assigner Figure 15- 1 shows a block dia gram of the time-s lot ass igner (TSA) .

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Serial Inte rface with Time-Slot Assig ner MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 15-2 F re escale Sem icondu ctor Fig ure 15-1 . SI Bl oc k Di a gram If the T S A is not us ed as intende d, it can be used to generate compl ex wave f or ms on dedicated output pins.

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Serial In terface wi th Time-Slot As signer MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 15-3 15.1 Featur es Each SI has the following features: • Can connect to four independent TDM channe ls.

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Serial Inte rface with Time-Slot Assig ner MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 15-4 F re escale Sem icondu ctor • Independent mapping f or receive/transmit • Individual channel echo or loop mode • Global echo or loop mode through the SI 15 .

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Serial In terface wi th Time-Slot As signer MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 15-5 Fi gure 1 5- 2.

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Serial Inte rface with Time-Slot Assig ner MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 15-6 F re escale Sem icondu ctor At its most flexi ble, the TSA can provide four separate TDM channels, each with independent recei ve and transmit routing assignments and independent sync puls e and clock input s.

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Serial In terface wi th Time-Slot As signer MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 15-7 to progr am the re ceive routing.

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Serial Inte rface with Time-Slot Assig ner MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 15-8 F re escale Sem icondu ctor Figu re 15- 4.

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Serial In terface wi th Time-Slot As signer MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 15-9 15.4.1 One M ultip lexed Ch anne l wi th Sta tic Fr ame s The example in Figure 15- 5. shows one of many possi ble settings.

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Serial Inte rface with Time-Slot Assig ner MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 15-10 F re escale Sem icondu ctor Figure 15-6. O ne TDM Channel wi t h Shadow RAM fo r Dynamic Route Chan ge This configur ation should be chos en when only one TDM is needed, but dyna m ic rerouting may be needed on tha t TDM.

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Serial In terface wi th Time-Slot As signer MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 15-11 T able 15-1. SI x RAM Entry (MCC = 0) Bits Name Description 0 MCC The entry control s the f uncti onality of the ot her bits in the SI x RAM entry .

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Serial Inte rface with Time-Slot Assig ner MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 15-12 F re escale Sem icondu ctor Figure 15- 8 shows how SWTR ca n be used. Figure 15-8. Using the SWTR Fe ature The SWTR option lets station B listen to transmissions from s tation A and send data to station A.

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Serial In terface wi th Time-Slot As signer MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 15-13 T able 15-2. SI x RAM Entry (MCC = 1) Bits Name Description 0 MCC If MCC =1, t he other SI x RAM entries in thi s tabl e ar e v ali d: 1L O O P / ECHO Channel l oopba ck or echo .

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Serial Inte rface with Time-Slot Assig ner MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 15-14 F re escale Sem icondu ctor 15.4.4 S I x RAM Pr ogrammi ng E xampl e This example shows how to progr am the RAM to s upport the 10-bit IDL bus.

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Serial In terface wi th Time-Slot As signer MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 15-15 • Static routing. The number of SI x R AM entries is determined by the banks t he user relates to the corresponding TDM and is divided i nto two parts (Rx and T x) .

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Serial Inte rface with Time-Slot Assig ner MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 15-16 F re escale Sem icondu ctor Figure 15-9.

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Serial In terface wi th Time-Slot As signer MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 15-17 15.5 Seri al Interf a ce Regis ter s The serial in terface register s ar e descr i bed in the following sections.

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Serial Inte rface with Time-Slot Assig ner MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 15-18 F re escale Sem icondu ctor T able 15-5 desc ribes SI x MR fi e lds.

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Serial In terface wi th Time-Slot As signer MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 15-19 6–7 R FSDx Receiv e frame sync del a y f or TDM a, b, c , or d. Determin es t he number of cloc k dela ys between the recei ve sync a nd the first bit of the receiv e fr ame.

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Serial Inte rface with Time-Slot Assig ner MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 15-20 F re escale Sem icondu ctor Figure 15- 12 shows the one-clock delay from sync to data when x FS D = 01.

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Serial In terface wi th Time-Slot As signer MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 15-21 Figure 15-14. Falling Edge (FE) Effect When CE = 1 and x FSD = 0 1 Figure 15- 15 shows the eff e cts of changing FE when CE = 0 w ith a 1-bit frame sync delay .

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Serial Inte rface with Time-Slot Assig ner MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 15-22 F re escale Sem icondu ctor Figure 15-16. Falling Edge (FE) Effect When CE = 1 and x FSD = 0 0 Figure 15- 17 shows the ef f ects of changing FE when CE = 0 w i th no frame s ync delay .

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Serial In terface wi th Time-Slot As signer MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 15-23 Figure 15-17.

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Serial Inte rface with Time-Slot Assig ner MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 15-24 F re escale Sem icondu ctor T able 15-6. describes SI x RS R fi e lds . 15.5.4 SI Co mma nd Re gi ster (SI x CMDR) The SI command re gi s ters (SI x CMDR), s hown in Figur e 15-19 , allow the use r to dynamically program the SI x R AM.

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Serial In terface wi th Time-Slot As signer MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 15-25 15.5.5 SI Sta tus R eg isters (S I x STR) The SI stat us r egister (SI x STR), shown in Figur e 15-20 , iden tifies t he current- route RA M.

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Serial Inte rface with Time-Slot Assig ner MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 15-26 F re escale Sem icondu ctor (physical layer device) and has separate receive and transmit sections.

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Serial In terface wi th Time-Slot As signer MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 15-27 Figure 15-22. IDL T erm i nal Adaptor The PowerQUICC II can identify and support each IDL channel or can out put strobe lines f or int erfacing devices that do not support the IDL bus.

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Serial Inte rface with Time-Slot Assig ner MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 15-28 F re escale Sem icondu ctor The bas i c rate ID L bus has the three f ollowing channel.

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Serial In terface wi th Time-Slot As signer MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 15-29 device negates L1GRx. The PowerQUICC II then s t ops sending and retransmits the frame when L1GRx is reasserte d.

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Serial Inte rface with Time-Slot Assig ner MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 15-30 F re escale Sem icondu ctor 2. CMXSI1CR = 0x00. T DM A rece ive clock is CLK1. 3. CMXSMR = 0x80. SMC1 is connec ted to the TSA . 4. CMXSCR = 0xC040_0000.

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Serial In terface wi th Time-Slot As signer MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 15-31 The GCI bus consist s of four lines—two data lines, a clock, and a frame synchronization line. Usually , a n 8-kHz frame s tructure defines the vari ous channels within the 256-kbps data rate.

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Serial Inte rface with Time-Slot Assig ner MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 15-32 F re escale Sem icondu ctor • M is a 64-Kbps monitor channel • D is a 16-Kbps sign.

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Serial In terface wi th Time-Slot As signer MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 15-33 signals to the SI x RAM transmit section, using the CR Tx bits. The user should then defin e the GCI f rame routing and s trobe select using the S I x RAM .

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Serial Inte rface with Time-Slot Assig ner MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 15-34 F re escale Sem icondu ctor NO T E If SCIT mode is not used, dele te the last thr ee entries of the SI x RAM, divide one entry in to two and set the LST bit in t he new las t entr y .

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 16-1 Chapter 1 6 CPM Mu ltiple xing The CPM multiplexing logic (CMX) connec t s the physica l layer—UTOP IA, MII, modem lines, TDM lines and pr opr ietary serial l ines to the FC Cs, SCCs and SM Cs.

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CPM Mult iplexin g MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 16-2 F re escale Sem icondu ctor Figure 16-1. CPM Multiplexing Logic (CMX) Bloc k Diagram 16.

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CPM Mu ltipl exin g MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 16-3 • Each SCC can have its own set of modem control pins. • Each SMC ca n have its own set of four pins. • Each FCC, SC C, and SM C can be dr iven from a bank of twenty clock pins or a bank of eight BRGs.

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CPM Mult iplexin g MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 16-4 F re escale Sem icondu ctor Figu re 16- 2. Enabli ng Con nect ions to t he TSA 16.3 NMSI C onfiguration The CMX supports an NM S I mode for each of the FCC s, SCCs, and SMCs.

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CPM Mu ltipl exin g MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 16-5 Figure 16-3. B ank of Clocks The eight BRGs als o make their clocks available to e xt ernal logic, regardles s of whet her the BRGs are being used by a serial device.

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CPM Mult iplexin g MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 16-6 F re escale Sem icondu ctor T able 16-1. Clock Sour ce Options Clock CLK BRG 12345 678 9 1 0 1 1 1 2 1 3 1 4 1 .

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CPM Mu ltipl exin g MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 16-7 NO T E After a clock source is selected, the clock is given an internal name. For the FCCs and SCCs, the names ar e R CLK x and T CLK x ; for SMCs, the name is simply SMCL K x .

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CPM Mult iplexin g MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 16-8 F re escale Sem icondu ctor NO T E Each SADx and M ADx corresponds to a pair of separate receive and tran smit address pins. The PowerQUICC II ha s 16 output addres s pins and 10 input address pins dedicated for the UTOPI A interfac e.

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CPM Mu ltipl exin g MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 16-9 Figure 16 - 5. Connection of th e Master Address • For slave mode—The user has two gr oups of five address pins each. The user decides which FCC uses each pin by programming CMXUAR[SAD x ].

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CPM Mult iplexin g MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 16-10 F re escale Sem icondu ctor NO T E The user m ust program the a ddresses of the P HY s to be consecutive f or each FCC; th at is, the a ddress li nes connecte d to each F CC must be c onsecutive.

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CPM Mu ltipl exin g MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 16-11 Figur e 16 -7. Mu lti-PHY Receive Address Multiplexing 1 0 ¬SAD4 1 0 ¬SAD3 1 0 .

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CPM Mult iplexin g MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 16-12 F re escale Sem icondu ctor 16.4.2 CMX SI1 C lock R out e R egist er (CM XS I1CR ) The CMX SI1 clock route register (CMXSI1CR), displayed in Figur e 16-8 , defines the connection of SI1 to the clock s ources that ca n be input f r om the bank of clocks.

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CPM Mu ltipl exin g MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 16-13 T able 16-4 desc ribes CMXSI2CR fields.

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CPM Mult iplexin g MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 16-14 F re escale Sem icondu ctor T able 16-5 desc ribes CMXFCR fi elds.

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CPM Mu ltipl exin g MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 16-15 8-9 FC2 Defines the FCC2 conn ection. 00 FCC2 is not connecte d to th e TSA and is eithe r conne cted d i r ectl y to the NMSIx pin s or is not used.

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CPM Mult iplexin g MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 16-16 F re escale Sem icondu ctor 16.4.5 CMX SCC Clo c k Route Register (CM XSCR) The CMX SCC clock route register (CMXSCR), seen in Figure 16- 1 1 , defines the connection of the SCC s to the T S A and to the clock sources from the bank of clocks.

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CPM Mu ltipl exin g MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 16-17 2–4 RS1CS Recei ve SCC1 cl ock source (NMSI mod e). Igno red if SCC1 is connect ed to the TSA (SC1 = 1). 00 0 SC C1 rec eive cl o ck is BR G1 .

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CPM Mult iplexin g MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 16-18 F re escale Sem icondu ctor 17 SC3 SCC3 connec tion 0 SCC3 is not conne cted to the TSA and is either connected direct ly t o the NMSIx pin s or is not used.

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CPM Mu ltipl exin g MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 16-19 16.4.6 CMX SMC Clock Route Register (CMXSMR) The CMX SM C clock route register ( CMXSMR), shown in F igure 16-12 , defines the connection of the SMCs to th e TSA and to the clock sources from the bank of clocks.

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CPM Mult iplexin g MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 16-20 F re escale Sem icondu ctor 2–3 SMC1CS SMC1 cloc k source (NMSI mode). SMC1 can tak e i t s cloc ks from one of the tw o BRGs or one of two pi ns from t he bank of cl ocks.

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 17-1 Chapter 1 7 Baud-Rate Generato rs (BRG s) The CPM contains eight i ndependent, identical baud-rate generators (BR Gs) that can be used with t he FCCs, SCC s, and SMCs.

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Baud-Rate Gen e rator s (BRGs) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 17-2 F re escale Sem icondu ctor source for multiple BRGs.

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Baud-Rate Generators (BRGs) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 17-3 T able 17-2 shows the possible external c lock sources for the BR Gs. T able 17-1. BRG C x Field Descriptions Bits Name Descripti on 0–13 — Reserved, s hould be clear ed.

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Baud-Rate Gen e rator s (BRGs) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 17-4 F re escale Sem icondu ctor 17.2 A utoba ud O peration on a U ART During the autobaud proces s, a UAR T deduces the baud rate of its received cha racter strea m by exam ining the received pa ttern and its timing.

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Baud-Rate Generators (BRGs) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 17-5 17.3 U ART Baud Rate Exampl es For synchronous communication using the internal BR G , the BRGO must not exceed the BR G input clock divided by 2.

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Baud-Rate Gen e rator s (BRGs) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 17-6 F re escale Sem icondu ctor For example, to get a r ate of 64 kbps, the s ystem clock can be 24.

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 18-1 Chapter 1 8 Ti mer s The C PM includes four identical 16- bit g eneral-purpos e time rs or t wo 32-bit timer s.

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Time rs MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 18-2 F re escale Sem icondu ctor • 16-nanosecond resolution (at 66 MHz) • Programmable sources for the clock input • Inpu.

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Time rs MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 18-3 The restart gate mode performs the same function a s normal mode, except it also resets the counter on the falling edge of TGA TE x .

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Time rs MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 18-4 F re escale Sem icondu ctor T able 18-1 describes TGCR1 f i e lds. The TGCR2 r egister is shown in Figure 18- 4 . 01234567 Field CAS2 — STP2 RST2 GM1 — STP1 RST1 Reset 0000 _0000 R/W R/W Addr 0x0x10D80 Figure 18-3.

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Time rs MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 18-5 T able 18-2 describes TGCR2 f i e lds. 18 .2.3 Time r Mo de R egi ste rs (TM R1–TM R4) The four tim e r mode r egisters (TMR1–TMR4) are shown in Figure 18-5 .

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Time rs MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 18-6 F re escale Sem icondu ctor T able 18-3 describes TMR1–TMR4 register fields. 18 .2.4 Time r R efere nce R egi ste rs (TRR 1–TR R4 ) Each timer re fer e nce register (TRR1–T RR4), shown in Figure 18- 6 , contains the timeout’ s refere nc e value.

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Time rs MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 18-7 18.2.5 Ti mer C aptu re Re gi sters ( TCR1 –TCR 4) Each timer cap ture register (TCR1–TC R4), shown in Figur e 18-7 , is used to latch the value of the counter according to TMR x [CE] .

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Time rs MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 18-8 F re escale Sem icondu ctor W riting ones clea rs event bits; writing ze ros has no ef fect. Both event bits must be cle ared before the time r negates the interrupt. T able 18-4 describes TER fields.

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 19-1 Chapter 1 9 SDMA Chann els and I DMA Em ulation The PowerQU I C C II has two physical serial DM A (SDM A) channels .

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SDMA Chann els a nd IDM A Emu lation MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 19-2 F re escale Sem icondu ctor The SDMA channel can be as signed big-endian (Freescale) or little-endian f ormat for accessing buf fer data.

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SDMA Chan nels and ID MA E mulation MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 19-3 Figure 19-2. S DMA B us Arbitration (T ransaction Steal) 19.

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SDMA Chann els a nd IDM A Emu lation MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 19-4 F re escale Sem icondu ctor 19.2.2 SDMA Mask Reg ist er (SDMR ) The SDMA mask re gist er (SDMR) is an 8-bit read/wr i te register with th e same bit format as t he SDM A status register .

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SDMA Chan nels and ID MA E mulation MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 19-5 19.3 ID MA Em ulati o n The CPM can be conf igured to provide general- purpose DMA f unctionality through the SDMA channel.

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SDMA Chann els a nd IDM A Emu lation MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 19-6 F re escale Sem icondu ctor • Programmable byte-order conversion is s upported independentl.

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SDMA Chan nels and ID MA E mulation MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 19-7 Figure 19- 5 shows the I DMA transfer buf fer . Figure 19-5. IDMA T ransfer Buffer i n the Dual-Po rt RAM Each buffer ’ s contents are t ransferred in three phas es: • First phase.

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SDMA Chann els a nd IDM A Emu lation MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 19-8 F re escale Sem icondu ctor Figure 19-6. Example IDMA T ransfer Buffer States f o r a Memo ry-to-Memo ry T r ansfer (S ize = 128 Bytes) 19.

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SDMA Chan nels and ID MA E mulation MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 19-9 19.5.1.2 Normal Mode When ex t e rnal re quest mode is not s elected (DCM[ERM] = 0) , the I DMA channel ope rates autom atically , ignoring DREQ.

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SDMA Chann els a nd IDM A Emu lation MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 19-10 F re escale Sem icondu ctor Any IDMA acc ess to a peripheral uses the highest arbitr atio n priority allowed f or the D MA, providing faster bus ac cess by bypassing other pe n ding DMA r equests.

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SDMA Chan nels and ID MA E mulation MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 19-11 related to the dual- port RAM bus are not re levant in fl y-by mode. Eac h DREQ assertion triggers a transfer the s i ze of the per ipheral por t.

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SDMA Chann els a nd IDM A Emu lation MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 19-12 F re escale Sem icondu ctor Conversely , i f the transfer s ize is small, the DMA requests the 60x bus more often, DMA latency increases and microcode eff iciency dec reases.

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SDMA Chan nels and ID MA E mulation MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 19-13 19. 6 IDM A P rior ities Each IDMA channel can be programmed to have a higher or l ow er prior ity relative to the seria l controller s or to have the lowest overall pri ority when requesting s ervice from the CP .

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SDMA Chann els a nd IDM A Emu lation MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 19-14 F re escale Sem icondu ctor DREQ x may be conf igured as either edge- or level- s ens itive by programming the RCCR[DR x M].

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SDMA Chan nels and ID MA E mulation MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 19-15 Figure 19-7. T i ming Re quireme nt for DREQ Negation w hen IM D A Read from a Peripheral 19.

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SDMA Chann els a nd IDM A Emu lation MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 19-16 F re escale Sem icondu ctor NO T E When DREQ is level- se nsitive and DONE is an input to the PowerQUICC II, the system des ign must ensure that DONE is not a ss e rted while DREQ is al so asse rted.

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SDMA Chan nels and ID MA E mulation MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 19-17 Figure 19-8. IDMA x Channel’ s BD T abl e Data associ ated with each IDMA channel is stored in buf f er s and each buf fer is referenced by a BD that uses a cir cular table s tructure in the dual-port RAM.

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SDMA Chann els a nd IDM A Emu lation MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 19-18 F re escale Sem icondu ctor T a ble 19-4. IDMA x Param eter RAM Offset 1 Name Widt h Description 0x00 IBASE Hwor d IDMA BD tabl e base addre ss.

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SDMA Chan nels and ID MA E mulation MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 19-19 19.8.2.1 DMA Channel Mode (DCM) The IDMA channel m ode (DCM), s hown in Figure 19-9 , is a 16- bit field within the IDMA pa rameter RAM, that controls t he operation modes of the IDMA channel.

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SDMA Chann els a nd IDM A Emu lation MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 19-20 F re escale Sem icondu ctor T able 19-5. DCM Field Descriptions Bits Name Des cription 0 FB Fly-by mode. See T abl e 19-6.. 0 D ual-add r es s mod e.

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SDMA Chan nels and ID MA E mulation MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 19-21 19.8.2.2 Data T ransfer T ypes as Pr ogrammed in DCM T able 19-6 summarizes the types of data transfers according to the DCM pr ogramming.

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SDMA Chann els a nd IDM A Emu lation MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 19-22 F re escale Sem icondu ctor 19.8.2.3 Programming DTS and STS The options for s etting ST S and DT S depend on (DCM[D MA_WR AP ]) and are des cribed in the f oll owing tables for m e mory/memory and memory/periphe ral trans fers.

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SDMA Chan nels and ID MA E mulation MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 19-23 T able 19-8 desc ribes valid STS/DTS va lues for memory/peripheral oper ations.

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SDMA Chann els a nd IDM A Emu lation MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 19-24 F re escale Sem icondu ctor transfer size s allows longer trans f ers to memor y devices, optimizes bus usage and thus reduces the overall load on the C P .

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SDMA Chan nels and ID MA E mulation MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 19-25 T able 19-10 describes IDMA B D fields.

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SDMA Chann els a nd IDM A Emu lation MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 19-26 F re escale Sem icondu ctor 6 CM Contin uous mode 0 Buffer chaining mode . The CP cle ars V after thi s BD i s serviced. Buff er chai ning mode is u sed to tr ansfer large quantiti es of data int o non-cont i gu ous b uff er area s.

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SDMA Chan nels and ID MA E mulation MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 19-27 19 .9 IDMA Comman ds The user has two commands to control each I DMA channel. These commands are ex ecuted through the CP command r egis ter (CPCR); see Section 14.

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SDMA Chann els a nd IDM A Emu lation MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 19-28 F re escale Sem icondu ctor In external r equest mode ( ERM=1), the ST ART _ ID MA command initializes the channel, but the first data tra nsfer is perf ormed after e xternal DR EQ x assertion.

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SDMA Chan nels and ID MA E mulation MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 19-29 19. 10. 1 Ex t ern a l ly R eco gniz ing ID MA Ope rand T r ansf .

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SDMA Chann els a nd IDM A Emu lation MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 19-30 F re escale Sem icondu ctor T able 19-14 describes parallel I/O re gister programming for por t D (optional).

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SDMA Chan nels and ID MA E mulation MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 19-31 DCM(SINC) = 0 The peripheral address are not i ncrement ed after transf ers , f i x ed loc ation. DCM(DINC) = 1 The memory add ress i s increment ed after e v er y t ransf er .

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SDMA Chann els a nd IDM A Emu lation MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 19-32 F re escale Sem icondu ctor 19. 12.2 Memo ry-to -P e ri ph era l Fl y- By M ode—ID M A3 In the exam ple in T able 19-16 , IDMA3 trans f ers data from a memor y device to a 4-byte wide peripheral, both on the 60x bus.

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SDMA Chan nels and ID MA E mulation MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 19-33 19. 12. 3 M emo ry-to -Memo ry (P CI B us to 60 x Bus )—I DMA 1 NO T E This section applies to the M P C8250, the MPC8265, and the MPC8266 only .

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SDMA Chann els a nd IDM A Emu lation MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 19-34 F re escale Sem icondu ctor DCM[DINC] = 1 The desti natio n memory address i s increment ed afte r e very trans fe r . IBASE=IBDPTR= 0x0 030 The current BD pointer is set to the BD ring Base addres s (al igned 16 -bit s[3–0]=0000 ).

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 20-1 Chapter 2 0 Seri al Comm unications Contro llers (SCCs) The PowerQUICC II ha s four serial communicati.

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Se rial Com muni cat ion s Co ntroll ers ( SC Cs) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 20-2 F re escale Sem icondu ctor Figure 20-1. S CC Block Diag ram 20.1 Featur es The following is a list of the main SCC featur es. (Perfor mance figur es as sum e a 25-MHz system clock.

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Ser ial Comm unica tion s Contr oll ers ( SC Cs) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 20-3 • Fully transparent option for one half of a n S CC (Rx/Tx) w hi le another pr otocol executes on the other half (Tx/Rx) • Echo and lo c al loopback modes for tes ting 20.

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Se rial Com muni cat ion s Co ntroll ers ( SC Cs) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 20-4 F re escale Sem icondu ctor 19–20 TRX, TTX T ran sparent recei ver/ t r an smitte r. The recei v er , tr ansmitter , or bot h can use totally tr a nsparent operat ion, regardl ess of GSMR_L[ MODE].

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Ser ial Comm unica tion s Contr oll ers ( SC Cs) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 20-5 Figure 20- 3 shows GSMR_L. T able 20-2 desc ribes GSMR_L f ields. 28–29 SYNL Sync length (BISYNC and tr ansparent mode onl y).

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Se rial Com muni cat ion s Co ntroll ers ( SC Cs) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 20-6 F re escale Sem icondu ctor 1–2 EDGE Cl o ck e dge. Determines the cloc k edge the D PL L uses t o adju st t he receiv e sample po int due to jitter i n t he receiv ed signal .

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Ser ial Comm unica tion s Contr oll ers ( SC Cs) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 20-7 11–12 TPP Tx pre amb le patte r n. Determines what , if an y , bit patte r n shoul d precede each Tx f r a m e .

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Se rial Com muni cat ion s Co ntroll ers ( SC Cs) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 20-8 F re escale Sem icondu ctor 24–25 DIA G Di a gnostic mode. 00 Nor mal ope ration, CTS and CD ar e under a utomatic con t r ol. Dat a is re ceived t hrough RXD an d tran smitted th rough TXD .

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Ser ial Comm unica tion s Contr oll ers ( SC Cs) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 20-9 20. 1.2 Pr otoc ol- Speci fic Mode Re giste r (PSMR) The protocol implemented by an SCC i s selected by its GSMR_L[MODE].

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Se rial Com muni cat ion s Co ntroll ers ( SC Cs) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 20-10 F re escale Sem icondu ctor 20.

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Ser ial Comm unica tion s Contr oll ers ( SC Cs) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 20-11 — For an RxBD , this is the number of bytes t he controller writes into the buffe r . The CPM writes the length af t er received data is place d into th e associated buf f er and the buf fer c l osed.

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Se rial Com muni cat ion s Co ntroll ers ( SC Cs) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 20-12 F re escale Sem icondu ctor Figure 20 - 7. SCC BD and Buffer Memory Structure In all pr otocols, BDs can point to buff e rs in the internal dua l-port RAM.

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Ser ial Comm unica tion s Contr oll ers ( SC Cs) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 20-13 20. 3 SC C Parame ter R A M Each SCC parame t e r RAM a rea begins at the same offset from each SCC base are a.

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Se rial Com muni cat ion s Co ntroll ers ( SC Cs) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 20-14 F re escale Sem icondu ctor 20.

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Ser ial Comm unica tion s Contr oll ers ( SC Cs) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 20-15 20 .

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Se rial Com muni cat ion s Co ntroll ers ( SC Cs) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 20-16 F re escale Sem icondu ctor 20.

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Ser ial Comm unica tion s Contr oll ers ( SC Cs) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 20-17 Additional information about inte rrupt handling can be found in Section 4. 2, “Interrupt Controller.

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Se rial Com muni cat ion s Co ntroll ers ( SC Cs) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 20-18 F re escale Sem icondu ctor Figure 20-9. Outp ut Delay from RTS Asserted f o r Synchron ous Protocols When R TS is a sser ted, if C TS is no t already asserted, delays to the f i rst data bit depend on when CTS is asser ted.

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Ser ial Comm unica tion s Contr oll ers ( SC Cs) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 20-19 Figure 20-11 . CT S Los t in Sy nchronous Protoco ls Note that if GSMR_H[CTSS] = 1, CTS transiti ons must occur while the T x clock is low .

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Se rial Com muni cat ion s Co ntroll ers ( SC Cs) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 20-20 F re escale Sem icondu ctor Figur e 20- 12. Usi ng CD to Contr o l S y nchr onous Pr o tocol Reception If C D is progra mmed to envelope the data , it must remain a ss erted during frame transmission or a C D lost error occurs.

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Ser ial Comm unica tion s Contr oll ers ( SC Cs) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 20-21 20. 3. 6 Digi tal Pha se- Lock ed Loo p (DPL L) Opera t ion Each SCC channe l includes a digit al phase-locked loop (DPL L) for recoveri ng clock information fr om a received data stream.

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Se rial Com muni cat ion s Co ntroll ers ( SC Cs) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 20-22 F re escale Sem icondu ctor Figure 20-14. DPLL T ransmi tter Bl ock Di agram The DPLL can be dr iven by one of the baud r ate generator outputs or an exter nal clock, CLK x .

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Ser ial Comm unica tion s Contr oll ers ( SC Cs) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 20-23 The DPLL can also be us ed t o invert the data stream of a transfer . This f eature is available in al l encodings, including standard NRZ format.

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Se rial Com muni cat ion s Co ntroll ers ( SC Cs) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 20-24 F re escale Sem icondu ctor If t he DPLL is not needed, NRZ or NRZI codings can be s elected in GSM R_L [RENC, TENC]. C oding definitions are shown i n T able 20- 9 .

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Ser ial Comm unica tion s Contr oll ers ( SC Cs) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 20-25 4. If an INI T TX PARAMET ERS command was not i ssued in step 3, issue a RE STA R T TRANSM I T command.

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Se rial Com muni cat ion s Co ntroll ers ( SC Cs) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 20-26 F re escale Sem icondu ctor.

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 21-1 Chapter 2 1 SCC U ART Mode The universal asynchronous receiver transmitter ( UAR T) pr otocol is commonly used to send low-speed data between devices.

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SC C UART M od e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 21-2 F re escale Sem icondu ctor In synchronous UAR T (isochronous operation), a s eparate clock signal is explicitly pr ovided with the data.

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SC C UART M od e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 21-3 3. Address/data bit (optional) 4. Parity bit (optional) 5. Stop bits The receiver uses a clock 8 × , 16 × , or 32 × faster than the baud rate and samples each bit of the incoming data t hree times arou nd its center .

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SC C UART M od e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 21-4 F re escale Sem icondu ctor T a ble 21-1. U A RT -S pecific SCC P a rameter RAM Memo ry M ap Offset 1 Name W idth Descript ion 0 x30 — D Wo rd Reserve d 0x 38 MAX_IDL Hword Maximum idle char acter s.

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SC C UART M od e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 21-5 21.5 Data-Han dlin g Met h ods: Characte r - or Message -Based An SCC UAR T controlle.

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SC C UART M od e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 21-6 F re escale Sem icondu ctor 21.7 SC C U ART Commands The transmit comma nds in T able 21-2 are issued to the CP command regist er (CPCR) . Recei ve commands ar e desc ribed i n T able 21-3 .

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SC C UART M od e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 21-7 • Automatic multidr op mode — The contr oller checks the incoming addres s char acter and accepts subsequent data only if the addr ess matches one of two us er- defin ed values.

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SC C UART M od e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 21-8 F re escale Sem icondu ctor T able 21-4 describes the data s truc ture used in control chara cter recognition.

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SC C UART M od e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 21-9 21.10 Hunt Mode (Receiver) A UAR T receiver in hunt mode remains deactivated until a n idle or address characte r is rec ogn ized, depending on PS M R[UM].

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SC C UART M od e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 21-10 F re escale Sem icondu ctor 21.1 2 Sen ding a Break (T ran smitt er ) A break is an a ll-zeros character w ith no s top bit that is sent by iss uing a ST OP TRANS MIT command.

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SC C UART M od e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 21-11 21.15 Handling Error s in the SCC U AR T Co ntr oller The UAR T control ler reports character reception and transmission error conditions via the BDs, the error counters, and the SCCE.

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SC C UART M od e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 21-12 F re escale Sem icondu ctor 21.16 U ART Mode Registe r (PSMR) For UAR T mode, the SC C pr otocol-specific mode regi ster (PSM R ) is called the UAR T m ode regis ter .

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SC C UART M od e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 21-13 T able 21-9 desc ribes PSMR UAR T fields.

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SC C UART M od e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 21-14 F re escale Sem icondu ctor 21.1 7 SCC U ART Receive Buf fer Desc r ip tor (RxBD) The CPM uses RxBDs to report on each buf fer received.

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SC C UART M od e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 21-15 •A n EN TER HUNT MODE or CL O SE RXB D command is i ssued. • An address character is received in multidrop mode . The addres s character is written to the next buf fer for a softw a re comp arison.

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SC C UART M od e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 21-16 F re escale Sem icondu ctor Figure 21-7. SCC U ART Receiving using RxBDs Figure 21- 8 shows the SCC UAR T Rx BD.

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SC C UART M od e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 21-17 T able 21-10 describes RxB D status and contr ol fields.

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SC C UART M od e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 21-18 F re escale Sem icondu ctor Section 20.2, “SCC Buf fe r Descriptors (BDs),” describes the data length and buff er pointer f ields.

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SC C UART M od e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 21-19 The data length and buffer pointer f ields are described in Section 20.

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SC C UART M od e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 21-20 F re escale Sem icondu ctor Figure 21-10. SCC UAR T Interrup t Event Exam ple SCCE bits are cleared by writing ones; writing zeros ha s no ef fect. Unmasked bits mus t be cle ar ed before the CPM clears an internal interr upt request.

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SC C UART M od e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 21-21 21.2 0 SCC U AR T St atus Regi ster (SCCS) The SCC UAR T status register (SCCS), shown in Figure 21-12 , monitors the real-time status of R XD.

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SC C UART M od e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 21-22 F re escale Sem icondu ctor 21. 21 SCC U ART Pr o gramm in g Exam ple The fol lowing initializatio n sequence is for the 9,600 baud, 8 data bits, no parity , and stop bi t of an S C C in UAR T mode assuming a 66-MHz system frequency .

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SC C UART M od e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 21-23 18. Initialize the TxBD. As sume the buffer is at 0x0000_2000 in main memory and contains sixteen 8-bit characters.

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SC C UART M od e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 21-24 F re escale Sem icondu ctor T o recei ve S-recor ds, the cor e must wa it for an RX inter rupt, indicating that a complete S-record buffer was r eceived.

729ページ

MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 22-1 Chapter 2 2 SCC HDLC Mode High-level data link control (HDLC) is one of the most common protocol s in the data link l ayer , layer 2 of the O S I model.

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SCC HDLC Mod e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 22-2 F re escale Sem icondu ctor • Four address comparison r e gisters with mas k • Maintenance of five 16- bit erro.

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SCC HDL C Mode MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 22-3 and an address ma sk. The SCC compares the rec eived addres s field with th e user-define d values after masking wit h the address mas k.

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SCC HDLC Mod e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 22-4 F re escale Sem icondu ctor Figure 22- 2 shows 16- and 8- bit address r ecognition. Figure 22-2. HDLC Add ress Recogni ti on 22.5 Programming the SCC i n HDLC Mode HDLC mode is selected f or an SCC by writing GSMR_L[MODE] = 0 b0000.

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SCC HDL C Mode MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 22-5 address comparisons . Receive er r ors are reported through the RxB D; transmit errors are r eported through the TxBD. 22.6 SC C HDLC Com mands The transmit and receive commands are issued to the CP command regi st er (CPCR) .

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SCC HDLC Mod e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 22-6 F re escale Sem icondu ctor Reception errors are described in T able 22-5 .

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SCC HDL C Mode MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 22-7 22.8 HDLC Mode Register (P S MR) The pr otocol-spec ific mode re gister (PSMR), shown in F igur e 22-3 , functions as the HDLC mode register .

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SCC HDLC Mod e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 22-8 F re escale Sem icondu ctor 22.9 SCC HDL C Receive Buffer Descri p tor (RxBD) The CP uses the RxBD, shown in Figure 22- 4 , to report on data received for each buffer .

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SCC HDL C Mode MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 22-9 Data length and buf fer pointer fields are described in Section 20.

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SCC HDLC Mod e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 22-10 F re escale Sem icondu ctor Figure 22-5. SCC HDLC Receiving Using RxBDs Bu ffer 0 0x0008 32- Bit Buffer P o int er.

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SCC HDL C Mode MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 22-11 22.1 0 S CC HDL C T ransmit Buffe r Descriptor (TxBD) The CP uses the TxBD, shown i n Figure 22-6 , t o conf irm transmissions and indicate error conditions.

740ページ

SCC HDLC Mod e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 22-12 F re escale Sem icondu ctor The data length and buffer pointer f ields are described in Section 20.

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SCC HDL C Mode MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 22-13 Figure 22- 8 shows interrupts that can be gene ra ted using the HD LC protocol. Figure 22-8. SCC HDLC Interrupt Event Example 14 TXB T ransm it bu f f er .

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SCC HDLC Mod e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 22-14 F re escale Sem icondu ctor 22.1 2 S CC HDL C Status Regist er (SCCS) The SCC status r egister (SCCS), sh own in Fi gur e 22- 9 , per mits monitor ing of real-time status conditions on RXD.

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SCC HDL C Mode MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 22-15 3. Configure port C pin 29 to enable the CLK3 pin. Set PP ARC[29] and clear PDIRC[29] and PSORC[29]. 4. Connect CLK3 to SCC2 using the C PM mux.

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SCC HDLC Mod e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 22-16 F re escale Sem icondu ctor 25. W r i te 0x0000 to PSMR2 to configure one opening and one closing flag, 16-bit CC I TT -CRC, a nd prevent multiple fra mes in the FIFO.

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SCC HDL C Mode MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 22-17 tran smissi on continues. If the echo bit is ever 0 when the transmit bit is 1, a collision occurs between termina ls; the s tation(s) that s ent a zero s tops tran smitting.

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SCC HDLC Mod e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 22-18 F re escale Sem icondu ctor In single-master conf iguration, a master station tran smits to any slave s tation without collis ions . Slaves communicate only with the master , but can experience collisions in their access over the bus.

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SCC HDL C Mode MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 22-19 While in the a ctive condition (r eady to transmit), the HDL C bus controller m onitors the bus using C TS . It counts the one bits on CTS .

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SCC HDLC Mod e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 22-20 F re escale Sem icondu ctor Figure 22-13 . Nonsymmetrical T x Clock Duty Cyc le for Increased Perfor ma nce 22.15 .4 Delayed R TS Mode Figure 22- 14 shows local HDLC bus controllers using a standard tr ansmission line and a local bus.

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SCC HDL C Mode MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 22-21 Figure 22-15. Delayed RTS Mode 22.15 .5 Usin g th e Tim e-S lot A ssi gner (TSA ) HDLC bus controllers can be us ed with a time-division multiplexed transmission line and a local bus, a s shown in Figure 22-16 .

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SCC HDLC Mod e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 22-22 F re escale Sem icondu ctor 22.15.6 HDL C Bus Pro t ocol Pr o gra mming The HDLC bus on the PowerQUI CC II is im plemented using the SC C in HDLC mode with bus-specifi c option s selected in the PS MR and GSMR, as outlined be l o w .

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 23-1 Chapter 2 3 SCC BISYNC Mode The byte-oriented BISYNC pr otoc ol was developed by IBM for us e in ne tworking products.

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SCC BISYNC Mo de MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 23-2 F re escale Sem icondu ctor 23.1 Featur es The fol lowing list summar iz es f ea tures of the SCC in BISYNC mode:.

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SCC BISYNC Mod e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 23-3 23.3 SCC BIS YNC Channel Fr ame Recep tion Although the receiver is designed to wor k with almost no core intervention, the user can inter vene on a per- byte basis if necessar y .

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SCC BISYNC Mo de MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 23-4 F re escale Sem icondu ctor GSMR[MO DE] determines th e protocol for each SCC. The SYN1–SYN2 synchronizati on characters are programmed in the DSR (see Section 20.

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SCC BISYNC Mod e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 23-5 Recei ve commands ar e desc ribed i n T able 23-3 .

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SCC BISYNC Mo de MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 23-6 F re escale Sem icondu ctor The control character table lets the BISYNC contro l l er recognize the e nd of the current block.

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SCC BISYNC Mod e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 23-7 23.7 BISY NC SYNC Register (BSYNC) The BSYNC register , shown in Figur e 23-3 , defines BIS YNC stripping and SYNC character insertion.

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SCC BISYNC Mo de MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 23-8 F re escale Sem icondu ctor 23.8 SC C BISYNC DLE Register (BDLE) Seen in Figure 23- 4 , the BDLE register is used to define the B ISYNC stripping and inse rtion of DLE characters.

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SCC BISYNC Mod e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 23-9 23.9 Sen ding and Receivin g the Synch ron i zati on Seq uence The BI SYNC channel can be programmed to s end and receive a synchr oni zati on pattern defined in the DSR.

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SCC BISYNC Mo de MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 23-10 F re escale Sem icondu ctor T able 23-9 describes receive er ror s. 23.1 1 BI SYNC Mo de Register (PS M R) The PSMR is used as the BISYNC mode r egister , shown in F i gure 23-5 .

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SCC BISYNC Mod e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 23-11 T abl e 23- 10. PS MR Fi eld D escr i ption s Bits Name Descripti on 0–3 NOS Minimum n umber of SYN1–SYN2 pair s (defined i n DSR) sen t bet ween or bef ore messag es.

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SCC BISYNC Mo de MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 23-12 F re escale Sem icondu ctor 23 .1 2 SCC BISYNC Recei ve BD (RxBD) The CP uses BDs to report on each buf fer received.

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SCC BISYNC Mod e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 23-13 Data length and buffer pointer fields a r e desc ribed in Section 20.2, “ SCC Buffer Descriptors (BDs) .” Data length repres e nts the number of octets the CP writes into this buf f e r , including the BCS.

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SCC BISYNC Mo de MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 23-14 F re escale Sem icondu ctor 23.1 3 S CC BI S YNC T ransm it BD ( T xBD) The CP arr anges data to be se nt on an SCC cha nnel in buf fers ref er enced by the channel TxBD table.

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SCC BISYNC Mod e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 23-15 Data length and buf fer pointer fields are described in Section 20. 2, “SCC Buf fer Descriptors ( BDs).” Although it is neve r modified by the CP , data length s hould be greater than zero.

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SCC BISYNC Mo de MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 23-16 F re escale Sem icondu ctor T able 23-13 desc ribes SCCE and SCCM fields. 23.1 5 SCC Sta tus R e g ist ers (SCCS) The S CC st atus ( SCCS) r egiste r , seen in Figure 23-9 , a ll ows real-time monitoring of RXD.

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SCC BISYNC Mod e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 23-17 23.1 6 Pr ogram mi n g the SCC BISYNC Control ler Software has two ways to handle data receive d by the BISYNC controller .

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SCC BISYNC Mo de MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 23-18 F re escale Sem icondu ctor After ETX, a B CS is e xpected; t hen the buf fer should be clos ed .

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SCC BISYNC Mod e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 23-19 17. W r i te CHARACTER2–8 with 0x8000. They are not used. 18. W rite RC CM with 0xE0FF . It is not used. 19. Initialize the RxBD and a ssume the data buf fer is at 0x00001000 in main m emory .

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SCC BISYNC Mo de MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 23-20 F re escale Sem icondu ctor.

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 24-1 Chapter 2 4 SC C T ran sp ar ent Mod e T ranspar ent mode (also c all e d totally transparent or promiscuous mode) provide s a cle ar channel on which the SCC can send or receive se rial data without bit-level manipulation.

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SCC T ra nsp are nt M ode MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 24-2 F re escale Sem icondu ctor 24.2 SCC T rans pare nt Chan nel Fr ame T ransm is sion Pro cess The tr a nsparent trans mitter i s designed t o work a lmost no intervention from the core.

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SC C T ransp are nt Mo de MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 24-3 24.4 Achie ving S ynchr on ization in T ra nsparent M ode Once the SC C tran.

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SCC T ra nsp are nt M ode MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 24-4 F re escale Sem icondu ctor frame. Pulse oper ation allows an uninter rupted stream of data. However , use e nvelope mode t o identify frames of transpa r ent data.

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SC C T ransp are nt Mo de MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 24-5 24.4.1.3 T ransparent Mode w ithout Explicit Synchr onization If there is no.

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SCC T ra nsp are nt M ode MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 24-6 F re escale Sem icondu ctor 24.5 CRC Calculation in T ransparent Mode The CRC calculations follow the ITU/IEEE standar d.

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SC C T ransp are nt Mo de MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 24-7 T able 24-4 describes receive comm ands.

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SCC T ra nsp are nt M ode MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 24-8 F re escale Sem icondu ctor 24.9 T ran sparen t Mo de and the PSMR The protocol-specif ic mode register (PSMR) is not used by the trans pare nt controller because all transparent mode se lections are made in the GSMR .

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SC C T ransp are nt Mo de MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 24-9 T a bl e 24-7. SCC T ranspa rent RxBD St a tus and Contr o l Field Descriptions Bits Name Descripti on 0 E Empty . 0 The b uff er is f ull or sto pped recei vi n g data bec ause an er r or oc curred.

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SCC T ra nsp are nt M ode MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 24-10 F re escale Sem icondu ctor Data length and buffer pointer f ields are described in Section 20.

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SC C T ransp are nt Mo de MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 24-11 Data length and buf fer pointer fields are described in Section 20. 2, “SCC Buf fer Descriptors ( BDs).” Although it is neve r modified by the CP , da ta length shoul d be greater than ze ro.

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SCC T ra nsp are nt M ode MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 24-12 F re escale Sem icondu ctor 24.1 3 SCC Sta tus Regist er in T ran spar ent Mode (SCCS ) The SCC status register (SCCS) allows monitoring of real- time status conditions on the RXD line.

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SC C T ransp are nt Mo de MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 24-13 The transmit and receive clocks ar e externally provi ded to PowerQUI CC II(B) using CLK3.

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SCC T ra nsp are nt M ode MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 24-14 F re escale Sem icondu ctor NO T E After 5 bytes ar e sent, the T x buff e r is close d and after 16 bytes are rece ived the Rx buffer is closed.

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 25-1 Chapter 2 5 SCC Ethernet M ode The Ethernet I EEE 802.3 protocol is a widely used LAN pr otoc ol based on the carrier sense multiple access/collision detect (CSMA/CD) approach.

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SCC E ther net Mo de MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 25-2 F re escale Sem icondu ctor Figure 25-2. Ethernet Blo c k Diagram The Po werQUICC II Ether n et cont roller re quires an external s er ial interface adaptor (S IA) and tr ansceiver function to complete the interface to the media.

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SCC E the rnet M ode MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 25-3 — T wo nonaggressive backoff modes — Automatic fra me retra ns mis sion (unti.

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SCC E ther net Mo de MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 25-4 F re escale Sem icondu ctor 25.3 Conn ectin g the P o werQUICC II to E therne t The ba sic inte rface to the .

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SCC E the rnet M ode MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 25-5 connect to AUI or twisted-pair media are exter n al to the E EST . T he MC68160 docume nt ation describes EEST connection c ircuits.

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SCC E ther net Mo de MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 25-6 F re escale Sem icondu ctor 25.5 SC C Etherne t Channel Fra me Re ception The Ethernet r eceiver handles address recognition and p e rfor ms CRC, short f r ame, maximum DMA tran sfer , and maximum fr ame length checking with almost no cor e intervention.

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SCC E the rnet M ode MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 25-7 generate writes to the CAM for addres s recognition. In addition, the RENA signal supplied from the SIA can be used to abort the compar ison if a collision occu rs on the receive frame.

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SCC E ther net Mo de MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 25-8 F re escale Sem icondu ctor 0x 4C MINF L R Hword Minimum fr a me length reg ister . The Ethernet con trol ler check s the incomi ng frame’ s length against MINFL R (ty pi c ally 64 dec imal) .

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SCC E the rnet M ode MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 25-9 25.8 Pr ogrammi ng the Ether net Contr olle r The core configures the SCC to operate a s a n Ethernet controll e r by s etting GSMR[MODE] to 0b1 100.

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SCC E ther net Mo de MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 25-10 F re escale Sem icondu ctor T able 25-3 describes receive comm ands. NO T E After a CPM reset via CPCR[RS T], the Ethernet transmit en able (TENA) signal de faults to its R T S , active-low f unctiona lity .

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SCC E the rnet M ode MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 25-11 25.10 SCC Ethe rnet Addres s Re cognition The Ethernet controller can f ilter re.

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SCC E ther net Mo de MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 25-12 F re escale Sem icondu ctor address, addres s recognition can be perfor med on multiple gr oup addresses using the GADDR n has h table.

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SCC E the rnet M ode MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 25-13 If a collision occurs within 64 byte times, the r etry process is initiated. The tr a nsmitter waits a r andom number of slot tim e s (512 bit times or 52 µ s ).

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SCC E ther net Mo de MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 25-14 F re escale Sem icondu ctor T able 25-5 describes reception error s. 25.17 E thernet Mode Register ( PSM R) In E thernet mode, the protocol- specific mode register (PSMR ), shown in Figur e 25-5 , is used as the Ethernet mode register .

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SCC E the rnet M ode MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 25-15 T able 25-6. PSMR Field Descri ptions Bits Name Descripti on 0 HBC Hear tbeat chec king. 0 No hear t beat c hecki ng i s perf ormed.

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SCC E ther net Mo de MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 25-16 F re escale Sem icondu ctor 25.1 8 S CC Ethernet Rece ive BD The Ethernet controller uses the RxBD to report on t he received data for each buffer . T able 25-7 describes RxB D status and c ontrol fields.

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SCC E the rnet M ode MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 25-17 Data length and buffer pointer fields a r e desc ribed in Section 20.2, “ SCC Buffer Descriptors (BDs) .” Data length includes the total number of fr ame octets (including four bytes for CR C).

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SCC E ther net Mo de MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 25-18 F re escale Sem icondu ctor Figure 25-7. E therne t Rece iving using RxBDs 25.

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SCC E the rnet M ode MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 25-19 T able 25-8 desc ribes TxBD status and contr o l fi elds. 0123456 789 1 0 1 3 1 4 1 5 Of fse t + 0 RP A D W I L T C DEF HB LC RL RC UN CSL Of fse t + 2 Data Le ngth Of fse t + 4 Tx Dat a Buff er P ointer Of fse t + 6 Figure 25-8.

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SCC E ther net Mo de MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 25-20 F re escale Sem icondu ctor Data length and buf fer pointer fields are described in Section 20.

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SCC E the rnet M ode MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 25-21 Figure 25- 10 shows an example of inter r upts that ca n be generated in E thernet protocol.

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SCC E ther net Mo de MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 25-22 F re escale Sem icondu ctor 25.21 SCC E therne t Programmi ng Exa mple The following is an initialization sequence for the S CC2 in Ethernet mode. The CLK3 pin is used for the Etherne t receiver and CLK4 is used for the trans mitter .

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SCC E the rnet M ode MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 25-23 23. W rite 0x0040_0000 to the S IU interrupt mask register low (SIMR_L) so the SMC1 can generate a system interrupt. Initialize SI U interrupt pending regis ter low (SIPNR _L) by writing 0xFFFF_FF FF to it.

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SCC E ther net Mo de MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 25-24 F re escale Sem icondu ctor.

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 26-1 Chapter 2 6 SCC A ppl eT alk M ode AppleT alk is a set of pr otocols developed by Apple Computer , Inc. to provide a LAN service between Macintosh computers and printers.

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SCC AppleT alk Mode MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 26-2 F re escale Sem icondu ctor RT S pi n) is sent to request the network, a CTS f r ame is sent by the destination node, and the data frame is sent by the re questing node.

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SCC App leT alk M od e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 26-3 Figure 26-2. Connecting the P owerQUICC II to LocalT alk The 1 6 × overspeed of a 3.

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SCC AppleT alk Mode MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 26-4 F re escale Sem icondu ctor 8. Clear TINV a nd RINV so data will not be i nve rted. 9. Set TSNC to 1. 5 bit times ( 0b10). 10. Clear E DGE. Both the positive and ne gative edges are used to c hange the sample point (default).

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 27-1 Chapter 2 7 Seri al Mana gement Contr oller s (SMCs) The two serial management controllers (SMCs) are .

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Seri al Mana geme nt Cont rollers ( SMC s) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 27-2 F re escale Sem icondu ctor The receive data source can be L1RXD if t he SMC is connected to a T DM channel of an SI x , or SMRXD if it is connect e d to the NMSI.

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S erial M anag ement Contro llers (SM Cs ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 27-3 T able 27-1 desc ribes SMCMR fi elds.

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Seri al Mana geme nt Cont rollers ( SMC s) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 27-4 F re escale Sem icondu ctor 27.2.2 S MC Buff er Descr iptor Oper ation In UAR T a nd transpar ent modes, the SMC’ s memo ry structur e is l ike t he SCC’ s, except t hat SMC-associated data is stored in buffer s.

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S erial M anag ement Contro llers (SM Cs ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 27-5 Figure 27-3. SMC Memor y Structure The BD table all ow s buffers to be defined for transmission and r ec eption.

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Seri al Mana geme nt Cont rollers ( SMC s) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 27-6 F re escale Sem icondu ctor T able 27-2. S MC U ART and T r ansparen t P arameter RAM Memo ry M ap Offset 1 Name Wid t h Des cripti on 0x00 RBASE Hwo rd RxBDs and TxBDs base address .

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S erial M anag ement Contro llers (SM Cs ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 27-7 T o extract data from a partially full receive buffer , issue a CLOS E RXB D comm and. Certain parameter R AM values m ust be initialized bef ore the S MC is ena bled.

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Seri al Mana geme nt Cont rollers ( SMC s) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 27-8 F re escale Sem icondu ctor 27.2.3.1 SMC Function Code Registers (RFCR/TFCR) The func t ion c ode register s contai n the transa ction spec ification a ssociat ed with SDMA channel a ccesses to external memory .

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S erial M anag ement Contro llers (SM Cs ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 27-9 27.2.4.1 SMC T ransmitter Fu ll Sequence Follow these steps to fully enable or disable th e SMC trans mitter : 1.

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Seri al Mana geme nt Cont rollers ( SMC s) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 27-10 F re escale Sem icondu ctor 2. Issue an INIT TX AND RX PARAME TERS COMMA ND to initialize tr ansmit and receive parameters. Make any additional SMCMR changes.

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S erial M anag ement Contro llers (SM Cs ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 27-11 27.3.1 Fe at ures The following list summarizes the main f.

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Seri al Mana geme nt Cont rollers ( SMC s) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 27-12 F re escale Sem icondu ctor errors are reported via the BD s. At its simpl est, the SMC UAR T controller functions in a character -oriented environment, wher eas eac h character i s sent with the sel ected stop bit s and pari ty .

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S erial M anag ement Contro llers (SM Cs ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 27-13 number of break char acters according to BRKCR a nd then reverts to id le or sends data if a RESTART TRANSMIT is issued be fore completion.

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Seri al Mana geme nt Cont rollers ( SMC s) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 27-14 F re escale Sem icondu ctor • A program mable number of consec ut ive idle c haracters a re received Figure 27- 6 shows the format of the SMC UAR T RxBD.

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S erial M anag ement Contro llers (SM Cs ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 27-15 Data length represe nt s the number of octets the CP wr i tes into the buf fer . After data is re ceived in buf f e r , the CP only writes t hem once as the BD closes.

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Seri al Mana geme nt Cont rollers ( SMC s) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 27-16 F re escale Sem icondu ctor Figure 27-7.

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S erial M anag ement Contro llers (SM Cs ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 27-17 27.3.1 0 S MC U A R T Tx BD Data is s ent to the CP for transmission on a n SMC channel by a rranging it in buffers referenced by the channel TxBD table.

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Seri al Mana geme nt Cont rollers ( SMC s) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 27-18 F re escale Sem icondu ctor to 3. T o send three UAR T characters of 9-bit data, 1 s t.

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S erial M anag ement Contro llers (SM Cs ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 27-19 Figure 27-10.

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Seri al Mana geme nt Cont rollers ( SMC s) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 27-20 F re escale Sem icondu ctor 12. Initialize the RxBD.

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S erial M anag ement Contro llers (SM Cs ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 27-21 • Transmits and re ceives transparently on its own set o.

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Seri al Mana geme nt Cont rollers ( SMC s) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 27-22 F re escale Sem icondu ctor SMC c ontinues tr a nsferring da ta to this BD’ s buf fer . If the C M bit is set in the RxBD , the E bit is not cleared, so the CP can automatical ly overwri t e the buff er on its next access.

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S erial M anag ement Contro llers (SM Cs ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 27-23 Figu re 27- 11. Sy nchr onizat ion wi th SMSYN x If bot h SMCMR[REN] and S M CM R[TEN] are set, the fir st falling e dge of SMSYN causes both the tran smitter and receiver to achieve synchronization.

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Seri al Mana geme nt Cont rollers ( SMC s) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 27-24 F re escale Sem icondu ctor Figure 27-12 . Synchro nization wi th the TSA Once SMCMR[ RE N] is set, the first time- s lot af ter th e frame sync cause s the SMC receiver to achieve synchronization.

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S erial M anag ement Contro llers (SM Cs ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 27-25 describes how to safely disable and reenable th e SMC. S imply clear ing and setting TEN may not be enough. 27.

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Seri al Mana geme nt Cont rollers ( SMC s) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 27-26 F re escale Sem icondu ctor 27. 4. 8 SM C T ransp aren t R xBD Using BDs, the CP repor.

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S erial M anag ement Contro llers (SM Cs ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 27-27 Data length and buf fer pointer fields are described in Section 20. 2, “SCC Buf fer Descriptors ( BDs).” 27.

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Seri al Mana geme nt Cont rollers ( SMC s) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 27-28 F re escale Sem icondu ctor Data length repr e sents the number of octets the CP s hould transmit fr om this buf fer . It is never modif ied by the CP .

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S erial M anag ement Contro llers (SM Cs ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 27-29 T able 27-16 desc ribes SMCE/SMCM f ields . 27. 4. 11 SM C T ran spar ent NMS I P r ogr ammin g Exam p le The following example initializ es the SMC1 transparen t channel over its own set of signals.

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Seri al Mana geme nt Cont rollers ( SMC s) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 27-30 F re escale Sem icondu ctor 8. W rite MRBLR with the maximum bytes per receive buffer . Assuming 16 bytes MRBLR = 0x0010. 9. Initialize the RxBD assuming the buffer is at 0x0000_1000 in main memory .

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S erial M anag ement Contro llers (SM Cs ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 27-31 27.5.2 Han dlin g the GC I M onitor Chan nel The following s ections describe how the G CI monitor channel is ha ndled.

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Seri al Mana geme nt Cont rollers ( SMC s) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 27-32 F re escale Sem icondu ctor 27.5.3 Han dlin g the GC I C/I Channel The C/I c hannel is used to contro l the layer 1 device.

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S erial M anag ement Contro llers (SM Cs ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 27-33 27.5.6 S MC GCI M onitor Ch annel TxBD The CP uses this BD, shown in F i gure 27-16 , to report about the monitor channel transmit byte .

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Seri al Mana geme nt Cont rollers ( SMC s) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 27-34 F re escale Sem icondu ctor T able 27-21 describes SMC C/I channel R xBD fields. 27.5.8 S MC GCI C/ I Chann el TxBD The CP uses this BD, as seen in Figure 27-18 , t o r eport about the C/I channel transmit byte.

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S erial M anag ement Contro llers (SM Cs ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 27-35 the internal inte rrupt reque st to the SIU inter rupt controller . Figure 27-19 displays the SMCE/SMC M re gist er s.

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Seri al Mana geme nt Cont rollers ( SMC s) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 27-36 F re escale Sem icondu ctor.

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 28-1 Chapter 2 8 Multi-Cha nnel Contr oller s (MCCs) NO T E The MPC8 2 50 and the MPC8255 have only one MCC. The signalling s ystem #7 (SS7) functionality des c ribed in this c hapter i s not available on r ev A.

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Multi- Cha nnel C ontrolle rs (M CCs ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 28-2 F re escale Sem icondu ctor • Ef f icie nt c ontrol of the interrupts to the core • Uses exte rnal BD t ables.

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Multi -Cha nnel C ontrolle rs (M CCs) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 28-3 — Section 28.3.4, “C hannel-Sp e cific SS 7 Par ameters” Note that the D PRAM memory corresponding to the inactive channels can be us ed for other purposes.

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Multi- Cha nnel C ontrolle rs (M CCs ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 28-4 F re escale Sem icondu ctor 28. 2 Gl obal M CC P a ram ete r s The global M CC parameters are described in T able 28-1 . T able 28-1. Global MCC Parameter s Offset 1 Name Widt h Descript ion 0x00 MCCB ASE W ord MCC base pointe r.

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Multi -Cha nnel C ontrolle rs (M CCs) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 28-5 28.3 Chann el-Sp ecifi c P aram eter s Each FIFO in the MCC is managed by a se t of channe l-specific par ameters. The se parameters can change based upon w hat protocol is being used on that cha nnel.

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Multi- Cha nnel C ontrolle rs (M CCs ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 28-6 F re escale Sem icondu ctor T a ble 28-2. Channel-Sp ecific P aram eters for HDLC Offset 1 Name Width Descri ption 0x00 TST A TE W ord Tx internal stat e.

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Multi -Cha nnel C ontrolle rs (M CCs) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 28-7 28.3.1.1 Internal T ransmitte r State (TST A T E)—HDLC Mode In.

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Multi- Cha nnel C ontrolle rs (M CCs ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 28-8 F re escale Sem icondu ctor 28.3.1.2 Interrupt Mask (INTMSK)—HDLC Mode The interrupt m a sk (INTMSK) provides bits for enabling/dis abling the reporting of each possible event defined in the interrupt circular table entry .

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Multi -Cha nnel C ontrolle rs (M CCs) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 28-9 T abl e 28-4. CHAMR Field Descriptions Bits Name Description 0 MODE This mode bit determines whether the HDLC or tra nsparent mod e is used.

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Multi- Cha nnel C ontrolle rs (M CCs ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 28-10 F re escale Sem icondu ctor 28.3.1.4 Internal Rece iver State (RST A TE)—HDLC Mode Inter.

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Multi -Cha nnel C ontrolle rs (M CCs) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 28-11 28.3.2 Cha nne l-Spec ific T r ansp arent Par amet ers T able 28-6 describes channel-specific par a mete rs for t ransparent ope ration.

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Multi- Cha nnel C ontrolle rs (M CCs ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 28-12 F re escale Sem icondu ctor 28.3.2.1 Internal T ransmitte r State (TST A T E)—T r ansparent Mode In transparent mode, TST A TE f unctions the same as in HDL C mode.

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Multi -Cha nnel C ontrolle rs (M CCs) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 28-13 28.3.2.3 Channel Mode Register (CHAMR)—T ran sparent Mode Figure 28- 6 shows the user-initialized channe l mode register , C HAMR, for trans parent mode.

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Multi- Cha nnel C ontrolle rs (M CCs ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 28-14 F re escale Sem icondu ctor 28.3.2.4 Internal Rece iver State (RST A TE)—T ransparent Mode In transparent mode, R ST A TE f unctions the same a s in HDLC mode .

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Multi -Cha nnel C ontrolle rs (M CCs) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 28-15 28.3.3.1 Channel-Spec ific P aram eter s—AAL1 C ES The following are changes th at occur in the cha nnel-spec ific parameter RAM when us ing AAL1 CES.

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Multi- Cha nnel C ontrolle rs (M CCs ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 28-16 F re escale Sem icondu ctor The CHAMR in CE S mode fields are described in T able 28- 7 . 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 Field MO DE POL 1 1 EP RD SYNC — TS RQ N CESM UDC UTM Reset — R/W R/ W Offs et 0x1A Figure 28-8.

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Multi -Cha nnel C ontrolle rs (M CCs) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 28-17 28.3.4 Chan nel-Sp ecific SS7 Paramet ers Based on the H DLC protocol, the s i gnalling system #7 (SS7) protocol is used to manage public se rvice networks.

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Multi- Cha nnel C ontrolle rs (M CCs ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 28-18 F re escale Sem icondu ctor • Flow control SS7 features are as follows: • Up to 128 in.

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Multi -Cha nnel C ontrolle rs (M CCs) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 28-19 T able 28-10. Chan nel-Specific P a rameters f o r SS7 Offset 1 Name 2 Wid th Descript ion 0x 00 TST A TE Wor d Tx int er n al s tate .

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Multi- Cha nnel C ontrolle rs (M CCs ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 28-20 F re escale Sem icondu ctor 0x 38 MFLR H w ord Maxi mum fra me leng th regi ster . Defi nes the l ongest e xpected fr ame for t his channel .

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Multi -Cha nnel C ontrolle rs (M CCs) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 28-21 28.3.4.1 Extended Cha nnel Mode Register (ECHAMR)—SS7 Mode Th.

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Multi- Cha nnel C ontrolle rs (M CCs ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 28-22 F re escale Sem icondu ctor ECHAMR fields are described in T able 28-1 1.

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Multi -Cha nnel C ontrolle rs (M CCs) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 28-23 28.3.4.2 Signal Unit E rr or Monitor (SUERM)—SS7 Mode The microcode maintains th e signal unit error rate monitor as desc ribed in ITU-T Q.

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Multi- Cha nnel C ontrolle rs (M CCs ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 28-24 F re escale Sem icondu ctor • For every JTRDelay an error flag is checked. • If there is no error , decrement the counter SUE RM by 1 (not below zero).

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Multi -Cha nnel C ontrolle rs (M CCs) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 28-25 28.3.4.3 .1 AERM Im plemen tation The SS7 microcode implements the IT U Q.703 alignment error rate monitor (AERM).

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Multi- Cha nnel C ontrolle rs (M CCs ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 28-26 F re escale Sem icondu ctor T o disable AE RM and enter SUERM, do the f ollowing: 1. Set SUERM_D IS bit in SS7_OP T . 2. Set parameters (T , D & SUERM) for Japanese SUERM.

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Multi -Cha nnel C ontrolle rs (M CCs) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 28-27 • State 0—The first 3-5 bytes (depending on the contents of the LI fi eld) are m asked and then compared with the first 3-5 bytes of the last SU.

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Multi- Cha nnel C ontrolle rs (M CCs ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 28-28 F re escale Sem icondu ctor 28.3.4.5 Octet Counting Mode—SS7 Mode When ente ring the octet counting mode (OCM), the CP will load the user defined N register to its internal octet counter .

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Multi -Cha nnel C ontrolle rs (M CCs) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 28-29 28.5 Supe r channe ls A TDM may not be progr ammed to contiguously transmit mor e than one byte of data from the same MCC channel.

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Multi- Cha nnel C ontrolle rs (M CCs ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 28-30 F re escale Sem icondu ctor 28.5.2 Sup erchann els a nd Re cei ving The restrictions stated in Section 28.5 r egarding us ing back-to-back timeslots wi th the same channel do not apply to the re ceive side of the MCC.

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Multi -Cha nnel C ontrolle rs (M CCs) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 28-31 Figure 28-14. T ran smitter Super Cha nnel Example In this example, data is expected to be se nt on the first timeslots allocated for each superc hannel.

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Multi- Cha nnel C ontrolle rs (M CCs ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 28-32 F re escale Sem icondu ctor of the ma naging MCC channel for that superchanne l (t he same MCC channel number use d in the superchannel table entries cor r esponding to th e transmit FIFOs for that superchannel).

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Multi -Cha nnel C ontrolle rs (M CCs) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 28-33 Fi gu re 28-16.

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Multi- Cha nnel C ontrolle rs (M CCs ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 28-34 F re escale Sem icondu ctor T able 28-16 describes gr oup assignments. NO T E The TDM group channel assignments made in MCCF mus t be coherent with the SI register programming and SI RAM programming; see Section 15.

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Multi -Cha nnel C ontrolle rs (M CCs) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 28-35 28.8 MCC Except ions The MCC interrupt report ing scheme has two levels.

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Multi- Cha nnel C ontrolle rs (M CCs ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 28-36 F re escale Sem icondu ctor Event Regis ter ( MCC E)/ Mas k Regist er (MCCM) ” ) reports some global- leve l events and whether new activit y has taken place in any of that MCC’ s inter rupt tables.

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Multi -Cha nnel C ontrolle rs (M CCs) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 28-37 desired interrupt handler latency or other f actors. It is up to the user to determine an interr upt handling scheme that provides desired performance and functionality .

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Multi- Cha nnel C ontrolle rs (M CCs ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 28-38 F re escale Sem icondu ctor 28.8.1.1 Interrupt Circular T able Entr y Each interr upt circular table entr y , shown in Figure 28-20 , contains inf or mation about channel-specific events.

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Multi -Cha nnel C ontrolle rs (M CCs) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 28-39 T able 28-19. Inter rupt Cir cular T able E ntry Field Des criptions Bits Name Descri ption 0 V V alid bi t . V = 1 indi cates that t his entry contain s vali d inter rupt i nfo r mati on.

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Multi- Cha nnel C ontrolle rs (M CCs ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 28-40 F re escale Sem icondu ctor 28.8.1.2 Global T ransmitter Underrun (GUN) A global underr un (GUN) event indica tes t hat the MC C’ s transmit FIFO ar r ay experienced an underrun condition.

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Multi -Cha nnel C ontrolle rs (M CCs) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 28-41 T o avoid these cases, pad out the SIRAM programming with “ null entries ,” entries with no CPM pe ripheral specified (MCC=0 and CS EL = 0000 i n SIRAM entry) at the end of the SI RAM programming.

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Multi- Cha nnel C ontrolle rs (M CCs ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 28-42 F re escale Sem icondu ctor 28.8.1.2 .6 CPM P rior ity It is pos sible for the M CC to experience a GUN due to prioriti zation in the CPM. See Section 14.

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Multi -Cha nnel C ontrolle rs (M CCs) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 28-43 28.8.1.4 Global Over run (GO V) An MCC receiver global overrun (GOV) is the receive version of the transmit G UN.

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Multi- Cha nnel C ontrolle rs (M CCs ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 28-44 F re escale Sem icondu ctor T able 28-22.

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Multi -Cha nnel C ontrolle rs (M CCs) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 28-45 The data length and buffer pointer are described as follows: • Data length. Data length is the number of octets written by the C P into this BD’ s data buf fer .

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Multi- Cha nnel C ontrolle rs (M CCs ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 28-46 F re escale Sem icondu ctor T able 28-23 describes TxBD f ields.

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Multi -Cha nnel C ontrolle rs (M CCs) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 28-47 The data length and buffer pointer ar e described below: • Data length. The data length is the number of byt es the MCC shoul d transmit fr om this B D’ s data buf f er .

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Multi- Cha nnel C ontrolle rs (M CCs ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 28-48 F re escale Sem icondu ctor 3. Program the SI’ s SIRAM and related registers . If the user wishes to enable the TDM at this ti me , the SIRAM programming cannot yet contain MC C- related tim e slots.

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Multi -Cha nnel C ontrolle rs (M CCs) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 28-49 The following sequence m us t be followed to stop a single channel in order to change the SI without using the shadow SI: 1.

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Multi- Cha nnel C ontrolle rs (M CCs ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 28-50 F re escale Sem icondu ctor If multiple synchr onized TDMs are used (as an exa mple 8 T1 with common clock/sync) it is recomme nded to start the TDMs out of phase relative to each other , in order to s pread out C PM and bus util iza ti on.

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 29-1 Chapter 2 9 F ast Comm uni cations Con troll ers (F C Cs ) NO T E The MPC82 55 has only two FCCs—FCC1 and FCC2.

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Fast Commun icatio ns Cont rollers (FCC s) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 29-2 F re escale Sem icondu ctor A T M inter faces (U T OP IA); see Chapter 15, “Serial Inter f ac e with T ime-Slot Assig ner, ” Chapter 35, “F ast Ethernet Controller,” and Chapter 30, “A T M Controller and AAL0, AAL1, and AAL 5.

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Fast Communic ations Contr ollers (FCCs ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 29-3 Figure 29-1. FCC Bloc k Dia gram 29.2 Genera l FCC Mode Registers ( G FMR x ) Each FCC contains a general FCC mode register (GFMR x ) that defines common FCC options and selects the protocol to be r un.

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Fast Commun icatio ns Cont rollers (FCC s) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 29-4 F re escale Sem icondu ctor T able 29-2.

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Fast Communic ations Contr ollers (FCCs ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 29-5 3 TRX T ran sparent recei ver .

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Fast Commun icatio ns Cont rollers (FCC s) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 29-6 F re escale Sem icondu ctor 8 CTSS CTS sam pli n g 0 The CTS input i s assum ed to be as ynchronou s with t he data. When it is i nter n ally sync hroniz ed by the FCC , data is sent after a dela y of n o more than two serial clocks .

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Fast Communic ations Contr ollers (FCCs ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 29-7 NO T E In addition to selecting the correct mode of operation in GFMRx[MODE], the user must issue the appropriate CP c omm and and choose the correct protocol in CPCR (r efer to Section 14.

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Fast Commun icatio ns Cont rollers (FCC s) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 29-8 F re escale Sem icondu ctor 29.4 FCC Data Synchr o nization Registers (FDSR x ) Each FC.

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Fast Communic ations Contr ollers (FCCs ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 29-9 Fields in the FTODR ar e described in T able 29- 3. . 29.6 FCC Buff er Descr ipt ors Data associated with e ach FCC is stored in buffers.

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Fast Commun icatio ns Cont rollers (FCC s) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 29-10 F re escale Sem icondu ctor Figure 29-5. FCC Me mory Structure The for mat of transmit and receive BDs , shown in Fi gure 29-6 , is the same for ever y FCC mode of operation except A T M mode; s ee Section 30.

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Fast Communic ations Contr ollers (FCCs ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 29-11 The CP proces ses the TxBDs in a straightf orward fashion. Once t he transmit side of an FCC is enable d, it starts with the firs t BD in tha t FCC’ s T xB D table .

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Fast Commun icatio ns Cont rollers (FCC s) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 29-12 F re escale Sem icondu ctor • See Section 29.12, “D isabling the FCCs On-t he-Fly.” Some parameters in T able 29-4. are not described a nd are li sted only to pr ovide information for experienced users and for debugging.

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Fast Communic ations Contr ollers (FCCs ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 29-13 29 .7.1 FCC Fu ncti on Co de R egis te rs (FC R x ) The func t ion c ode register s contai n the transa ction spec ification a ssociat ed with SDMA channel a ccesses to external memory .

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Fast Commun icatio ns Cont rollers (FCC s) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 29-14 F re escale Sem icondu ctor 29.8 Interrupts fr om the FCCs Interrupt handling f or eac.

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Fast Communic ations Contr ollers (FCCs ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 29-15 no effect on bit value s. FCCE is cle ared at reset. Fiel ds of this register are protocol-dependent a nd are described in the r e spective pr otocol sections.

914ページ

Fast Commun icatio ns Cont rollers (FCC s) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 29-16 F re escale Sem icondu ctor The first R xBD’ s empt y bit must be set bef or e the INI T RX COMMA ND . However TxB Ds can have their ready bits set at any time .

915ページ

Fast Communic ations Contr ollers (FCCs ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 29-17 6. Enable FCC transmission by se tting GFMR[ENT]. 29.10.1.2 Recovery Sequence 1. Determin e which BD is t o be transmitte d next and, if necessary , modi fy BDs .

916ページ

Fast Commun icatio ns Cont rollers (FCC s) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 29-18 F re escale Sem icondu ctor Figure 29-8. Outp ut Delay fr o m RTS Asserted If C TS is not already asser ted when R TS is asserted, the dela ys to the first bit of data depend on when CTS is asser ted.

917ページ

Fast Communic ations Contr ollers (FCCs ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 29-19 Figure 29-10 . CT S Los t NO T E If GFMR[CTS S] = 1, all CTS transitions must occur while the transmit clock is low .

918ページ

Fast Commun icatio ns Cont rollers (FCC s) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 29-20 F re escale Sem icondu ctor Figur e 29- 11. Usi ng CD to Contr o l Reception If i t is pr ogrammed to envelope data, C D must remai n asserte d during frame transmission or a C D lost error occurs.

919ページ

Fast Communic ations Contr ollers (FCCs ) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 29-21 29. 12. 1 F CC T r ansmi t ter Fu ll Se qu ence For the FCC transmitter , the full disable and enable sequence is as follows.

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Fast Commun icatio ns Cont rollers (FCC s) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 29-22 F re escale Sem icondu ctor 2. Issue the INIT RX PARAME TERS command. Any additional ch anges ca n be made now . 3. Set GFMR[ENR]. 29. 12.

921ページ

MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 30-1 Chapter 3 0 A TM Contr oller a nd AAL0, AAL1, and AAL5 NO T E The functionality described in this chapter is not available on the MPC8250.

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A TM Co ntr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 30-2 F re escale Sem icondu ctor • Up to 255 ac tive VCs intern ally , and up to 64K VCs us ing external memory • TM 4 .0 C BR, VB R, UBR , UBR+ tr affic ty pes • VBR type 1 and 2 traff ic using leaky buc kets (GCRA) • TM 4.

923ページ

A TM Con tr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 30-3 – Sequence number generation – Sequence number protect.

924ページ

A TM Co ntr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 30-4 F re escale Sem icondu ctor — Performs A T MF UNI 4.

925ページ

A TM Con tr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 30-5 30.2.1 T ra nsm itter Ov erv iew Before the transmitte r is enabled, t he host must initia liz e the Powe rQUICC II and create the transmit dat a structure, described in Section 30.

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A TM Co ntr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 30-6 F re escale Sem icondu ctor For the structure d format, the transm itte r rea ds 47 or 46 bytes from the exter nal buff e r and inserts them into the AAL1 us er d ata field.

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A TM Con tr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 30-7 (UDC mode) i nclude an extra header of 1–12 bytes w i th an optional HEC octet. C ell transfers use the UT OPIA level II, c ell-level handshake.

928ページ

A TM Co ntr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 30-8 F re escale Sem icondu ctor The PowerQUICC II supports pa r tially filled cells conf ig ur ed on a per-VC basis.

929ページ

A TM Con tr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 30-9 For inf ormation about cell r ate pacing, see Section 30.3.5, “A T M T raf fic T ype.” For information about prioritiza tion, s ee Section 30.

930ページ

A TM Co ntr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 30-10 F re escale Sem icondu ctor Each 2-byte time-slot entry points to one A TM channel. Additi onal channe ls sc heduled to transmit i n the same slot ar e linked t o eac h other using the APC linke d-channel field in the T C T .

931ページ

A TM Con tr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 30-11 For the above example, 32 kbps = 155.52 M bps/(( 1216-1) × 4). Use equations (A) and ( B) to obtain the maximum a nd minim um bit rates of a s cheduling table.

932ページ

A TM Co ntr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 30-12 F re escale Sem icondu ctor 30.3.5.3 P eak and Sustain T raffic T ype (VBR) V ariable bit rate (VBR) traffic can burst a t the peak cell r ate as long a s the long- term average r ate does not exceed the s ustainable cell rate.

933ページ

A TM Con tr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 30-13 Equation D yields the number of slots the user w rites to the channe l’ s TCT[BT].

934ページ

A TM Co ntr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 30-14 F re escale Sem icondu ctor 30.4.1 E xter nal CAM L ookup An external CAM is usually used when the range of VCI/VPI values varies widely or is unknown.

935ページ

A TM Con tr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 30-15 30.4.2 Addre ss Comp ress ion The addr ess compr ession mecha nism uses two levels of addres s translation to help minimize the memory space needed to cover the available address range.

936ページ

A TM Co ntr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 30-16 F re escale Sem icondu ctor to indicate the r eceived ce l l’ s channel code. Address compr ession field descriptions are s hown in T able 30-3 .

937ページ

A TM Con tr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 30-17 The PowerQUICC II can check that all unallocated bits of the PHY + VPI are 0 by sett ing GMODE[CUAB] (c hec k una llocated bit s) i n the par ameter RAM.

938ページ

A TM Co ntr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 30-18 F re escale Sem icondu ctor Figure 30- 8 shows the VC point e r address compression from T able 30- 6 . Figure 30-8. VC Po inter Address Comp ression 30.

939ページ

A TM Con tr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 30-19 Figure 30-9.

940ページ

A TM Co ntr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 30-20 F re escale Sem icondu ctor support. The destination rece i ve s forward RM cells and r etur ns them to the source as backward RM cells.

941ページ

A TM Con tr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 30-21 7. Before sending an F-RM ce ll, if more than A DTF (AC R decreas e time factor) has elapsed s ince sending the last F-RM cell, AC R is reduced to ICR.

942ページ

A TM Co ntr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 30-22 F re escale Sem icondu ctor Figure 30-11.

943ページ

A TM Con tr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 30-23 Figure 30-12.

944ページ

A TM Co ntr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 30-24 F re escale Sem icondu ctor Figure 30-13.

945ページ

A TM Con tr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 30-25 Figure 30-14. ABR Receiv e Flo w 30.5.2 RM Cell Structu re T able 30-7 describes the s tructure of the RM cell supported by the PowerQUICC II.

946ページ

A TM Co ntr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 30-26 F re escale Sem icondu ctor 30.5.2.1 RM Cell Rate Representation Rates in the RM cell.

947ページ

A TM Con tr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 30-27 30.5.3 ABR Flow Control Setup Follow thes e steps t o setup ABR flow control: 1. Initialize the ABR data structure : RCT , TCT , RCT -ABR protocol-s pe c ific, TCT E-ABR protocol-specific.

948ページ

A TM Co ntr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 30-28 F re escale Sem icondu ctor 30.6.2 Vir tual P ath ( F4) Flow Me c h anis m The F4 fl ow is designated by pr e-assigned virtual cha nnel identif iers within the virtual path.

949ページ

A TM Con tr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 30-29 insert it in an AAL 0 T xBD.

950ページ

A TM Co ntr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 30-30 F re escale Sem icondu ctor 30.6.6.1 Running a Perf ormance B lock T est For bidir e ctional P M blo ck tests, FMC s are monitored a t the r eceive side a nd generated at the transmit s ide.

951ページ

A TM Con tr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 30-31 Before the BRC is transferred to the transmit raw cell queue, the PM function type should be changed to backward re porting and additional che cking should be done r egarding the BLER field.

952ページ

A TM Co ntr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 30-32 F re escale Sem icondu ctor 30.6.6.4 BRC P e rformance Calculations BRC r eception uses the regular AAL 0 raw c ell queue.

953ページ

A TM Con tr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 30-33 30. 8 A TM Layer S tat i sti cs A TM layer s tatistics c an be us ed to iden tify pr oblems, such as the line-bit e rror ra te, tha t af fect the UNI performance.

954ページ

A TM Co ntr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 30-34 F re escale Sem icondu ctor Figure 30 -21. A T M-to-TDM Interworking When going from TDM to A T M, the MCC r eceiver routes data from the TDM line to a specific BD table.

955ページ

A TM Con tr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 30-35 30.9.3 Timi ng Is sues Use of the TDM interface assumes that all communi cating entities are synchronized (that is, that they are using a synchronized s erial clock).

956ページ

A TM Co ntr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 30-36 F re escale Sem icondu ctor The MCC and A TM controller should be synchronized with the framer ’ s multi-frame block boundary .

957ページ

A TM Con tr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 30-37 0x44 UDC_TMP_BAS E Hwo rd UDC mode onl y . P oint s to a total of 64 b ytes reserved dua l-por t RAM area used b y the CP .

958ページ

A TM Co ntr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 30-38 F re escale Sem icondu ctor 0x78 VPT1_BASE / EXT_CAM1_BASE W ord Base addr ess of the address compres sion VP1 t abl e/ EX T CAM1. User- defined.

959ページ

A TM Con tr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 30-39 30.10.1.1 Determining UEAD_OFFSET (UE AD Mode Only) The UEAD_OFFSET value is based on the position of t he user-defined extended addr ess (UEAD) in the UD C e xtr a h ead er .

960ページ

A TM Co ntr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 30-40 F re escale Sem icondu ctor 30.10.1.3 Global Mode Entry (G MODE) Figure 30- 23 shows the layout of the global mode entry (GMODE) . T able 30-14 describes GMODE f ields.

961ページ

A TM Con tr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 30-41 30. 10.2 C o nnect ion T ab les (R CT , TCT , an d TCTE ) The receive and transmit connection ta bles, RCT and TCT , store host-initialized connec tion parameters after connection set-up.

962ページ

A TM Co ntr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 30-42 F re escale Sem icondu ctor a VC whe n sending a ATM TR ANSMIT command, initiatin g the exte r nal CAM or address compressi on tables, and when the CP sends an interrupt to an interrupt queue.

963ページ

A TM Con tr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 30-43 T able 30-16 describes R CT fields.

964ページ

A TM Co ntr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 30-44 F re escale Sem icondu ctor T able 30-16. RCT F ield Descriptions Offset Bits Name Descr i pt ion 0x00 0–1 — Reserved, shoul d be cleared.

965ページ

A TM Con tr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 30-45 30.10.2 .2.1 AAL 5 Pro tocol- S p ecific RCT Figure 30- 26 shows the AAL5 protocol-s pecif ic area of an RCT entry .

966ページ

A TM Co ntr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 30-46 F re escale Sem icondu ctor T able 30-17 describes AAL5 protocol s pecific RCT f i elds. 30.10.2.2.2 AAL5-ABR Proto col-Specific RCT Figure 30- 27 shows the AAL5-ABR protocol-specific area of a n RCT entr y .

967ページ

A TM Con tr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 30-47 T able 30-18 describes AAL5-ABR pr otocol-speci fic RCT fields. 30.10.2 .2.3 AAL 1 Pro tocol- S p ecific RCT Figure 30- 28 shows the AAL1 protocol-s pecif ic area of an RCT entry .

968ページ

A TM Co ntr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 30-48 F re escale Sem icondu ctor T able 30-19. AAL1 Protoc ol-Sp eci fic RCT Field Descriptions Offset Bits Name Description 0x0E 0–7 — Reser v ed, s hould be clear ed.

969ページ

A TM Con tr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 30-49 30.10.2 .2.4 AAL 0 Pro tocol- S p ecific RCT Figure 30- 29 shows the layout for the AAL0 pr otocol-specific RCT .

970ページ

A TM Co ntr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 30-50 F re escale Sem icondu ctor 30.10.2 .2.5 AAL 1 CES Pro tocol -Speci fic RCT Re fe r to Section 31.9.1.1, “AAL1 CES Pr otocol- Specif ic RCT.

971ページ

A TM Con tr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 30-51 T able 30-21 describes general T CT fields.

972ページ

A TM Co ntr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 30-52 F re escale Sem icondu ctor.

973ページ

A TM Con tr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 30-53 T able 30-21. TCT Field Descri ptions Offset Bits Name Descrip tion 0x00 0–1 — Res er v ed, should be clear ed.

974ページ

A TM Co ntr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 30-54 F re escale Sem icondu ctor 0x02 0 — Inte r nal use only . Shoul d be clea r ed. 1 INF U sed for AA L5 On ly . In dica tes the tran smitt er st ate.

975ページ

A TM Con tr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 30-55 30.10.2 .3.1 AAL 5 Pro toc ol-Sp ecif ic TCT Figure 30- 31 shows the AAL5 proto col-specif ic TCT . T able 30-22 describes AAL5 protocol-specific T CT fields.

976ページ

A TM Co ntr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 30-56 F re escale Sem icondu ctor T able 30-23 describes AAL1 protocol-specific T CT fields.

977ページ

A TM Con tr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 30-57 30.10.2 .3.3 AAL 0 Pro toc ol-Sp ecif ic TCT Figure 30- 33 shows the AAL0 proto col-specif ic TCT . T able 30-24 describes AAL0 protocol-specific T CT fields.

978ページ

A TM Co ntr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 30-58 F re escale Sem icondu ctor T able 30-25 describes VBR protocol-specific T CTE fields. 30.10.2.3.7 UBR+ Protocol - Speci fic TCTE Figure 30- 35 shows the UBR+ protocol-specific T CTE.

979ページ

A TM Con tr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 30-59 T able 30-26 describes UB R+ protocol-specific TCTE fields. 30.10.2.3.8 ABR Protoco l-Specific TCTE Figure 30- 36 shows the ABR protocol-specific T CTE.

980ページ

A TM Co ntr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 30-60 F re escale Sem icondu ctor T able 30-27 describes ABR-specifi c TCTE fie l ds.

981ページ

A TM Con tr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 30-61 3 NI-T A No increase– tu rn-arou nd cell.

982ページ

A TM Co ntr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 30-62 F re escale Sem icondu ctor 30. 10.3 O AM P er f orma nce M onit oring T able s The OAM performance monitoring tables include performance monitor ing block test pa ra meters, as shown in Figure 30-37 .

983ページ

A TM Con tr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 30-63 30. 10. 4 AP C D at a S truct ure The AP C data structur e consist s of three e lements: the APC pa rameter ta bles for the PHY devices, the APC priority table, a n d the APC s cheduling tables.

984ページ

A TM Co ntr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 30-64 F re escale Sem icondu ctor Figure 30-38.

985ページ

A TM Con tr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 30-65 30.10.4.2 APC Priority T able Each PHY’ s APC prior ity table holds pointers to the APC scheduling table of each priority level.

986ページ

A TM Co ntr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 30-66 F re escale Sem icondu ctor T able 30-31 describes contr ol slot fields. 30.10.5 A TM Co ntr o ller Buffer Des criptors (BDs) Each A TM cha nnel has separat e receive a nd transmit BD tables .

987ページ

A TM Con tr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 30-67 Figure 30-41.

988ページ

A TM Co ntr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 30-68 F re escale Sem icondu ctor Figure 30-42. Receive Static Buffer Al location Exam ple 30.10.5 .2.2 Global Buf fer Allo cation The user prepare s a table of BDs without assigning buf f e rs to them (no buffer pointers).

989ページ

A TM Con tr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 30-69 Fi gu re 30-43.

990ページ

A TM Co ntr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 30-70 F re escale Sem icondu ctor T able 30-32 describes f ree buffer pool entry fields.

991ページ

A TM Con tr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 30-71 30.10.5.3 A TM Controller Buffers T able 30-34 describes properties of the A TM receive and transmit buffers.

992ページ

A TM Co ntr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 30-72 F re escale Sem icondu ctor T able 30-35 describes AAL5 RxBD fields . m T able 30-35. AAL5 RxBD F ield Descriptions Offset Bit s Name Des cr ipti on 0x00 0 E Empty .

993ページ

A TM Con tr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 30-73 30.10.5.5 AAL1 RxBD Figure 30- 47 shows the AAL1 RxBD. T able 30-36 describes AAL1 RxBD fields . 0x02 — DL Data l ength.

994ページ

A TM Co ntr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 30-74 F re escale Sem icondu ctor 30.10.5.6 AAL0 RxBD Figure 30- 48 shows the AAL0 RxBD. T able 30-37 describes AAL0 RxBD fields . T able 30-36.

995ページ

A TM Con tr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 30-75 30.10.5.7 AAL1 CES RxBD Re fe r to Section 31.12.1, “AAL 1 CES RxBD.” 30.10.5.8 AAL2 RxBD Re fe r to Section 32.

996ページ

A TM Co ntr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 30-76 F re escale Sem icondu ctor 30.10.5.9 AAL5, AAL1 CES User-Defined Cell—RxBD Extensi on In user-defined ce l l mode, the AAL5 and AAL 1 CES RxB Ds are extended to 32 byte s; see F igure 30-49 .

997ページ

A TM Con tr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 30-77 30.10.5.

998ページ

A TM Co ntr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 30-78 F re escale Sem icondu ctor T able 30-39 describes AAL1 TxBD fields.

999ページ

A TM Con tr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 30-79 T able 30-40 describes AAL0 TxBD fields.

1000ページ

A TM Co ntr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 30-80 F re escale Sem icondu ctor 30.10.5.

1001ページ

A TM Con tr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 30-81 30.10 .7 UNI S tat istics T able The UNI statistics table, shown in T able 30- 41 , resides in the dual-port RAM and holds U NI statist ics parameters.

1002ページ

A TM Co ntr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 30-82 F re escale Sem icondu ctor the queue. I f th e CP tr ie s t o overwrite a va lid entry (V = 1), an overflow condition occ urs and the queue’ s ove rflo w f lag, FCCE [INT O x ], is set.

1003ページ

A TM Con tr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 30-83 30. 11. 3 Int erru pt Queue P arame ter T able s The inte rrupt que ue parameters are held in parameter table s in the dual-port RAM ; see T able 30-43 .

1004ページ

A TM Co ntr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 30-84 F re escale Sem icondu ctor 30 .1 2 The UT OPIA Int e rface The A TM controller interfaces with a P HY device through the U T OPI A interface.

1005ページ

A TM Con tr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 30-85 30.12.1.1 UT OPIA Master M ultiple PHY Operation The PowerQUICC II supports two polling modes : • Direct polling uses CL A V[3–0] with PHY selection using ADD[1–0].

1006ページ

A TM Co ntr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 30-86 F re escale Sem icondu ctor 30.12 .2 UT O PIA Inte rfac e Slave Mod e In UT OPIA slave mode (single or multiple PHY), ce lls are transferre d using cell-le ve l and octet-leve l handshakes as defined by t he UTOPI A level-2 s tandard.

1007ページ

A TM Con tr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 30-87 30.12.2.1 UT OPIA Slave Multiple PHY O peration The user should write the A TM controller PHY address in FPSMR[PHY ID].

1008ページ

A TM Co ntr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 30-88 F re escale Sem icondu ctor 30. 13. 1 Gen eral FCC Mo de Regi ster ( GFMR ) The GFMR mode field s houl d be programmed for A TM mode.

1009ページ

A TM Con tr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 30-89 8 ICD I dle ce lls di sca rd 0 Di sca rd idle cells (GFC,.

1010ページ

A TM Co ntr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 30-90 F re escale Sem icondu ctor 30. 13. 3 A TM Ev ent Re gist er (FCCE) /Ma sk R egis ter ( FCC M) The FCCE registe r is the A TM controller event register when the FCC operates in A TM m ode.

1011ページ

A TM Con tr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 30-91 T able 30-48 desc ribes FCCE fields.

1012ページ

A TM Co ntr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 30-92 F re escale Sem icondu ctor The first four PHY device s (address 00– 03) on FCC1 and FCC 2 have their own tran smit inter na l rate re g is te r s (FT IR R x _PHY0–FTIRR x _PHY3) f or use in tra nsmit internal rate mode.

1013ページ

A TM Con tr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 30-93 Example: Suppose the PowerQUICC II is connecte d to four 155 Mbps PHY devices and the maximum tra nsmis sion rate is 155 M bps for the f irst PHY and 10 Mbps for the rest of the PHYs.

1014ページ

A TM Co ntr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 30-94 F re escale Sem icondu ctor 30.15 SR T S Generation and Clock Re co ve ry Using External Logic The PowerQUICC II supports SR TS generation using e xternal logic.

1015ページ

A TM Con tr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 30-95 samples a new S R TS and stores it internally . The SR T S is a s ample of a 4-bit counter with a 2. 43- MHz reference clock (for E1/T1) synchronized with the network c lock.

1016ページ

A TM Co ntr o ller and AAL0, AAL1, and AAL5 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 30-96 F re escale Sem icondu ctor For example, suppose a system uses a 155.52-Mbps OC-3 device as PHY0, but the maximum required data rate is only 100 Mbps.

1017ページ

MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 31-1 Chapter 3 1 A TM AAL1 Cir cuit Em ulation Serv i ce NO T E The functionality described in this chapter is not available on the M PC8250 nor on . 29 µ m (HiP 3) rev A.

1018ページ

A TM AAL 1 Ci r cuit Emulatio n Ser vic e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 31-2 F re escale Sem icondu ctor – Segment PDU directly f r om external me mory – Partial.

1019ページ

A TM AA L1 C ir cui t Em ula ti on S ervi ce MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 31-3 31.2 AAL1 CES T r a n s mitter Over vie w The PowerQUICC I I supports both structured and unstructur ed AAL1 cell f or mats.

1020ページ

A TM AAL 1 Ci r cuit Emulatio n Ser vic e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 31-4 F re escale Sem icondu ctor Section 31.4.6, “C hannel Associated S ignaling (CAS) Support .” The signaling information that resides in the internal R AM is inserted into the AAL1 c ell according to the a f-vtoa-0078 specification.

1021ページ

A TM AA L1 C ir cui t Em ula ti on S ervi ce MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 31-5 received octet bec om es the first byte of the ne w BD (new super frame). (See Section 31.5, “A TM-to-TDM Adaptive Slip Control,” and Section 31.

1022ページ

A TM AAL 1 Ci r cuit Emulatio n Ser vic e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 31-6 F re escale Sem icondu ctor Figure 31-4. AAL1 CES Re cei ver Data flow 31.4 Interworking Functio ns The PowerQUICC II supports the i nterworking of A TM and TDM.

1023ページ

A TM AA L1 C ir cui t Em ula ti on S ervi ce MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 31-7 A T M receiver, set RCT[INVE] of the AAL1 CES-specifi c ar eas of the receive connection table; se e Section 31.

1024ページ

A TM AAL 1 Ci r cuit Emulatio n Ser vic e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 31-8 F re escale Sem icondu ctor In order to pr event an overrun condition on the MCC rece iver , the A TM transmitter should be programmed to work at a faster rate than the MCC s uper channel.

1025ページ

A TM AA L1 C ir cui t Em ula ti on S ervi ce MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 31-9 and CESAC reaches the A TM_Start threshold, the receiver .

1026ページ

A TM AAL 1 Ci r cuit Emulatio n Ser vic e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 31-10 F re escale Sem icondu ctor 31.4.5 T run k Con dition According to the Bellcore standar.

1027ページ

A TM AA L1 C ir cui t Em ula ti on S ervi ce MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 31-11 Fig ure 31- 8. Inter nal CA S Block F orm ats 31.4.7 Ma ppin g VC S ignalin g to CAS Blocks Each A TM channel is connected to a specific C AS block.

1028ページ

A TM AAL 1 Ci r cuit Emulatio n Ser vic e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 31-12 F re escale Sem icondu ctor Figur e 31- 9. Mapp ing C AS Entr y 31.4.7.1 CAS Routing T able Figure 31- 10 shows the structure of a CAS routing table.

1029ページ

A TM AA L1 C ir cui t Em ula ti on S ervi ce MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 31-13 T able 31-1 desc ribes CAS r outing table entry fields.

1030ページ

A TM AAL 1 Ci r cuit Emulatio n Ser vic e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 31-14 F re escale Sem icondu ctor The user may use external logic to convert the fram er super- frame SYNC to tr igger the M CC .

1031ページ

A TM AA L1 C ir cui t Em ula ti on S ervi ce MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 31-15 the external framer . E ach byte in the CAS block c o ntains one nibble of valid CAS information (depicted in Figur e 31-8 ).

1032ページ

A TM AAL 1 Ci r cuit Emulatio n Ser vic e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 31-16 F re escale Sem icondu ctor Mode.” In the example s hown in Figure 31-14 , the MCC is programmed to send the curr ent B D during the pre-underrun condition.

1033ページ

A TM AA L1 C ir cui t Em ula ti on S ervi ce MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 31-17 T able 31-2 describes CE S adaptive threshold table f ields.

1034ページ

A TM AAL 1 Ci r cuit Emulatio n Ser vic e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 31-18 F re escale Sem icondu ctor Figure 31-16 . P re-Und errun Seque nce BD 1 BD 2 BD 3 BD 4 BD 5 MCC Tx po i nt er 0 0 0 0 0 AT M - t o - T D M Step 1: Ini tiali ze the MCC and A TM pointer s to t he sam e B D t able.

1035ページ

A TM AA L1 C ir cui t Em ula ti on S ervi ce MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 31-19 Figure 31-17. Pre-Overr un Sequenc e BD 1 BD 2 BD 3 BD 4 BD 5 MCC Tx po i nt er 0 0 0 0 0 AT M - t o - T D M Step 1: Ini tiali ze the MCC and A TM pointer s to t he sam e B D t able.

1036ページ

A TM AAL 1 Ci r cuit Emulatio n Ser vic e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 31-20 F re escale Sem icondu ctor 31.6 3-Step -SN Al go r ithm The 3-s tep-SN algorithm is a fast a nd eff icie nt sta te mach ine that has the ability to recover one lost or misinse rted cell.

1037ページ

A TM AA L1 C ir cui t Em ula ti on S ervi ce MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 31-21 Figure 31-19.

1038ページ

A TM AAL 1 Ci r cuit Emulatio n Ser vic e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 31-22 F re escale Sem icondu ctor Figure 3 1-20.

1039ページ

A TM AA L1 C ir cui t Em ula ti on S ervi ce MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 31-23 0x44 UDC_TMP_BASE Hword UDC mode only . P oint s to a total of 32 byt es r es er v ed d ual-por t RAM area used b y the CP .

1040ページ

A TM AAL 1 Ci r cuit Emulatio n Ser vic e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 31-24 F re escale Sem icondu ctor 0x82 VCI_Fi ltering Hword VCI fil tering enabl e bits . W hen ce lls wit h VCI = 3, 4, 6, 7-15 are r ece iv ed and the assoc i a t ed VCI_Fi ltering bi t = 1 the cell is sent to t he raw cel l queue.

1041ページ

A TM AA L1 C ir cui t Em ula ti on S ervi ce MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 31-25 Additional CES parame ters needed by the AAL 1 mic rocode are des cribed in the f oll owing table.

1042ページ

A TM AAL 1 Ci r cuit Emulatio n Ser vic e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 31-26 F re escale Sem icondu ctor between transmit and r e ceive connecti on tables of the same channel is the CR T (CAS routing ta bl e); see Section 31.

1043ページ

A TM AA L1 C ir cui t Em ula ti on S ervi ce MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 31-27 T a ble 31- 5. RC T F ield Des cript ions Offset Bits Name Description 0x00 0–1 — Reserved , shou l d be clear ed during in iti aliza t i on.

1044ページ

A TM AAL 1 Ci r cuit Emulatio n Ser vic e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 31-28 F re escale Sem icondu ctor 31.9.1.1 AAL1 CES Protocol-Specific RCT Figure 31- 22 shows the AAL1 CES protocol-specific area of an RCT e ntry .

1045ページ

A TM AA L1 C ir cui t Em ula ti on S ervi ce MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 31-29 T able 31-6 describes AAL 1 CES protocol-specific RCT fields. Offset + 0x16 Bl o ck Siz e — SN Offset + 0x18 Super Channel Number RXBM SL IPIM — CASBS T able 31-6.

1046ページ

A TM AAL 1 Ci r cuit Emulatio n Ser vic e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 31-30 F re escale Sem icondu ctor 0x12 0 SPV Struct ured p ointer val i d . Shoul d be user-i niti ali z ed user to ze r o . Structure d f ormat only .

1047ページ

A TM AA L1 C ir cui t Em ula ti on S ervi ce MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 31-31 31.9.2 T ra nsmit Conne ctio n T a ble (TCT) Figure 31- 23 shows the format of an TCT entry . T able 31-7 desc ribes general TCT fields.

1048ページ

A TM AAL 1 Ci r cuit Emulatio n Ser vic e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 31-32 F re escale Sem icondu ctor T able 31-7. TCT F ield Descr i ptions Offset Bit s Name Descr iptio n 0x00 0–1 — Reserved, should b e clea red duri ng ini tial izat ion.

1049ページ

A TM AA L1 C ir cui t Em ula ti on S ervi ce MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 31-33 0x02 0-12 — Reserv ed, shoul d be c leared dur i ng i nitializ ation.

1050ページ

A TM AAL 1 Ci r cuit Emulatio n Ser vic e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 31-34 F re escale Sem icondu ctor 31.9.2.1 AAL1 CES Protocol-Specific TCT Figure 31- 24 shows the AAL1 CES protocol-specific tr ansmission connection tables ( TCT).

1051ページ

A TM AA L1 C ir cui t Em ula ti on S ervi ce MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 31-35 31 .1 0 O ut goi ng C AS Sta tu s R e gis te r ( O CAS SR) Figure 31- 25 shows the layout of the outgoing CA S block status regi ster (OCASSR).

1052ページ

A TM AAL 1 Ci r cuit Emulatio n Ser vic e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 31-36 F re escale Sem icondu ctor 31.1 1 Buf f er De scriptor s The AAL1 CES controller opera.

1053ページ

A TM AA L1 C ir cui t Em ula ti on S ervi ce MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 31-37 Figure 31-26. T ransmi t Buffers and BD T able Exampl e 31.11 .2 Rec eive B uffe r Op eration The user pr epare s a table of BDs pointing to the rece ive buf fe rs.

1054ページ

A TM AAL 1 Ci r cuit Emulatio n Ser vic e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 31-38 F re escale Sem icondu ctor Figure 31-27 . Receive Buffer s and BD T abl e Examp le 31.1 2 A TM Contr oller Buff ers T able 31-10 describes properties of the A TM receive and transmit buffers.

1055ページ

A TM AA L1 C ir cui t Em ula ti on S ervi ce MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 31-39 T able 31-1 1 describes AAL1 CES RxBD f ields.

1056ページ

A TM AAL 1 Ci r cuit Emulatio n Ser vic e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 31-40 F re escale Sem icondu ctor 31.12.2 AAL 1 CES TxBDs Figure 31- 29 sho ws the AAL 1 CES TxBD. T able 31-12 describes AAL 1 CES TxBD f ields.

1057ページ

A TM AA L1 C ir cui t Em ula ti on S ervi ce MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 31-41 31 .1 3 A AL1 C ES Exc eptio ns There are four circular interrupt queues available for each channel. The interrupt queue number is programmed in RCT[INTQ] and TCT[INTQ].

1058ページ

A TM AAL 1 Ci r cuit Emulatio n Ser vic e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 31-42 F re escale Sem icondu ctor 31.1 4 AAL1 Sequ ence Number (SN) Pro tect ion T a bl e The.

1059ページ

A TM AA L1 C ir cui t Em ula ti on S ervi ce MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 31-43 31.1 5 I nter nal AAL1 CES Stat ist i c s T ab les An AAL1 CES statistics table, shown in T able 31-14 , resides in the dual-port RAM a nd holds AAL 1 CES statistics on a per -VC basis.

1060ページ

A TM AAL 1 Ci r cuit Emulatio n Ser vic e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 31-44 F re escale Sem icondu ctor 31.1 6 E xtern al AAL1 CES Sta tis tic s T abl es An AAL1 CES statis tics table, shown in T a ble 31-15 , resides in the external memory and holds AAL1 CES statistics on a per -VC basis.

1061ページ

A TM AA L1 C ir cui t Em ula ti on S ervi ce MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 31-45 The external f ramer then places the signaling info rmation at the appropriate pos ition in the s uper frame.

1062ページ

A TM AAL 1 Ci r cuit Emulatio n Ser vic e MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 31-46 F re escale Sem icondu ctor.

1063ページ

MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 32-1 Chapter 3 2 A T M AAL2 NO T E The functionality described in this chapter is not available on the M PC8250 nor on r ev A.1 .29 µ m (HiP3) silicon. Refe r to www .

1064ページ

A TM AAL 2 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 32-2 F re escale Sem icondu ctor AAL2 is s ubdivided into two sublayers, as shown in F igure 32-2 : • Common pa rt sublaye.

1065ページ

A T M AAL2 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 32-3 Figur e 32 -3. AAL2 Swit c h ing Example 32.2 Featur es The PowerQUICC II’ s AAL2 features are as f ollows: • Fully complies with IT U-T I.

1066ページ

A TM AAL 2 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 32-4 F re escale Sem icondu ctor — A separate queue for every VP | V C | CID or a common queue for multiple VP | VC | CID .

1067ページ

A T M AAL2 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 32-5 32.3 AAL2 T ransmi tter The fol lowing sections de scribe the AAL2 trans mitter . 32.3.1 T ra nsm itter Ov erv iew A tran smitter cycle starts whe n the APC schedules an A TM channel number for transm ission.

1068ページ

A TM AAL 2 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 32-6 F re escale Sem icondu ctor • Round r obin (TCT[Fix]=0) • Fi xed priority (TCT[ Fix]=1) The following s ections describe the pri ority options . 32.3.2.1 Round Robin P riority In round robin priority mode, the Tx queues all have equal prior i ty .

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A T M AAL2 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 32-7 Figure 32-5. F ixed Priority Mode The TCT[OneP] determines the num be r of packets that the transmitter attempts to ta ke from each queue (see the expla nation in round r obin mode).

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A TM AAL 2 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 32-8 F re escale Sem icondu ctor 32.3.4 No S TF Mode The no-STF ( no start of frame) m ode enables the transmission of 48- byt e packets by not including the STF byte in the C PS PDU.

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A T M AAL2 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 32-9 32.3.5.1 AAL2 Protocol-Specific TCT The transmit connection table (TCT) is a VC -level ta ble and is where the AAL type for the A T M channel number is selected.

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A TM AAL 2 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 32-10 F re escale Sem icondu ctor ..

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A T M AAL2 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 32-11 T abl e 32-1. AAL2 Protocol-Specific T ra nsmit Conn ecti on T able (TCT) Field Desc riptions Offset Bits Name 1 Descri ption 0x00 0–1 — Rese r ved , should be clear ed dur i ng initia lization.

1074ページ

A TM AAL 2 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 32-12 F re escale Sem icondu ctor 0x02 0-11 — Reserved, shou ld be cleared during in i t ializat ion. 12 NoSTF No STF byte . See Section 32. 3.4, “N o STF Mode .” 0 Nor mal AAL2 cell structur e.

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A T M AAL2 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 32-13 32.3.5.2 CPS Tx Queu e Descriptor Each C PS TxBD table is ma naged by a C PS T x queue descriptor (TxQD), as shown in Figure 32-7 . The TxQD contains the address of the next BD to be s er viced, and other queue-specifi c parameters.

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A TM AAL 2 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 32-14 F re escale Sem icondu ctor T able 32-2 describes the CPS TxQD fields.

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A T M AAL2 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 32-15 32.3.5.3 CPS Buffer Structure The CPS buffer structure consis ts of a B D table t hat points to data buffers. The BDs contain, apart f r om the buffer pointer, also t he packe t header .

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A TM AAL 2 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 32-16 F re escale Sem icondu ctor T able 32-3 describes the CPS TxBD fields. . 0 1 2 3 4 7 8 15 Offset + 0x00 R CM W I — CPS P acket Head er Offset + 0x02 CPS Packet Header Offset + 0x04 Tx Data Buffe r P o i nter (T XD BPT R) Offset + 0x06 Figure 32-9.

1079ページ

A T M AAL2 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 32-17 32.3.5.4 SSSAR Tx Qu eue Descriptor A SSSAR TxB D table and its associate d buff e rs are collective ly c all ed an SSSAR TX Que ue. Eac h SSSAR TX Queue is managed by an SSSAR TxQD, as shown in Figure 32-1 1 .

1080ページ

A TM AAL 2 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 32-18 F re escale Sem icondu ctor . T able 32-4. SSSAR TxQD Field Descri ptions Offset Bits Name 1 1 Boldfac e d entries mus t be i n i t iali zed b y the user . Descript ion 0x00 0 -7 — Re ser v ed, shoul d be clea r ed during i niti aliz ation .

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A T M AAL2 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 32-19 32.3.5.5 SSSAR T ransmit Bu ff er Descriptor The SSS AR buf fer structure consists of a BD table that points to data buf f ers. The buf f ers may contain SSSAR SDUs belonging to different CIDs.

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A TM AAL 2 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 32-20 F re escale Sem icondu ctor 32.4 AAL2 Receiver The following sections descri be the AAL2 receiver . 32.4.1 Rec eiver Ov er view The re ceiver cycle star ts after t he FCC r ecei ves a cell .

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A T M AAL2 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 32-21 The receiver issues an interrupt for ea ch of the above errors.

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A TM AAL 2 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 32-22 F re escale Sem icondu ctor • RxQD off s ets fr om 8 thr ough 51 1 point int o the inter na l RxQD table located in dual- port RAM at RxQD_Base_Int. Note t hat the first 32 bytes of the int e rnal RxQD table a re reserved (so of fsets 0–7 are reserved).

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A T M AAL2 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 32-23 Figure 32-14 . AAL 2 Switching A partial packet dis card mode is provided f or th e AAL2 s witched channels that perform end- t o-end SSSAR.

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A TM AAL 2 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 32-24 F re escale Sem icondu ctor 32.4.4.1 AAL2 Protocol-Specific RCT The receive connection table (RCT) is a VC-level ta ble and is w here the AAL type for the A T M channel number is selected.

1087ページ

A T M AAL2 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 32-25 T able 32-6. A AL2 Pro tocol-S pecific RCT Field Descriptio ns Offset Bit s Name 1 Descr iption 0x00 0–1 — Reserved, should be cleare d during i nitiali zation.

1088ページ

A TM AAL 2 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 32-26 F re escale Sem icondu ctor 0x04 — — Reserved, s hould be cleare d durin g initial ization.

1089ページ

A T M AAL2 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 32-27 32.4.4.2 CID Mapping T ables and RxQ Ds Each PHY | VP | VC | C ID combination is assigned an RxQD using a CID mapping table.

1090ページ

A TM AAL 2 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 32-28 F re escale Sem icondu ctor 32.4.4.4 CPS Receive Buff er Descriptor (RxBD) The CPS RxBD structure consists of a BD table that points to data buf fer s. The RxBDs contain, apart from the buffer pointer , the packet header , as shown in Figure 32- 17 .

1091ページ

A T M AAL2 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 32-29 . 32.4.4.5 CPS Switch Rx Queue Descriptor The switch R xQD, shown in Fi gure 32-18 , is us ed for CIDs that a re being switched from one PHY 1 |V P 1 |V C 1 |C I D 1 to another PHY 2 |V P 2 |V C 2 |C I D 2 .

1092ページ

A TM AAL 2 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 32-30 F re escale Sem icondu ctor T able 32-9 describes the CPS switch RxQD fields. 32.4.4.6 SWITCH Rece ive/T ransmit Buffer Descriptor (Rx BD) The switch buf fer structure consists of a B D table that poi nts to data buffers.

1093ページ

A T M AAL2 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 32-31 32.4.4.7 SSSAR Rx Qu eue Descriptor The SSS AR RxQD, as shown in Figure 32-20 , point s to the R xBD t able and contains other par ameter s specific to the SSSAR sublayer .

1094ページ

A TM AAL 2 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 32-32 F re escale Sem icondu ctor T able 32-1 1 desc ribes the SSSAR RxQD fields.

1095ページ

A T M AAL2 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 32-33 32.4.4.8 SSSAR Rece ive Buff er Descriptor The S SSAR SDU is store d in a B D-buffer stru cture si m ilar t o the stru ctures used f or AAL5 f rames.

1096ページ

A TM AAL 2 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 32-34 F re escale Sem icondu ctor T able 32-12. SSSAR R xBD Field Descriptions Offset Bits Name 1 1 Boldf aced entries must be initial ized by the user .

1097ページ

A T M AAL2 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 32-35 32.5 AAL2 Par ameter RAM When configured for A TM mode, the FCC parameter RAM is mappe d as shown in T able 32-13 . The table includes both the fields for general A TM operation and also the fields s pecific to AAL2 operation.

1098ページ

A TM AAL 2 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 32-36 F re escale Sem icondu ctor 0x62 APCP_BASE Hword APC paramet ers tabl e base address . User-def ined. 0x64 FBT_BASE Hword F ree bu f f er pool paramet ers tabl e base . User-def i n ed.

1099ページ

A T M AAL2 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 32-37 0xA4 EP A YLO AD Word Reserved p ayload. Init ializ e to 0x6A6 A6A6A. 0xA8 T r m Wor d ( ABR only) The uppe r bound on the tim e between F- R M cell s for an acti v e sou rce.

1100ページ

A TM AAL 2 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 32-38 F re escale Sem icondu ctor 32. 6 U ser-De fin ed Cells in AA L2 The user - def ined cell (UDC) mode f or A T M as described in Section 30. 7, “User-Defined Cells (UDC), ” also applies to AA L2 oper ation.

1101ページ

A T M AAL2 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 32-39 T able 32-14 describes the interrupt queue entry fields for a CID. An interrupt entry for the VC is s hown in Figure 32-24 . . T able 32-15 desc ribes the interrupt queue en try fields f or the VC.

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A TM AAL 2 MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 32-40 F re escale Sem icondu ctor T able 3 2-15. AAL2 I nterrupt Q ueue En t r y CID = 0 Field Descriptions Offset Bits Name Descriptio n 0x00 0 V V al id inte rrupt entry 0 This interrupt queue entry is free and can be used by the CP .

1103ページ

MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 33-1 Chapter 3 3 In ver se Multiple xing f o r A TM (IMA ) NO T E The functionalit y described in this chapter is a vailable only on the MPC8264 and the MPC 8266.

1104ページ

Inverse M ultiplex ing fo r A TM ( IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 33-2 F re escale Sem icondu ctor I The PowerQUICC II’ s IMA microcode alone does not imp lement all of t hese functions.

1105ページ

Inverse M ultiplex ing f or A TM (IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 33-3 — Discards ce l ls with bad HECs (available on .

1106ページ

Inverse M ultiplex ing fo r A TM ( IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 33-4 F re escale Sem icondu ctor (2) can be programmed not to screen out HEC-errorred cells. Most PHYs have thi s mode available for IM A a lso . 33.

1107ページ

Inverse M ultiplex ing f or A TM (IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 33-5 Figure 33-1. Ba si c Co ncept of IMA In the trans mit dir ec t .

1108ページ

Inverse M ultiplex ing fo r A TM ( IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 33-6 F re escale Sem icondu ctor F igu r e 33 -2 . Il lu str ati on o f I MA Fr a me s At the tr a nsmitt ing end, the cells are transmitted con tinuously .

1109ページ

Inverse M ultiplex ing f or A TM (IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 33-7 33.2.3 Ov erv ie w o f IMA Ce lls An IMA f rame consists of M number of cells (M = 32, 64, 128, or 256 c ells). Each frame c onsists of A TM data cells and I MA control cells.

1110ページ

Inverse M ultiplex ing fo r A TM ( IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 33-8 F re escale Sem icondu ctor AT M RX Functi on Ce ll 1 Ce ll 2 Ce ll 3 Cell 4 Cell n IMA R .

1111ページ

Inverse M ultiplex ing f or A TM (IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 33-9 AT M RX Functi on Ce ll 1 Ce ll 2 Ce ll 3 Cell 4 Cell n IMA R X.

1112ページ

Inverse M ultiplex ing fo r A TM ( IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 33-10 F re escale Sem icondu ctor Figur e 33 -4. IMA Fra me and ICP Cell Formats The IMA pr otocol must c ompensate for pot e ntial dif fe rence s in delay between the diff erent links of the IMA group.

1113ページ

Inverse M ultiplex ing f or A TM (IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 33-11 33.3.1.1 User Plane F unctions P erf ormed by Micr ocod e • A TM cell str eam splitting and reconstruction • ICP cell insertion/ removal • Cell r ate decoupling ( i.

1114ページ

Inverse M ultiplex ing fo r A TM ( IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 33-12 F re escale Sem icondu ctor Figure 33-5.

1115ページ

Inverse M ultiplex ing f or A TM (IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 33-13 At startup, the non-TRL links will transmit filler cells until their transmit queues have reached a minimum depth.

1116ページ

Inverse M ultiplex ing fo r A TM ( IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 33-14 F re escale Sem icondu ctor At group start-up, instead of accessing its trans mit queue, the link will s end filler cells. This is to allow the transmit queues to reach their tar ge t steady-st ate depth.

1117ページ

Inverse M ultiplex ing f or A TM (IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 33-15 Figur e 33-8.

1118ページ

Inverse M ultiplex ing fo r A TM ( IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 33-16 F re escale Sem icondu ctor Figure 33-9.

1119ページ

Inverse M ultiplex ing f or A TM (IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 33-17 2. The non-TRL ta sks do not determine when to perform stuffing on the non-TRL links.

1120ページ

Inverse M ultiplex ing fo r A TM ( IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 33-18 F re escale Sem icondu ctor received cells (and other event indications) are used by the softwar e to initi alize IMA links and groups, and to manage transitions between link and group st ates.

1121ページ

Inverse M ultiplex ing f or A TM (IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 33-19 Cell Re cepti on Ta sk - E ac h I M A Lin k fo llo ws a Fo ur .

1122ページ

Inverse M ultiplex ing fo r A TM ( IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 33-20 F re escale Sem icondu ctor.

1123ページ

Inverse M ultiplex ing f or A TM (IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 33-21 Figure 33-11.

1124ページ

Inverse M ultiplex ing fo r A TM ( IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 33-22 F re escale Sem icondu ctor The st ates are describe d as f ollows: • Group Unassigned—T his corresponds to a link which is known to be IMA, but for which no information is known (e.

1125ページ

Inverse M ultiplex ing f or A TM (IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 33-23 • The system is only capable of car rying services that either do not require CDV control (e.g. some data ser vices), or where the CDV is handled in so me other wa y (e.

1126ページ

Inverse M ultiplex ing fo r A TM ( IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 33-24 F re escale Sem icondu ctor available in its delay compensation buf f ers, then the gr oup is determined to ha ve stalled and a n error interrupt is provided to software.

1127ページ

Inverse M ultiplex ing f or A TM (IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 33-25 Figure 33-12.

1128ページ

Inverse M ultiplex ing fo r A TM ( IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 33-26 F re escale Sem icondu ctor 33.4.2 IM A FCC P r o grammin g 33.4.2.1 FCC Registers 33.4.2.1 .1 FPSMRx The FCC protocol-specific mode r egister (FPSMR) f or A TM operation is described in Section 30.

1129ページ

Inverse M ultiplex ing f or A TM (IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 33-27 NO T E IMAROOT must be programmed to a 128- byte aligned address terminating with 0x80 ( i. e. 0xnn80). 33.4.3 IM A Root T able T a ble 33- 3.

1130ページ

Inverse M ultiplex ing fo r A TM ( IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 33-28 F re escale Sem icondu ctor 0x3C TXPHYEN W ord T rans m it PHY enabl e. Bit arra y addresse d b y PHY address ( e.g. bit 0 corr esponds to PHY 0).

1131ページ

Inverse M ultiplex ing f or A TM (IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 33-29 33.4.3.1 IMA Control (IMA CNTL) The fields o f the IMACNTL are shown in Figure 33-13 . T able 33-4 desc ribes the IMACNTL bit f ields.

1132ページ

Inverse M ultiplex ing fo r A TM ( IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 33-30 F re escale Sem icondu ctor 33.4.4.1 IMA Group T ransmit T able Entr y T able 33-5. IMA Gr oup T r ansmit T able Entry 1 Offset Nam e Width Descr ipti on 0x00 I GTCNTL Byte IMA group tran smit control parameters .

1133ページ

Inverse M ultiplex ing f or A TM (IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 33-31 33.4.4.1 .1 IMA Gr oup T ransmi t Contr o l ( IGTCNTL) The fields of the IG T CNT L regi ster are shown in Figure 33-14 .

1134ページ

Inverse M ultiplex ing fo r A TM ( IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 33-32 F re escale Sem icondu ctor T able 33-7 desc ribes the IG TST A T E bit fields.

1135ページ

Inverse M ultiplex ing f or A TM (IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 33-33 33.4.4.1 .4 ICP Cell T emplates The ICP ce ll te mplates ar e a reas of me mory provid e d by software to the microc ode f or construction of ICP cells for tr a nsmis sion.

1136ページ

Inverse M ultiplex ing fo r A TM ( IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 33-34 F re escale Sem icondu ctor 0x08 GR OUP ST A TUS AND CONTRO L Byte Bits 7-4: Group State .

1137ページ

Inverse M ultiplex ing f or A TM (IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 33-35 0x18 LI NK 11 INFO Byt e Status a nd control of lin k wit h L .

1138ページ

Inverse M ultiplex ing fo r A TM ( IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 33-36 F re escale Sem icondu ctor 33.4.4.2 IMA Group Receive T able Entry T able 33-10. IMA Group Receive T abl e Entry 1 Offset Name Width Descr ipti on 0x00 I G RCNTL Byte IMA g roup r eceiv e co ntrol p aramete rs.

1139ページ

Inverse M ultiplex ing f or A TM (IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 33-37 0x16 TRLR Hwor d TRL ra t e . Us ed only when IDCR-re gulated cell pr oc es si ng is u sed (i.e. IGRCTNL[I DCR]=1).

1140ページ

Inverse M ultiplex ing fo r A TM ( IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 33-38 F re escale Sem icondu ctor 33.4.4.2 .1 IMA Gr oup Receive Co n tr ol (IGRCNTL) The fields o f the IGRCNTL register are shown in Figure 33-17 .

1141ページ

Inverse M ultiplex ing f or A TM (IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 33-39 33.4.4.2 .2 IM A Gro up Receive S tate (IGR ST A TE) The fields of the IGRST A T E regist er are shown in Figur e 33-18 .

1142ページ

Inverse M ultiplex ing fo r A TM ( IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 33-40 F re escale Sem icondu ctor T able 33-13 desc ribes the I RGFS bit fields.

1143ページ

Inverse M ultiplex ing f or A TM (IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 33-41 33.4.5 IM A Link T abl es The IMA li nk tables cons ist of multiple IMA group structures indexed by the PHY address of their corresponding PHYs.

1144ページ

Inverse M ultiplex ing fo r A TM ( IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 33-42 F re escale Sem icondu ctor 33.4.5.1 .1 IMA Lin k T r an smit Co ntr ol (IL TCNTL) The fields o f the IL TCNTL register are shown in Figure 33-21 .

1145ページ

Inverse M ultiplex ing f or A TM (IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 33-43 33.4.5.1 .2 IM A Link T ransmit S t at e (I L TST A TE) The fields of the IL TST A T E register are shown in Figure 33-22 T able 33-17 describes the IL TS T A TE bit fields.

1146ページ

Inverse M ultiplex ing fo r A TM ( IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 33-44 F re escale Sem icondu ctor T able 33-18 desc ribes the ITI NTST A T bit f ields. 33.4.5.2 IMA Link Rec eive T able Entry T able 33-18. ITINTST A T Field Descriptions Bits Name Description 0- 3 — Rese r v ed , init ialize to z ero.

1147ページ

Inverse M ultiplex ing f or A TM (IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 33-45 0x07 DFC Byte Number of frames t o discard on a t his l ink unti l it i s caught up wit h the other links in t his group (long propa gation del a y).

1148ページ

Inverse M ultiplex ing fo r A TM ( IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 33-46 F re escale Sem icondu ctor 33.4.5.2 .1 IMA Lin k Receive Co n tr ol (ILRCNTL) The fields of the ILRCNT L regist er are shown in Figur e 33-24 T able 33-20 describes the ILRCNTL bit fields.

1149ページ

Inverse M ultiplex ing f or A TM (IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 33-47 33.4.5.2 .2 IMA Lin k Rece ive Sta te (ILRST A TE) The fiel ds of the ILR S T A TE r egister are shown in Figure 33-25 T able 33-21 desc ribes the ILRST A TE bit f i e lds.

1150ページ

Inverse M ultiplex ing fo r A TM ( IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 33-48 F re escale Sem icondu ctor 33.4.5.3 IMA Link Rec eive Statistics T able The IMA li nk receive st atistics table is optional. It is e nabled globally f or this FCC via IMACN TL[IRSE].

1151ページ

Inverse M ultiplex ing f or A TM (IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 33-49 33.4.6.2 Delay Compensation Buffers (DCB) Cells received on a link are initially stored in a delay compensation buf f e r (DCB).

1152ページ

Inverse M ultiplex ing fo r A TM ( IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 33-50 F re escale Sem icondu ctor IMA events sent to t his queue incl ude only those desc ribed in this secti o n.

1153ページ

Inverse M ultiplex ing f or A TM (IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 33-51 33.4.7.2 ICP Cell Rec eption Exceptions ICP cell s are received as AAL 0 in the channel defined in RICPC H. Rece ive inter rupts are provided for this channel if enabled in its associat ed RCT .

1154ページ

Inverse M ultiplex ing fo r A TM ( IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 33-52 F re escale Sem icondu ctor 33.4.8 IDCR Time r Pr og ramming Programming of the ID CR timer data s tr uctures is opti onal. It is only required if any of the IMA groups use IDCR-r egulated cell processing.

1155ページ

Inverse M ultiplex ing f or A TM (IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 33-53 33.4.8.2 .2 Pr ogram m in g the FCC P aramete r Shadow All of the user -defined or user-initialized FCC parameters of the FCC should be copied from th e FCC paramete r pa ge to the sh adow page.

1156ページ

Inverse M ultiplex ing fo r A TM ( IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 33-54 F re escale Sem icondu ctor 33.4.8.3 IDCR_Init Com mand The IDCR_Init co mmand is a host co mmand issued to the CPCR ( refer to Section 14.4.

1157ページ

Inverse M ultiplex ing f or A TM (IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 33-55 33.4.8.6 IDCR Counter A lgorithm The IDCR count of each enabled IDC R timer is dec rem ented eac h tick of the IDCR master clock.

1158ページ

Inverse M ultiplex ing fo r A TM ( IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 33-56 F re escale Sem icondu ctor 33.4.9 AP C Pr o gram ming for IM A Dynamically adding and dr opping links from a gr oup ch anges the overall bandwidth of the group.

1159ページ

Inverse M ultiplex ing f or A TM (IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 33-57 Per the above explanation and examples, it is seen that TNUMLINKS is the only pa r ameter which needs to be modif ied by soft war e when a link is added or dropped f rom a n IMA group.

1160ページ

Inverse M ultiplex ing fo r A TM ( IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 33-58 F re escale Sem icondu ctor 33.4.1 0 C hangin g IMA V ersion A new CPC R command has been added to the IMA microcode to cha nge the IMA ve rsion on-the-fly without s oftware intervention.

1161ページ

Inverse M ultiplex ing f or A TM (IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 33-59 Figure 33-32. I MA Microcode/Softw are I nteracti on 33.5.2 Initia lizatio n Procedu re 1. Program FCC registers/parameters for A TM operation with UTOPIA multi-PHY (excluding APC para me te rs fo r IM A PHYs ).

1162ページ

Inverse M ultiplex ing fo r A TM ( IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 33-60 F re escale Sem icondu ctor 33.5.3.2 General Ope ration • React to received ICP ce lls.

1163ページ

Inverse M ultiplex ing f or A TM (IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 33-61 33.5.3.6 T ransmit Group State Machine Control • Define the .

1164ページ

Inverse M ultiplex ing fo r A TM ( IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 33-62 F re escale Sem icondu ctor 33.5.3.11 T est P attern Control • Initiate transmit test p.

1165ページ

Inverse M ultiplex ing f or A TM (IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 33-63 of ICP ce l ls requires that the corresponding PHYs (i .e., links) have been enabled and the corresponding connection table entry/entr ies initialized (see RXPHYEN, I M APHYEN , and RICPH).

1166ページ

Inverse M ultiplex ing fo r A TM ( IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 33-64 F re escale Sem icondu ctor • Set IGRST A TE[GD SS ] to 1 (on e ) to enab le GDS. Once group delay s ynchronization is achieved, a “GDS” ex c eption is generated.

1167ページ

Inverse M ultiplex ing f or A TM (IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 33-65 Figure 33-33 . Near -En d ver s us F ar-End 33.5.4.3 .2 As Respo n der (RX) The IMA GS M/LSM software will receive ICP cells in the ICP buf f er conveying the state of the FE ’ s group and l inks .

1168ページ

Inverse M ultiplex ing fo r A TM ( IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 33-66 F re escale Sem icondu ctor 2. Assign corresponding gr oup number for t he new link: IL RCNTL[IGNUM] = x. 3. Assign channel number for ICP ce l l reception: R IC PCH = x.

1169ページ

Inverse M ultiplex ing f or A TM (IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 33-67 5. Program the Link’ s ID (LID ) in the IMA Link T r an smit T able E ntry (IL T TE): IL ID = x. 6. Program the ICP offset (IL TTE): LICPOS = x.

1170ページ

Inverse M ultiplex ing fo r A TM ( IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 33-68 F re escale Sem icondu ctor 8. Inhibit reception of cells over droppe d li nk in the IMA Root T a ble: RXPHYEN &= ~x ( i.e., clear the corresponding lin k bit in the R XPHYEN entry).

1171ページ

Inverse M ultiplex ing f or A TM (IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 33-69 5. Indicate that the link should be dr opped: ILRCNTL[RXSC] = 2. 6. Software should wait ( poll) for the PowerQUI C C II to remove t he link from t he DCB routine.

1172ページ

Inverse M ultiplex ing fo r A TM ( IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 33-70 F re escale Sem icondu ctor 33.5.4.9 T ransmit Event Re sponse Pr ocedures The following T X events may take place when operating in IMA mode.

1173ページ

Inverse M ultiplex ing f or A TM (IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 33-71 4. GDS (Group Delay Synchronized)—Group de la y synchronized ac hi eved or group de lay synchronized not achieved.

1174ページ

Inverse M ultiplex ing fo r A TM ( IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 33-72 F re escale Sem icondu ctor 33.5.4.11 T est P atter n Pr ocedure T e st patterns ar e used verify “connectivity” of a link in a par ticular group.

1175ページ

Inverse M ultiplex ing f or A TM (IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 33-73 for the f irst link encountered in w hich a change (SCC I) is detected, it may or may not be the link under test.

1176ページ

Inverse M ultiplex ing fo r A TM ( IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 33-74 F re escale Sem icondu ctor 9. Program to appr opriate rate and enab le tim e r if using a BRG (refer to Chapter 17, “Baud-Rate Gen e ra tors (BRGs)” ): TMRx, TRRx, and TGCRx.

1177ページ

Inverse M ultiplex ing f or A TM (IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 33-75 33.5.4.1 3.2 Receive No special f acility is included for reception of the e nd-to-e nd channel.

1178ページ

Inverse M ultiplex ing fo r A TM ( IMA) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 33-76 F re escale Sem icondu ctor.

1179ページ

MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 34-1 Chapter 3 4 A TM T rans mission C o n ver gence La ye r NO T E The functionalit y described in this chapter is a vailable only on the MPC8264 and the MPC 8266.

1180ページ

A TM Transm is sio n Co n verg en ce L ayer MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 34-2 F re escale Sem icondu ctor — Protocol-specific over head bits may be discar ded or routed to other controllers by the SI — Performing A TM TC layer functions (according to ITU-T I .

1181ページ

A TM T ra nsmi ssio n Con v er g e nce La yer MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 34-3 • Cell counters fo r performance monitoring: — 16-bi.

1182ページ

A TM Transm is sio n Co n verg en ce L ayer MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 34-4 F re escale Sem icondu ctor Figure 34-2. TC Layer Bl ock Diagram 34.2.1 Receiv e A T M Cell Fun ctions The A TM receive cell functions block ( RCF) perform s th e receive functions of the TC block.

1183ページ

A TM T ra nsmi ssio n Con v er g e nce La yer MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 34-5 SYNCH state, the TC is assumed to be synchronize d so that ot her funct ions can be applied to the received cell.

1184ページ

A TM Transm is sio n Co n verg en ce L ayer MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 34-6 F re escale Sem icondu ctor Figure 34-4 . HEC: Receiver M odes of Operation The R C F can als o perf orm idle/unassigned c e ll filter ing.

1185ページ

A TM T ra nsmi ssio n Con v er g e nce La yer MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 34-7 The FI FO management in c ludes e mptying cells fr om th.

1186ページ

A TM Transm is sio n Co n verg en ce L ayer MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 34-8 F re escale Sem icondu ctor T able 34-2 describes TCMODE f ields. 0 1 234567 89 1 0 1 1 1 2 1 3 1 4 1 5 Field RXEN TXEN RPS TPS RC TC SBC CF URE LB TBA IMA S M CM Reset 0000_ 0000_0000_0 000 R/W R/ W Figure 34-5.

1187ページ

A TM T ra nsmi ssio n Con v er g e nce La yer MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 34-9 34.4.1.

1188ページ

A TM Transm is sio n Co n verg en ce L ayer MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 34-10 F re escale Sem icondu ctor 34.4.1.3 TC Layer Event Register [1–8] (TCERx) The TC laye r event regis t ers (TCERx), as shown in Fi gure 34-7 , records error e vents for e ach TC block.

1189ページ

A TM T ra nsmi ssio n Con v er g e nce La yer MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 34-11 34.4.1.4 TC Layer Mask Register (TCMRx) This registe r ’ s f ield des cription is identical to that of T C ER (re fer to Section 34.

1190ページ

A TM Transm is sio n Co n verg en ce L ayer MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 34-12 F re escale Sem icondu ctor T able 34-6 desc ribes TCGSR f ields.

1191ページ

A TM T ra nsmi ssio n Con v er g e nce La yer MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 34-13 34.4.3.6 Filtered Cell Counter [1–8] (TC_FCC x ) This cell counter is updated whe never an idle/unassigned cell is filtered (discarded).

1192ページ

A TM Transm is sio n Co n verg en ce L ayer MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 34-14 F re escale Sem icondu ctor The TC layer request s A T M cells for tra nsmis sion via the inter nal UT OPIA interfac e. Then, when the A TM cell is passed to the TC layer transm it block, it is stored in the TC layer tra nsmit FI FO.

1193ページ

A TM T ra nsmi ssio n Con v er g e nce La yer MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 34-15 Figure 34-11. T C Opera t ion in FCC I nternal Rate M ode (Sub Rate Mod e) Operation in byte-aligned mode ( TCMODE[xTBA] = 1) is required for T1/E1 mainly .

1194ページ

A TM Transm is sio n Co n verg en ce L ayer MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 34-16 F re escale Sem icondu ctor Figure 34-12. Examp le of Serial A T M Application 34.5.1 Oper atin g the T C Layer at High er Fre quencie s The operation of the T C layer re quires a mini mum fre quency ratio of 1:2.

1195ページ

A TM T ra nsmi ssio n Con v er g e nce La yer MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 34-17 6. Progra m the Seri a l Inte r face (SI) 7. Enable TDM Ste p 1 T o setup and initializ e FCC2, progr a m the FPSM R and GFM R as shown in T able 14.

1196ページ

A TM Transm is sio n Co n verg en ce L ayer MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 34-18 F re escale Sem icondu ctor Ste p 6 Program the SI to r etri eve the data bits (192 bits ) out of the T1 frame ( 193 bits). The SI f r ame pattern is programmed in the SI R AM (Rx or Tx), as s hown in T able 18.

1197ページ

MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 35-1 Chapter 3 5 F ast Etherne t Contr oller The E the rnet I E EE 802.3 protoc ol is a wide ly-used L AN based on the carrier- s ense multipl e access/collision detect (CSMA/CD) approach.

1198ページ

Fast Eth ernet Contro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 35-2 F re escale Sem icondu ctor 10-Mbps Ethernet basic ti ming spec ifications follow: • T ransmits at 0.8 µ s per byte • The pre amble plus start f rame delimit e r is sent i n 6.

1199ページ

Fast Eth erne t Contro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 35-3 • Performs framing functions — Preamble generation and s tripping — .

1200ページ

Fast Eth ernet Contro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 35-4 F re escale Sem icondu ctor — Busy (out of buffers) • Error counters — Discarded frames (out of b.

1201ページ

Fast Eth erne t Contro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 35-5 The PowerQUICC II ha s additional signals for interfac ing with an optional external content-addressable memory ( CAM), which are described in Section 35.

1202ページ

Fast Eth ernet Contro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 35-6 F re escale Sem icondu ctor or for er ror situat ions.

1203ページ

Fast Eth erne t Contro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 35-7 35.6 Flow Contr ol Because collisions cannot occur in full-duplex mode, Fas t Ethernet can operate at the maximum rate.

1204ページ

Fast Eth ernet Contro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 35-8 F re escale Sem icondu ctor When an external C AM is us e d for addres s filtering, users ca n choose to either discard r ejected frames (FPSMR[ECM ] = 0) or receive rejected frames and si gnal the C AM miss i n the RxB D (FPSMR[ECM] = 1).

1205ページ

Fast Eth erne t Contro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 35-9 0x 68 TFCST A T Hword Out-of -sequenc e TxBD . Includ es the stat us/con trol, data leng t h, and buff er poin t er fields i n the same f ormat as a regular TxBD .

1206ページ

Fast Eth ernet Contro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 35-10 F re escale Sem icondu ctor 0xB4 CF_RANG E Hword Cont r ol fr ame range. Int er nal usage 0xB 6 MA X_B H word Max imu m BD by te co un t. In ter n al u sag e 0x B8 MAXD1 Hword Max DMA1 leng t h r egister (typi ca lly 1520 decimal) .

1207ページ

Fast Eth erne t Contro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 35-11 35.9 Pr ogramm ing Mode l The core conf igur es an FCC to operate as an Ethernet controller us ing GFMR [MODE].

1208ページ

Fast Eth ernet Contro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 35-12 F re escale Sem icondu ctor NO T E Before resett ing the CPM, configur e TX_EN (R TS ) to be an input. T r ans mit commands that a pply to Ether net are described in T able 35-3 .

1209ページ

Fast Eth erne t Contro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 35-13 If an address from the hash table m us t be deleted, the Ethernet channel.

1210ページ

Fast Eth ernet Contro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 35-14 F re escale Sem icondu ctor 35.1 2 Eth erne t Ad dres s Re cogniti on The Ethernet contr oller can fil.

1211ページ

Fast Eth erne t Contro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 35-15 Check Addres s I/ G Address Indi vidual Addr Matc h? I G Broadc ast Addr .

1212ページ

Fast Eth ernet Contro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 35-16 F re escale Sem icondu ctor Figu re 3 5-4. Ethern et A ddres s Re cog nition Flow char t In the physic.

1213ページ

Fast Eth erne t Contro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 35-17 small fra ction of fr ames from reaching memory . In such instances, an exter na l CAM is advised if the extra bus use cannot b e tolerated.

1214ページ

Fast Eth ernet Contro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 35-18 F re escale Sem icondu ctor T ransmission errors are described in T able 35 -6 .

1215ページ

Fast Eth erne t Contro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 35-19 T able 35-8 desc ribes FPSMR f i elds .

1216ページ

Fast Eth ernet Contro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 35-20 F re escale Sem icondu ctor 35.18 .2 Eth erne t Ev ent R eg ister (FC CE)/ Ma sk Reg ist er ( FCCM ) The FCC E, shown in Figur e 35-6 , is used as the E thernet eve nt r egister whe n the FCC functions as an Ethernet contr oller .

1217ページ

Fast Eth erne t Contro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 35-21 T able 35-9 describes FCCE/FCCM fields.

1218ページ

Fast Eth ernet Contro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 35-22 F re escale Sem icondu ctor Figure 35-7. Ethernet Interrupt E vents Example NO T E The FCC status regis ter is not valid f or the Ethernet pr otocol. The curr ent state of the M II signals can be read through the para llel ports.

1219ページ

Fast Eth erne t Contro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 35-23 T able 35-10 describes Eth erne t RxBD fields.

1220ページ

Fast Eth ernet Contro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 35-24 F re escale Sem icondu ctor Data l e ngth is the number of octets the CP writ e s i nto this BD data buf fer . It is writte n by the CP as the buf fer is closed.

1221ページ

Fast Eth erne t Contro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 35-25 Figure 35-9. Ethernet Receivi ng Using RxB Ds 35.2 0 Eth ernet T xBDs Data is sent to the Ethernet c ontroller for tran smission on an FCC channel by a r ranging it in buffers referenced by the channel’ s TxBD table.

1222ページ

Fast Eth ernet Contro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 35-26 F re escale Sem icondu ctor T able 35-1 1 desc ribes Ethernet TxBD fields.

1223ページ

Fast Eth erne t Contro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 35-27 Data length is the num ber of oct ets the Ethernet cont roller should tr a ns mit fr om this BD da ta buf fer . This value should be gr eater than zero.

1224ページ

Fast Eth ernet Contro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 35-28 F re escale Sem icondu ctor.

1225ページ

MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 36-1 Chapter 3 6 FCC HDLC Contr oller Layer 2 of the seven-layer OSI model is the data link layer (DLL), in which HDLC is one of the most common protocols. The f raming structure of HDLC is shown in Figure 36-1 .

1226ページ

FCC HDLC Controller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 36-2 F re escale Sem icondu ctor • Four address comparison r e gisters with mas ks • Maintenance of four 16-bit.

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FCC HDLC Co ntr o ll er MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 36-3 36.3 HDLC Chann el Fr ame Recep tion Pr ocessi n g The HDLC receiver is de signed to work with almo s t no core i nter vention and can perform address recognition, CRC checking, and maximum frame length checking.

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FCC HDLC Controller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 36-4 F re escale Sem icondu ctor Figure 36- 2 shows an example of using HMASK and HAD DR[ 1–4].

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FCC HDLC Co ntr o ll er MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 36-5 Figu re 36- 2. HD LC A ddres s R ecogn ition Ex am ple 36.5 Pr ogramm ing Mode l The core configures each FCC to operate in the protocol spec i fied in GFMR[MODE ].

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FCC HDLC Controller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 36-6 F re escale Sem icondu ctor T able 36-3 describes the receive c om mands that apply to the HD L C controller .

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FCC HDLC Co ntr o ll er MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 36-7 36.6 HDLC Mode Register (FP S MR) When an FCC is configured f or HDLC mode, the FPSMR is used a s the HDL C mode register , show n in Figure 36- 3 .

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FCC HDLC Controller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 36-8 F re escale Sem icondu ctor The FPS MR fields are described in T able 36-6 .

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FCC HDLC Co ntr o ll er MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 36-9 36.7 HDLC Receive Buf fer Desc riptor (RxBD) The HDLC controller uses the RxBD to report on data received for each buf f er . Figur e 36- 4 shows an example of the RxBD process.

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FCC HDLC Controller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 36-10 F re escale Sem icondu ctor Figure 36-4. F CC HDLC Receiving Usi ng RxBD s Bu ffer 0 0x0020 32-Bi t Buff er P.

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FCC HDLC Co ntr o ll er MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 36-11 Figure 36- 5 shows the FCC HDLC RxBD.

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FCC HDLC Controller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 36-12 F re escale Sem icondu ctor The RxB D status bits are written by the HDLC c ont roller after r eceiving the as sociated data buf f er .

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FCC HDLC Co ntr o ll er MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 36-13 The TxBD s tatus bits are written by the HDL C controller after s ending the associated data buffer .

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FCC HDLC Controller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 36-14 F re escale Sem icondu ctor 36.9 HDLC Event Regis ter (FCCE) /Mask Registe r (FCCM) The F CCE is used as the HDLC event r egister w hen the FCC oper ates as an HDLC c ontroller .

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FCC HDLC Co ntr o ll er MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 36-15 Figure 36- 8 shows interrupts that can be gene ra ted in the HDLC protocol. T a bl e 36-9. FCCE/FCCM Field Desc riptions Bits Name Descri ption 0–7 — Reserved, shoul d be clear ed.

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FCC HDLC Controller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 36-16 F re escale Sem icondu ctor Figure 36-8. HDL C Interrupt Event Examp l e 36.1 0 FCC Status Regi ster (FCCS) The FCCS r e gister , shown in Figur e 36-9 , a llows the user to monitor real-time status conditions on the RXD line.

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FCC HDLC Co ntr o ll er MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 36-17 T able 36-10 desc ribes FCCS bits . T able 36-10. FCCS Register Field Descriptions Bits Name Descripti on 0–4 — Reserved, shoul d be clear ed.

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FCC HDLC Controller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 36-18 F re escale Sem icondu ctor.

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 37-1 Chapter 3 7 FCC T r ansparent Con troller The FCC transpare nt controller functions as a high- speed serial-to-parallel and parallel-to-serial converter .

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FC C T ransp aren t Co ntr olle r MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 37-2 F re escale Sem icondu ctor • Reverse data mode • Another protocol can be perfor med on the FCC’ s other half ( transmitter or r eceiver ) during transparent m ode • External BD ta ble 37.

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F CC T ran sp aren t Co ntro ller MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 37-3 following the 8-bit SYNC. T his eff ectively links the transmitter s ynchronization to the receiver synchronization. 37.

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FC C T ransp aren t Co ntr olle r MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 37-4 F re escale Sem icondu ctor Figure 37-2. Sending T ransparent Fram es b etwee n P owerQUICC IIs PowerQUICC II ( A) and Power QUICC II(B) exc hange trans par ent frame s and synchronize eac h other using R TS and CD .

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 38-1 Chapter 3 8 Serial P eriphera l Interface (SPI) The se rial per ipheral int erface (S P I) allows the .

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Se ri a l Peri p he r al In t er fa c e ( S P I) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 38-2 F re escale Sem icondu ctor • W or ks with data characters from 4 to 16 bits lo.

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Serial Pe ripheral Interface (SPI) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 38-3 38.3 Configuri ng the SP I Contr oller The SPI can be programmed to work in a single- or multiple-m a s ter en vironme nt.

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Se ri a l Peri p he r al In t er fa c e ( S P I) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 38-4 F re escale Sem icondu ctor When multiple T xB Ds ar e ready , T xB D[L] determines whether the SPI keeps transmitting without SPCOM[ STR] bei ng set aga i n.

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Serial Pe ripheral Interface (SPI) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 38-5 Figure 38-3. M ultimaster Con f iguration The maximum sustained data rate that the SPI supports is SYST E MCLK/50.

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Se ri a l Peri p he r al In t er fa c e ( S P I) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 38-6 F re escale Sem icondu ctor mode. Gaps should be inserted betwee n multiple cha r acters to keep from exc eeding the maximum sustained data rate.

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Serial Pe ripheral Interface (SPI) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 38-7 Figur e 38-5. SPI T rans f er Fo rmat with SPM ODE[CP] = 0 Figure 38- 6 shows the SPI tr ansfer form at in which SPICLK starts toggling at the beginning of the t ransfe r (SPM OD E[CP] = 1).

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Se ri a l Peri p he r al In t er fa c e ( S P I) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 38-8 F re escale Sem icondu ctor Figur e 38-6. SPI T rans f er Fo rmat with SPM ODE[CP] = 1 38.4.1.1 SPI Example s with Different SPMODE[LEN] V alues The examples below s how how SPMODE[LEN] is us ed to determine character length.

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Serial Pe ripheral Interface (SPI) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 38-9 with LEN =7 (d at a si ze =8 ), th e fo ll ow in g dat a is sel ec .

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Se ri a l Peri p he r al In t er fa c e ( S P I) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 38-10 F re escale Sem icondu ctor 38.4.3 S PI Com mand Re giste r (SP COM) The SPI command register (SPCOM), s hown in Figure 38-8 , is used to start SPI operation.

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Serial Pe ripheral Interface (SPI) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 38-11 T ab le 38-5. SP I P aram eter RAM Memo ry M ap Offset 1 1 F rom the pointe r val ue programmed in SPI_BASE at IMMR + 0x89FC .

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Se ri a l Peri p he r al In t er fa c e ( S P I) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 38-12 F re escale Sem icondu ctor 38.5.1 Rec eive/T ran smi t Funct ion C ode R eg isters ( RFCR /TFCR) Figure 38- 9 shows the f ields in the r ece ive/transmit f unc tion code r egisters (RFCR/TFCR).

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Serial Pe ripheral Interface (SPI) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 38-13 38.7 The SPI Buffe r Descriptor (BD) T ab le As shown in Figure 38-10 , BDs are or ganized into separate RxBD and TxBD tables in dual-port RAM.

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Se ri a l Peri p he r al In t er fa c e ( S P I) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 38-14 F re escale Sem icondu ctor — For a TxBD, this is the number of octets the CP s hould transmit f rom its buffer . Normally , this value should be gr eater than zero.

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Serial Pe ripheral Interface (SPI) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 38-15 38.7.1.2 SPI T ransmit BD (Tx BD) Data to be s ent w i th the SPI is se nt to the CP by ar ranging it in buffers referenced by T xBDs in the TxBD table.

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Se ri a l Peri p he r al In t er fa c e ( S P I) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 38-16 F re escale Sem icondu ctor 38 .8 SPI Mas ter Pr ogram m i n g Exa mple The fol lowing sequence initializes the SPI t o run at a high speed in master mode : 1.

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Serial Pe ripheral Interface (SPI) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 38-17 8. Initialize the TxBD. As sume the T x buf fer is at 0x0000_2000 in main memory and c ontains five 8-bit characters.

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Se ri a l Peri p he r al In t er fa c e ( S P I) MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 38-18 F re escale Sem icondu ctor NO T E If the master sends 3 bytes and negates SPIS E L , the RxBD is closed but the TxBD remains open.

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 39-1 Chapter 3 9 I 2 C Contr oller The inter- integrated cir cuit (I 2 C®) controlle r lets the PowerQUICC II exc ha nge data with other I 2 C devices, such a s microcontrollers, EEPROMs , real-time clock devices, A/D converters, and LCD displays.

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I 2 C Controll er MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 39-2 F re escale Sem icondu ctor 39.1 Featur es The fol lowing is a lis t of the I 2 C contr oller ’ s ma in featur.

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I 2 C Controll er MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 39-3 because the R/W request follo ws the slave port address in th e I 2 C bus specif i cation, the R/W r eques t bit must be placed in the lsb (bit 7) unles s operating i n reverse data mode; s ee Section 39.

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I 2 C Controll er MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 39-4 F re escale Sem icondu ctor A master write occurs as follows: 1. The m aster c ore sets I2COM [STR] . The t rans fer star ts when the SDM A channel loads t he Tx F IFO with data and t he I 2 C bus is not busy .

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I 2 C Controll er MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 39-5 3. After the first byte is shifted in, the s lave compares the received data to its s lave address. If the slave is an Power QUICC II, the addr ess is programmed in its I 2 C addr ess register (I2ADD).

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I 2 C Controll er MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 39-6 F re escale Sem icondu ctor 39 .4 I 2 C Regi ster s The following se ctions describe the I 2 C re g i st er s. 39.4.1 I 2 C Mo de Register (I2MOD) The I 2 C mode register , shown in Figure 39-6 , c ontrols the I 2 C modes and clock source.

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I 2 C Controll er MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 39-7 T able 39-2 describes I2ADD fields . 39.4.3 I 2 C Bau d Rate Generat or Register (I2BRG) The I 2 C baud rate generator registe r , shown in F igure 39-8 , sets t he divide ra tio of the I 2 C B RG .

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I 2 C Controll er MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 39-8 F re escale Sem icondu ctor T able 39-4 describes the I 2C ER/I2CMR fields. 39.4.5 I 2 C Com mand R egist er (I 2COM) The I 2 C command r egister , shown i n Figure 39-10 , is used to start I 2 C trans fers and to se lect mas ter or slave mode.

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I 2 C Controll er MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 39-9 39 .5 I 2 C P a rame te r RAM The I 2 C controller paramete r table is used f or the general I 2 C paramete rs and is similar to the SCC general-purpose par ameter RAM.

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I 2 C Controll er MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 39-10 F re escale Sem icondu ctor Figure 39- 11 shows the RFCR/TFC R bit fields . T able 39-7 describ es the RFCR/T F CR b i t field s. 0x10 RBPTR Hword RxBD poi nter .

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I 2 C Controll er MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 39-11 39 .6 I 2 C Comma nds The I 2 C transmit and r eceive commands, shown in T able 39-8 , are issued to the CP command register (CP CR). 39.

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I 2 C Controll er MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 39-12 F re escale Sem icondu ctor Figure 39-12 . I 2 C Memo ry S truc ture 39.7.1 I 2 C Bu ffe r Descrip tors (BDs) Receive and transmit buffer descriptors r eport information about e ach buffer transferred and whether a maskable interrupt should be gene rated.

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I 2 C Controll er MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 39-13 T able 39-9 describes I 2 C RxB D status and control bits . 39.7.1.2 I 2 C T ransmit Buffer Descriptor (TxBD) T ra nsmit data is a rranged in buff ers re ference d by TxBDs in the TxBD table .

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I 2 C Controll er MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 39-14 F re escale Sem icondu ctor T able 39-10 describes I 2 C T xBD status and control bits . 0123456 1 2 1 3 1 4 1 5 Of fset + 0 R — WI LS — NAK UN CL Of fset + 2 Dat a Length Of fset + 4 Tx Bu ffer P oin ter Of fset + 6 Figure 39-14 .

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MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 40-1 Chapter 4 0 P aralle l I/O P orts The CPM supports four general-purpose I/O ports—ports A, B, C, and D. Each pin in the I/O por ts can be configured as a general-purpose I/O si gnal or as a de dicated per ipheral interface s ignal.

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Parall el I/O Ports MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 40-2 F re escale Sem icondu ctor T able 40-1 desc ribes PODR fi elds.

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Parall el I/O Ports MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 40-3 40.2.3 P or t D ata Directio n Registers (PDIR A–PDIRD) The port data dir ec t ion register(PDIR), shown in Figur e 40-3 , is cleared at system reset .

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Parall el I/O Ports MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 40-4 F re escale Sem icondu ctor 40.2.4 P or t P in A ssig nm ent Re gi ster (PP AR) The port pin a ssignment register ( PP AR) is clea red at system reset. T able 40-2 desc ribes PP AR x fields.

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Parall el I/O Ports MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 40-5 PSOR bits are e f f ective only if the corresponding PP AR x [D D x ] = 1 (a dedicated pe ripheral function). T able 40-4 desc ribes PSOR x f ields.

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Parall el I/O Ports MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 40-6 F re escale Sem icondu ctor Figu re 40- 6. P o rt F unction al O peration 40.4 P or t P ins Func t ions Each pin can operate as a general pur pose I/O pin or as a de dicated input or output pin.

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Parall el I/O Ports MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 40-7 40.4.1 Gene ral Purpo se I/O Pins Each one of the port pins is independently confi gured as a general- purpose I/O pin if the corresponding port pin as signment r egister ( PP AR ) bit is clear ed.

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Parall el I/O Ports MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 40-8 F re escale Sem icondu ctor Fi gure 40-7. Prima ry an d Secon dary O ption Program ming In the tables below , the default value for a primary opt ion is simply a r eference to the secondar y opti on.

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Parall el I/O Ports MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 40-9 PA 2 5 FCC1: TxD[0] 1 UT OPIA 8 FCC1: TxD[8] 1 UTOPI A 16 MSNUM[0] 2 PA 2 4 FCC1: .

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Parall el I/O Ports MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 40-10 F re escale Sem icondu ctor PA 1 7 FCC1: RxD[7] 1 UT OPIA 8 FCC1: Rx D[ 15] 1 UTOPI A 16 FCC1: RxD[0 ] MII/HDLC ni b ble FCC1: RxD HDLC/t ransp .

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Parall el I/O Ports MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 F reesca l e Semiconduct or 40-11 T able 40-6 shows the port B pin as s i gnments.

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Parall el I/O Ports MPC8260 P o w erQUI CC II F amil y Refe r enc e Manual , Rev . 2 40-12 F re escale Sem icondu ctor T able 40-6. P ort B Dedicated Pin Assignme nt (PP ARB = 1) Pin Pin Function PSOR.

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