Intelメーカー80960HTの使用説明書/サービス説明書
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809 60HA/ HD/ H T 32- Bit Hig h -Pe r fo rmanc e Su pers ca la r Pr oce sso r Data sheet Pro duc t Fe atures ■ 32 - B it Par a ll e l A r ch itectu r e — L oad/S t o r e Arch it ectur e — S ixteen 32 -B it Glob al R e gis t ers — S ixteen 32 -B it Lo cal R e gis t ers — 1 .
2 Da t a sh ee t INF O RMA T ION I N T H I S DOCUM E N T IS P R O V IDE D IN CO NNE CT IO N W I T H INT E L ® PRO DUCT S. NO L I CENSE , EX PRESS O R I M PL I E D, BY ES T O PPEL O R O T HER W I SE, T O ANY I N TEL L E CTUAL PRO P ER TY RI G H TS I S G R ANT E D BY THI S DO CUM ENT .
D a t ash ee t 3 Conte n ts Contents 1 . 0 A bout This Doc u me nt ......................... .................... ................... ................... .................... ............ 9 2 . 0 I n t el 80 960 Hx P r o ce sso r ........ ............
Cont e n t s 4 Da t a sh ee t 7 V CC 5 Cu rr en t- Lim i ti ng Res i s t or ................... ......................... .................... ................... ............. .3 8 8 A C Tes t Load ............... .................... ...............
D a t ash ee t 5 Conte n ts 57 A S u mm ar y of A li gne d an d Un al ign ed Tr an s f e r s fo r 8- Bi t B u s .. ................... .................... .......... 81 58 I d le Bu s O p er ati on ........... ................... ....................
Cont e n t s 6 Da t a sh ee t Revisio n Hi story Date Revi si on H i sto r y Sept ember 2002 008 F o rmat t ed t he dat asheet in a new t e mplat e . In “ 32-B i t P a rallel A r c h itec t u re ” o n p age 1 : • Remov ed ope rat i ng f r eq uency of 16/ 32 (bus / c ore) f r om 809 60HD.
D a t ash ee t 7 Conte n ts July 1998 (c ont inued) 007 (c ont inued) In T able 23 “ 80960Hx A C Ch aract e rist i cs ” on page 42 : • A dded overbars whe r e re qui r ed. • M odif i ed T DV NH t o list sep a rat e spec i f icat i ons f o r 3.
Cont e n t s 8 Da t a sh ee t Th is p a g e inten t ion a l l y lef t blank..
8096 0HA/H D /HT Dat ash ee t 9 1. 0 A bo ut T h i s D o c u me n t Th is d o cu m e n t d e scr i b e s th e p a r a m e tr ic p e rf o r m an ce o f I n tel ’ s 8 096 0H x embedd ed s up e rs cal ar mi cro p rocess o rs .
809 60HA / HD/HT 10 Da t a sh ee t In ad di ti on t o exp a nded cl ock freq u ency op ti o n s , t h e 8 096 0H x pro v i d es es sen ti a l en hancem ent s for an emer gin g clas s o f h i gh -p erfo rmanc e embed d ed applications .
8096 0HA/H D /HT Dat ash ee t 11 s ub s y s tem s with m i n i m u m sy st em co m p lex ity . T o r e du ce th e ef f ect o f wait s t ates, th e bu s d e sig n is d eco up l ed f r o m th e co r e . Th is lets th e p r o cesso r ex ecu te in str u ctio n s w h ile th e b u s p e rf o r m s memo ry acce ss es i n depen d en tl y .
809 60HA / HD/HT 12 Da t a sh ee t 2.2. 6 D ual Pr og r a mmable T i m e rs The p r oces so r p r ov i d es t w o i ndep e nden t 32 -bi t t i m ers , w it h four pro g ramm abl e cl ock rat e s . The us e r con f igur es t h e timers thro ugh the T i mer Unit reg i s t ers .
8096 0HA/H D /HT Dat ash ee t 13 2. 3 I nst r uction Set Sum m ary Ta b l e 4 su mmari zes t h e 8 09 60H x i n st r u ct i on s e t by l og i cal g r ou pi ng s.
809 60HA / HD/HT 14 Da t a sh ee t 3.0 P ac kage In fo r m atio n Thi s s ect i o n des c ri bes t h e p i ns , p i nou t s and t h er mal ch aract eri s ti cs f o r t h e 80 960 H x i n t h e 1 68- pi n ceramic Pin Grid Array (PG A ) packa g e, 2 08- pin PowerQu a d2* (PQ4).
8096 0HA/H D /HT Dat ash ee t 15 3.1 P i n Descr i p ti ons Thi s s ect i o n d e fi nes t h e 8 096 0H x p i ns . Ta b l e 6 p r esen ts th e leg e nd f o r i n ter p r e ti ng th e p i n d e scr i p tio n s in Ta b l e 7 .
809 60HA / HD/HT 16 Da t a sh ee t T a ble 7 . 8 0960 H x P r o c ess or Fa mi ly Pin De sc r i p t ions ( S he e t 1 of 4 ) Name T y p e D escri p ti on A31:2 O H(Z) B( Z) R(Z) ADDRE SS BU S carries t he upper 30 bit s of t he ph ysical addres s. A 31 is t he m o st signif i ca nt add ress bit an d A2 i s t he least signif i c ant .
8096 0HA/H D /HT Dat ash ee t 17 SU P O H( Z ) B( Z ) R(1) S U PE R V IS OR ACCE SS indicat e s wh et her t he cur r ent bus acc e ss originat es f r om a reques t iss ued while in super visor m ode or us er m ode.
809 60HA / HD/HT 18 Da t a sh ee t HOLD I S( L ) HOL D RE QUE S T signals t hat an ext e rnal a gent request s acc e ss t o t he proces sor ’ s addr ess, data, and cont rol bus es. W hen HO LD is ass e rt ed, t he proces sor: Comp l e t e s t he curr ent bus request .
8096 0HA/H D /HT Dat ash ee t 19 CL K I N I CL OCK I N P U T pr ovides t he t i m e bas e f o r t he 80960Hx. A ll int e rn al circu i t r y is synch ronized t o CLKI N.
809 60HA / HD/HT 20 Da t a sh ee t 3. 2 80960Hx Mechanic al Dat a 3.2. 1 80960Hx PG A Pinout Fi gu r e 2 dep i ct s t h e comp l e t e 80 960 H x PG A pi no ut as vi ew ed fr om t h e t op s i de of t h e co mpon ent (i.
8096 0HA/H D /HT Dat ash ee t 21 Figur e 3 . 80960 Hx 1 68 - Pin P G A Pinout — V i e w fr om B o ttom (P i n s Fa c i n g U p ) D5 D7 D8 D9 D1 1 D 12 D13 D 15 D16 D 1 7 D19 D 21 D24 D 25 D2 D4 D6 V.
809 60HA / HD/HT 22 Da t a sh ee t T a ble 8 . 80960 H x 168 - P in PG A P i nout — Signa l Na me Or de r (Sh ee t 1 of 2 ) Si gna l Na m e PG A Pi n Si gna l Na m e PG A Pi n Si gna l Na m e PG A P.
8096 0HA/H D /HT Dat ash ee t 23 V CC J16 V CCP LL B1 0 V SS H3 V SS Q1 0 V CC K2 VO L D ET A5 V SS H1 5 V SS Q1 1 V CC K1 6 V SS A1 V SS J3 W/R S10 V CC M2 V SS C4 V SS J15 WA I T S12 V CC M16 V SS C.
809 60HA / HD/HT 24 Da t a sh ee t T a ble 9 . 80960 H x 168 - P in PG A P i nout — Pin Numbe r O r de r (S he e t 1 of 2 ) PG A Pi n Si gn al N a m e PG A Pi n Si gn al N a m e PG A Pi n Si gn al N.
8096 0HA/H D /HT Dat ash ee t 25 Q4 D28 Q1 6 A2 1 R1 1 V CC S6 BE 2 Q5 D30 Q1 7 A1 8 R12 BS T A LL S7 BE 1 Q6 V CC R1 D24 R13 BR EQ S8 BLAS T Q7 V SS R2 D27 R14 A2 9 S9 DE N Q8 V SS R3 D31 R15 A2 6 S1.
809 60HA / HD/HT 26 Da t a sh ee t 3.2. 2 80960Hx PQ 4 P i nout F i gu r e 4 . 8 096 0Hx 208 - P in P Q 4 Pi nou t PI N 1 P I N 208 PIN 5 2 PI N 5 3 PIN 1 04 P I N 157 P I N 156 V CC V SS V SS V CC FA.
8096 0HA/H D /HT Dat ash ee t 27 T a b l e 10 . 80960 Hx P Q 4 P i nou t — S i gna l Na me O r de r ( S he e t 1 of 2 ) Si gn al N a m e PQ 4 Pi n Si gn al N a m e PQ 4 Pi n Si gn al N a m e PQ 4 Pi.
809 60HA / HD/HT 28 Da t a sh ee t V CC 92 V CC 187 V SS 70 V SS 164 V CC 95 V CC 196 V SS 73 V SS 170 V CC 101 V CC 199 V SS 75 V SS 172 V CC 102 V CC 201 V SS 80 V SS 178 V CC 109 V CC 204 V SS 86 V.
8096 0HA/H D /HT Dat ash ee t 29 T a b l e 1 1 . 80 960 Hx P Q 4 P i nou t — P i n Numbe r Or de r (S he e t 1 of 2 ) PQ 4 Pi n Si gna l Na m e PQ 4 Pi n Si gna l Na m e PQ 4 Pi n Si gna l Na m e PQ.
809 60HA / HD/HT 30 Da t a sh ee t 121 A2 0 143 V CC 165 V CC 187 V CC 122 V SS 144 A7 166 XI N T 3 188 TDO 123 V CC 145 A6 167 XI N T 2 189 P CHK 124 A1 9 146 A5 168 XI N T 1 190 V SS 125 A1 8 147 A4.
8096 0HA/H D /HT Dat ash ee t 31 3.3 P ack age Ther m al S p ec ifi cati on s The 809 60Hx is s p ecified for op eration wh en T C (cas e temp erature) is within the ran g e o f 0 ° C to 8 5 ° C. T C ma y be meas u r ed i n any env i r onm ent to d e termine wh ether th e 80 960 H x is wit h in the s p ecified op erating r a nge.
809 60HA / HD/HT 32 Da t a sh ee t T a b l e 1 2 . M axi mu m T A a t V a rio u s Airf lo w s i n ° C (P GA P acka g e On l y ) Ai rfl o w -f t / m i n (m/ sec) f CL KI N (MHz ) 0 (0) 200 (1.
8096 0HA/H D /HT Dat ash ee t 33 T a b l e 14 . M aximu m T A at V a rious Ai rf low s in ° C ( P Q 4 P ac kag e O n ly ) Ai rfl o w -f t / m i n (m/ sec) f CL KI N (M Hz) 0 (0) 200 (1.
809 60HA / HD/HT 34 Da t a sh ee t 3. 4 H ea t S i nk Ad hesi ves I n tel r eco mm e nd s s ilico n e - b ased ad h e si v e s t o attach h eat s i nk s t o th e PGA p ack ag e. T h er e is n o particular recomm endation con cernin g the PQ4 packag e.
8096 0HA/H D /HT Dat ash ee t 35 T a b l e 16 . F i el d s o f 809 60Hx Dev i ce ID Fi e l d V a l u e De f i ni t i on V e rs ion S ee T able 18 . I ndic a t e s m a j o r st epping changes. V CC 1 = 3. 3 V device I ndic a t e s t hat a dev i c e is 3.
809 60HA / HD/HT 36 Da t a sh ee t 3. 7 S ou r ces for Acces sori es The fo llowing is a lis t of s ugg es ted s our ces f o r 809 60Hx acces s o r i es . Th is is neith er an endo rse m ent no r a w a rr ant y of t h e perf orm a nce of any of t h e l i s t e d pro duct s and / or co mpan i e s.
8096 0HA/H D /HT Dat ash ee t 37 4 . 0 E lectr i cal S p ecifi catio ns 4.1 A b s o l ute M a xim u m Rat i ngs Wa r n i n g : S t res s i n g t h e devi ce b e yon d t h e “ Ab so lu te Max i m u m Rati ng s ” may caus e perm anent d a mage. Thes e are s t res s ratings o n ly .
809 60HA / HD/HT 38 Da t a sh ee t 4.3 R ec o mm e nded Conn ec ti ons P o w e r a n d g r ou nd c o nn ec ti o ns mu s t be m a de t o m u lti p l e V CC and V SS (GND) p i n s . E v ery 809 60H x - bas e d ci rcu it boar d s ho u l d i n cl ud e p o w e r ( V CC ) a n d g r ound ( V SS ) pl anes fo r po wer di st ri b u ti on.
8096 0HA/H D /HT Dat ash ee t 39 4. 5 V CCPLL Pin Requi rem e n t s W h en the voltage on th e VC C P LL power s u pply pin ex ceeds the V CC pi n v o lt a ge b y 0.
809 60HA /HD/HT 40 Da t a sh ee t 4 . 6 D . C . S p eci fic a tions T a b le 2 2 . 8 09 6 0Hx D . C . C h a r ac t e r is t i c s ( S h e et 1 o f 2) P e r t he condit i ons des cribed in Sec t ion 4. 3, “ R e comm ended Connect i ons ” on page 38 .
8096 0HA/H D /HT Dat ash ee t 41 I CC 5 Curr ent on t he V CC5 Pi n 80960HA 809 60HD 80960HT 200 200 200 µA 9 C IN I nput Cap a cit ance f o r : PQ 4 PG A 12 12 pF pF F C = 1 M H z 10 C OU T O u t pu.
809 60HA /HD/HT 42 Da t a sh ee t 4 . 7 A . C . S p ec i fi c a tions T a b le 2 3 . 8 09 6 0Hx A . C . C h a r ac t e r is t i c s ( S h e et 1 o f 2) Per condit i ons i n Sec t ion 4. 2, “ O per at ing Condit i ons ” on page 37 and Sec t ion 4. 7.
8096 0HA/H D /HT Dat ash ee t 43 T IS 2 In put S e tup fo r RE A DY , BT ER M , HO L D, and BO FF 6n s T IH 2 In put Hold for RE A DY , BT ER M , HO LD, and BO FF 2.
809 60HA /HD/HT 44 Da t a sh ee t T a b le 2 4 . A . C . C h a r ac t e r is t ics N o t es NOT ES : 1. See Sec t ion 4. 8, “ A C T i ming W a vef o rm s ” on p age 46 f o r wavef o rm s and def ini t ions. 2. See F i gur e 25, “ O u t put Delay or Hold vs.
8096 0HA/H D /HT Dat ash ee t 45 4.7.1 A . C . Test Conditions A . C . va l u es are der i ved u s i ng t h e 50 pF l o ad s ho w n i n F i g u r e 8 . F i gure 25, “ O u t p u t Delay o r H o ld v s . Load C a p acit a n ce ” on pag e 52 , show s how t i mi ngs v a ry w it h l o ad capaci t a nce.
809 60HA /HD/HT 46 Da t a sh ee t 4 . 8 A . C . T i m i ng W a vefor m s Figur e 9 . C L K I N W ave f o r m Figur e 10 . Output De la y W a ve f or m Figur e 1 1 . Out put De l ay W ave fo r m 2.0 V 1.5 V 0.8 V T CF T CH T CL T T CR CL KIN Out puts: 1.
8096 0HA/H D /HT Dat ash ee t 47 Figur e 1 2 . Out put Floa t W ave fo r m Figur e 1 3 . Input S e t up a nd Hold W a ve f or m Figur e 1 4 . NM I , X I NT7: 0 Input Se tup a nd Hold W ave f o r m Mi .
809 60HA / HD/HT 48 Da t a sh ee t Figur e 15 . H o l d Ac k nowle dge T i mings Figur e 1 6 . B u s Ba ck off ( B OFF ) T i mi ng s CL KIN 1. 5 V 1.5 V 1.
8096 0HA/H D /HT Dat ash ee t 49 Figur e 1 7 . TCK W ave fo r m Figur e 1 8 . Input S e t up a nd Hold W a ve f or ms fo r T BS IS 1 a nd T BS IH1 2. 0 V 1. 5 V 0. 8 V T BSC F T BS C H T BSC L T BSC T BSC R TC L K In pu t s : TM S 1.5 V 1. 5 V 1. 5 V TD I 1.
809 60HA / HD/HT 50 Da t a sh ee t Figur e 1 9 . Output De la y a nd Outp ut Floa t for T BS O V 1 a nd T BS OF1 Figur e 2 0 . Output De la y a nd Outp ut Floa t W ave fo r m for T BS OV 2 a nd T BSOF 2 Figur e 2 1 . I n put Se tup a nd Hold W ave f o r m fo r T BS IS 2 a nd T BS IH2 TC K 1.
8096 0HA/H D /HT Dat ash ee t 51 Figur e 2 2 . Ris e a nd Fa ll T i me De r a ting a t 8 5 ° C a nd M i nim u m V CC Figur e 2 3 . I CC Ac tiv e ( P owe r S upply ) v s . Fr e qu e nc y 5 0pF 100 pF 150 p F T i me (n s ) C L (p F) 5 4 3 2 1 2. 0 t o 0.
809 60HA / HD/HT 52 Da t a sh ee t Figur e 2 4 . I CC Ac tiv e (The r m a l ) v s . F r e que nc y Figur e 2 5 . Output De la y or Hol d vs . Loa d Ca p ac i t a nc e I CC A c t i v e (T he r m a l ) .
8096 0HA/H D /HT Dat ash ee t 53 F i gu r e 26 . O u t pu t De lay vs. T e mp e r at u r e Figur e 2 7 . Out put Hold T i me s v s . T e mpe r a t ur e F i gu r e 28 . O u t pu t De lay vs. V CC no m - 0 . 0 no m - 0 . 4 no m - 0 . 5 Out put V a l i d D e l a ys ( n s) @ 1.
809 60HA / HD/HT 54 Da t a sh ee t 5.0 B us W aveform s Figur e 29 . C o l d Re se t W ave for m CL KIN CT 3 : 0 , ADS , W/ R , DT /R , D 31: 0, STEST RESET V CC , VCC5 , LO C K , W A IT , DEN , B L A.
8096 0HA/H D /HT Dat ash ee t 55 F i gu r e 30 . W a rm Rese t W ave f o rm ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ Ma x i mu m RE SET Lo w to RES E T St a t e 16 C L K I N P e ri od s 1 C L K I N ∼ ∼ ∼.
809 60HA / HD/HT 56 Da t a sh ee t Figur e 3 1 . Ente r i ng ONCE Mo d e CL K I N ADS , B E 3 :0 , A 31 : 2, R E SET ONCE ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ CL KIN a nd V CC S t abl e a nd R ESE T l o w and O NC E lo w to RE SET hi gh , mi ni m u m 10 ,000 C L K I N P e r i ods.
8096 0HA/H D /HT Dat ash ee t 57 Figur e 32 . Non-Bur s t, Non - Pipe line d Re que s t s without W a i t S t a t es In ADS A 31:2 , S U P , D/C , L O CK, CT 3 : 0 W/ R BL AST DT /R DE N WA I T D 31: .
809 60HA / HD/HT 58 Da t a sh ee t Figur e 3 3 . N o n-Bur s t, Non- Pipe li ne d Re a d Re que s t with W a it S t a t es ADS A3 1 : 2 , BE3 : 0 W/ R BL AST DT / R DEN WA I T D3 1 : 0 , CL KIN A 3 21 D1 In V a lid V a lid A DP3 : 0 PCHK NOTE : B i t s 3 1 - 30, 27 -25 , 13 , a nd 5 a r e r e se rve d .
8096 0HA/H D /HT Dat ash ee t 59 Figur e 3 4 . Non-Bur s t, Non - Pipe line d W r ite Re que s t with W a it S t a t es ADS A 3 1:2, W/ R BL AST DT / R DEN WA I T D3 1 : 0 , CL KIN A3 2 1 D 1 Ou t A V.
809 60HA / HD/HT 60 Da t a sh ee t F i gu r e 3 5 . B u r s t , No n - Pi p e lin ed Re ad Re qu es t w i t hou t W a it S t at es, 32- Bit Bu s In 0 ADS A3 1 : 4 , SUP , CT 3 : 0 , D / C , BE3 : 0 , .
8096 0HA/H D /HT Dat ash ee t 61 Figur e 3 6 . Bur s t, Non-P i pe li ne d Re a d Re que s t w i th W a it S t a t es , 3 2 - Bit Bus ADS A 3 1:4, S U P , C T 3: 0, D / C , BE3 : 0 , L O CK W/ R BL AS.
809 60HA / HD/HT 62 Da t a sh ee t F i gu r e 3 7 . B u r s t , No n - Pi p e lin ed W r ite Re qu es t w i t hou t W a it S t at es, 32- Bit Bu s ADS A3 1 : 4 , SUP , CT 3 : 0 , D/C , BE3 : 0 , LO CK.
8096 0HA/H D /HT Dat ash ee t 63 Figur e 3 8 . Bur s t, Non-P i pe li ne d W r it e Re que s t w i t h W a it S t a t es , 3 2 - Bit Bus ADS A 31: 4, S U P , CT 3 : 0 , D/C , BE 3 : 0 , LOCK W/ R BL A.
809 60HA / HD/HT 64 Da t a sh ee t F i gu r e 3 9 . B u r s t , No n - Pi p e lin ed Re ad Re qu es t w i t h W a i t St at es , 16 - B i t Bu s ADS SUP , CT 3 : 0, W/ R BL AS T DT /R DEN A3 : 2 WA I .
8096 0HA/H D /HT Dat ash ee t 65 Figur e 4 0 . Bur s t, Non-P i pe li ne d Re a d Re que s t w i th W a it S t a t es , 8 - Bit Bus AD S SUP , C T 3:0, W/ R BL AST DT /R DEN A3 : 2 WA I T D3 1 : 0 , C.
809 60HA / HD/HT 66 Da t a sh ee t F i gu r e 4 1 . N on - Bu rs t , Pi p e lin ed Re ad Re qu es t w i t hou t W a it S t at es, 32- Bit Bu s ADS A3 1 : 4 , SUP , CT 3 : 0 , D/C , LO C K BL AST WA I .
8096 0HA/H D /HT Dat ash ee t 67 Figur e 4 2 . Non-Bur s t, P i pe li ne d Re a d Re que s t w i th W a it S t a t e s , 3 2 - Bit Bus ADS A 3 1:4, S U P , C T 3: 0, D / C , W/ R BL AS T DT /R DEN A3 : 2 WA I T D3 1 : 0 , CL KIN BE3 : 0 A1 A ’ D 1 D ’ IN D ’ V a lid V a lid I n va li d IN D LO C K V a lid V a lid I n va li d DP3 : 0 1.
809 60HA / HD/HT 68 Da t a sh ee t Figur e 4 3 . B u r s t, Pipe line d Re a d R e que s t without W a it S t a t es , 3 2 - Bi t B u s ADS A3 1 : 4 , SUP , CT 3 : 0 , D/C , BE3 : 0 , LO CK W/ R BL AS.
8096 0HA/H D /HT Dat ash ee t 69 F i gu r e 44 . Bu rs t , Pi p e lin ed Re ad Re qu es t w i t h W a i t St at es , 32 - B it Bu s AD S A3 1 : 4 , SUP , CT 3 : 0 , D/C , BE3 : 0 , LO CK W/ R A3 : 2 D.
809 60HA / HD/HT 70 Da t a sh ee t Figure 4 5 . B u r s t , P i peline d Read R e quest w i t h W a it S t a t es , 8 - B i t Bus ADS A3 1 : 4 , S U P , CT 3 : 0 , D/ C , LO C K W/ R A3 : 2 BE 1 /A 1,.
8096 0HA/H D /HT Dat ash ee t 71 F i gu r e 46 . Bu rs t , Pi p e lin ed Re ad Re qu es t w i t h W a i t St at es , 16 - B it Bu s ADS A3 1 : 4 , S U P , CT 3 : 0 , D/C , BE 0 /B L C , W/ R A3 : 2 BE.
809 60HA / HD/HT 72 Da t a sh ee t Figur e 4 7 . U s ing E x te r n a l RE AD Y CL KIN ADS A3 1 : 4 , SUP , DT /R DEN READY W/ R C T 3:0, D / C , BL AS T BT ERM A3 : 2 WA I T D3 1 : 0 , BE3 : 0 , LO C.
8096 0HA/H D /HT Dat ash ee t 73 Figur e 4 8 . T e r m ina t ing a Bur s t with BTE R M CL K I N ADS A3 1 : 4 , SUP , DT /R DEN READY W/ R CT 3 : 0 , D/C , BL AST BT ERM A3 : 2 WA I T D3 1 : 0 , BE3 :.
809 60HA / HD/HT 74 Da t a sh ee t The p r oces s o r may s t all ( B ST ALL as s e rted) even wit h an em pty b u s qu eue (B R E Q d eas s e rted ). D e p e nd i n g o n t h e i n st ru ct i o n s t ream a nd m e mory w a it st at es , t h e t w o si gn al s m a y b e sep a rat e d b y s e v e ral C L KI N cycles .
8096 0HA/H D /HT Dat ash ee t 75 Figur e 5 0 . BOFF Func tiona l T i ming. BOFF oc c u r s dur i n g a bur s t or non -bur s t d a t a cyc le . ADS BL AS T READY BO FF A3 1 : 2 , S U P , DP3 : 0 &.
809 60HA / HD/HT 76 Da t a sh ee t Figur e 51 . H O LD F unc t i ona l T i mi ng W o rd R ea d R equ est N RA D =1 , N XD A =1 Wo r d Re ad R e quest N RA D =0 , N XD A =0 H o l d S t at e H ol d S t .
8096 0HA/H D /HT Dat ash ee t 77 Figur e 5 2 . LOCK De lays HOLDA T i ming Figur e 5 3 . F A IL Fu nc t i on a l T i ming CL KIN ADS BL AST HO L D HOL D A LO C K W/ R RESET FA I L 257 ,51 7 C y c l e .
809 60HA / HD/HT 78 Da t a sh ee t Figur e 5 4 . A S u mma r y of Ali gn e d a nd Una l ign e d T r a n s f e r s for 3 2 - B it Re gions 04 8 1 2 1 6 2 0 2 4 01 23 4 5 6 One D o ubl e- W o r d S hor .
8096 0HA/H D /HT Dat ash ee t 79 Figur e 5 5 . A Summa r y of Aligne d a nd Una ligne d T r a n s f e r s f o r 3 2 - Bit Re gions (Cont i n ue d) 04 8 1 2 1 6 2 0 2 4 01 2 3 4 5 6 Tr i p l e - W o r .
809 60HA / HD/HT 80 Da t a sh ee t Figur e 5 6 . A S u mma r y of Ali gn e d a nd Una l ign e d T r a n s f e r s for 1 6 - B it Bus 04 8 1 2 1 6 2 0 2 4 01 23 4 5 6 B y te Of fs et W o rd Of fse t D .
8096 0HA/H D /HT Dat ash ee t 81 Figur e 5 7 . A Summa r y of Aligne d a nd Una ligne d T r a n s f e r s f o r 8 - Bit Bus 04 8 1 2 1 6 2 0 2 4 01 23 4 5 6 B y te Of fse t W o r d O f fse t S hort 8 .
809 60HA / HD/HT 82 Da t a sh ee t F i gu r e 5 8 . I d l e Bu s O p e r atio n CL KIN ADS A3 1 : 4 , SUP , D/ C , LOC K W/ R B L AST DT /R DEN A3 : 2 WA I T D3 1 : 0 READY , BTERM W r i t e R e quest.
8096 0HA/H D /HT Dat ash ee t 83 F i gu r e 59 . Bu s S t at es Ti = I D L E Th = H O L D T a = A D DRE SS Td = D A T A Tb = B O F F ’ ed T a w= a ddr ess to d a ta wa i t T o = ONCE Ta Tb Td 1 Ta w.
809 60HA / HD/HT 84 Da t a sh ee t 5.1 80960Hx Bo undary S can Chain T a b l e 2 6 . 8096 0Hx Bo und a ry S ca n Ch ain ( S h eet 1 o f 4 ) # B oun da r y S ca n Ce ll Ce ll T y p e Com m e nt DP 3 B .
8096 0HA/H D /HT Dat ash ee t 85 D 21 B i d ire c t i onal D 22 B i d ire c t i onal D 23 B i d ire c t i onal D 24 B i d ire c t i onal D 25 B i d ire c t i onal D 26 B i d ire c t i onal D 27 B i d .
809 60HA / HD/HT 86 Da t a sh ee t LO CKB A R O ut put BRE Q O u t put A31 O ut put A30 O ut put A29 O ut put A28 O ut put A27 O ut put A26 O ut put A25 O ut put A24 O ut put A23 O ut put A22 O ut put.
8096 0HA/H D /HT Dat ash ee t 87 X I N T 7B AR I nput A ppears as XI NT BAR (7: 0 ) in BS DL f ile. X I N T 6B AR I nput X I N T 5B AR I nput X I N T 4B AR I nput X I N T 3B AR I nput X I N T 2B AR I nput X I N T 1B AR I nput X I N T 0B AR I nput R ESE T BA R I nput C L KI N I nput C T 3 O ut put A ppears as CT (3: 0 ) in B S DL f i le.
809 60HA / HD/HT 88 Da t a sh ee t 5.2 B ound a r y Scan Description Lang uage Examp l e The B oun dary -Scan Des c ription Lang uage (B SDL) f o r PGA Package Examp l e, as s h own in Examp l e 1 , m eet s the de-fac t o s t an dard means o f des c rib i ng es s e n tial features of ANS I / I EEE 1 149 .
8096 0HA/H D /HT Dat ash ee t 89 -- Project code HA -- File **NOT** verified electrically -- ------------------------------------------------ -- Rev 0.7 18 Dec 1995 Updated for A-1 stepping. -- Rev 0.6 08 Dec 1994 -- Rev 0.5 21 Nov 1994 -- Rev 0.4 31 Oct 1994 -- Rev 0.
809 60HA / HD/HT 90 Da t a sh ee t SUPBAR : out bit; TCK : in bit; TDI : in bit; TDO : out bit; TMS : in bit; TRST : in bit; WAITBA R : out bit; WRBAR : out bit; XINTBAR : in bit_vector(0 to 7); FIVEV.
8096 0HA/H D /HT Dat ash ee t 91 “ D : (E03, C02, D02, C01, E02, D01, F02, E01, F01, ”& “ G01, H02, H01, J01, K01, L02, L01, M01, N01, ”& “ N02, P01, P02, Q01, P03, Q02, R01, S01, Q0.
809 60HA / HD/HT 92 Da t a sh ee t attribute Tap_Scan_In of TDI : signal is true; attribute Tap_Scan_Mode of TMS : signal is true; attribute Tap_Scan_Out of TDO : signal is true; attribute Tap_Scan_Reset of TRST : signal is true; attribute Tap_Scan_Clock of TCK : signal is (66.
8096 0HA/H D /HT Dat ash ee t 93 attribute Boundary_Cells of Ha_Processor: entity is “ BC_4, BC_1, CBSC_1 ”; attribute Boundary_Length of Ha_Processor: entity is 112; attribute Boundary_Register o.
809 60HA / HD/HT 94 Da t a sh ee t “ 35 (CBSC_1, D(25), bidir, X, 17, 1, Z), ” & “ 36 (CBSC_1, D(26), bidir, X, 17, 1, Z), ” & “ 37 (CBSC_1, D(27), bidir, X, 17, 1, Z), ” & “.
8096 0HA/H D /HT Dat ash ee t 95 “ 74 (BC_1, A(21), output3, X, 80, 1, Z), ” & “ 75 (BC_1, A(20), output3, X, 80, 1, Z), ” & “ 76 (BC_1, A(19), output3, X, 80, 1, Z), ” & “ 7.
809 60HA / HD/HT 96 Da t a sh ee t E xa m p l e 2. Bound a r y-S c an Descr ipt i on Langu a g e ( B S D L) f o r P Q 2 P ack ag e Ex amp l e ( S h eet 1 o f 8) -- Copyright Intel Corporation 1995, 19.
8096 0HA/H D /HT Dat ash ee t 97 entity Ha_Processor is generic(PHYSICAL_PIN_MAP : string:= “ PQ2 ” ); port (A : out bit_vector(2 to 31); ADSBAR : out bit; BEBAR : out bit_vector(0 to 3); BLASTBAR.
809 60HA / HD/HT 98 Da t a sh ee t VCC1 : linkage bit_vector(0 to 23); VCC2 : linkage bit_vector(0 to 23); VSS1 : linkage bit_vector(0 to 23); VSS2 : linkage bit_vector(0 to 23) ); use STD_1149_1_1990.
8096 0HA/H D /HT Dat ash ee t 99 “ ONCEBAR : 6, ”& “ PCHKBAR : 189, ”& “ READYBAR : 68, ”& “ RESETBAR : 174, ”& “ STEST : 208, ”& “ SUPBAR : 97, ”& “ .
809 60HA / HD/HT 100 Da t a sh ee t “ BYPASS (11 11), ” & “ EXTEST (00 00), ” & “ SAMPLE (00 01), ” & “ IDCODE (00 10), ” & “ RUBIST (01 11), ” & “ CLAMP (01 .
8096 0HA/H D /HT Dat ash ee t 10 1 “ 6 (BC_1, *, control, 1), ” & “ 7 (BC_4, ONCEBAR, input, X), ” & “ 8 (BC_4, BOFFBAR, input, X), ” & “ 9 (CBSC_1, D(0), bidir, X, 17, 1, Z).
809 60HA / HD/HT 102 Da t a sh ee t “ 41 (CBSC_1, D(31), bidir, X, 17, 1, Z), ” & “ 42 (BC_4, BTERMBAR, input, X), ” & “ 43 (BC_4, READYBAR, input, X), ” & “ 44 (BC_4, HOLD, .
8096 0HA/H D /HT Dat ash ee t 10 3 “ 76 (BC_1, A(19), out put3, X, 80, 1, Z), ” & “ 77 (BC_1, A(18), out put3, X, 80, 1, Z), ” & “ 78 (BC_1, A(17), out put3, X, 80, 1, Z), ” & .
809 60HA / HD/HT 104 Da t a sh ee t Th is p a g e inten t ion a l l y lef t blank..
デバイスIntel 80960HTの購入後に（又は購入する前であっても）重要なポイントは、説明書をよく読むことです。その単純な理由はいくつかあります：
Intel 80960HTをまだ購入していないなら、この製品の基本情報を理解する良い機会です。まずは上にある説明書の最初のページをご覧ください。そこにはIntel 80960HTの技術情報の概要が記載されているはずです。デバイスがあなたのニーズを満たすかどうかは、ここで確認しましょう。Intel 80960HTの取扱説明書の次のページをよく読むことにより、製品の全機能やその取り扱いに関する情報を知ることができます。Intel 80960HTで得られた情報は、きっとあなたの購入の決断を手助けしてくれることでしょう。
Intel 80960HTを既にお持ちだが、まだ読んでいない場合は、上記の理由によりそれを行うべきです。そうすることにより機能を適切に使用しているか、又はIntel 80960HTの不適切な取り扱いによりその寿命を短くする危険を犯していないかどうかを知ることができます。
ですが、ユーザガイドが果たす重要な役割の一つは、Intel 80960HTに関する問題の解決を支援することです。そこにはほとんどの場合、トラブルシューティング、すなわちIntel 80960HTデバイスで最もよく起こりうる故障・不良とそれらの対処法についてのアドバイスを見つけることができるはずです。たとえ問題を解決できなかった場合でも、説明書にはカスタマー・サービスセンター又は最寄りのサービスセンターへの問い合わせ先等、次の対処法についての指示があるはずです。
