IntelメーカーBX80646E31230V3の使用説明書/サービス説明書
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Intel ® Xeon ® Processor E3-1200 v3 Product Family Datasheet – Volume 1 of 2 June 2013 Order No.: 328907-001.
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Contents Revision History.................................................................................................................. 8 1.0 Introduction.............................................................................................
4.2 Processor Core Power Management......................................................................... 50 4.2.1 Enhanced Intel ® SpeedStep ® Technology Key Features..................................50 4.2.2 Low-Power Idle States...............
6.14 Processor Internal Pull-Up / Pull-Down Terminations................................................ 85 7.0 Electrical Specifications.............................................................................................. 86 7.1 Integrated Voltage Regulator.
Tables 1 Terminology........................................................................................................... 12 2 Related Documents.................................................................................................. 15 3 Processor DIMM Support by Product.
53 Processor Storage Specifications.............................................................................. 104 54 Processor Ball List by Signal Name.
Revision History Revision Description Date 001 • Initial Release June 2013 Processor—Revision History Intel ® Xeon ® Processor E3-1200 v3 Product Family Datasheet – Volume 1 of 2 June 2013 8 Order No.
1.0 Introduction The Intel ® Xeon ® processor E3-1200 v3 product family are 64-bit, multi-core processors built on 22-nanometer process technology. The processors are designed for a two-chip platform consisting of a processor and Platform Controller Hub (PCH).
Figure 1. Platform Block Diagram Processor PCI Express* 3.0 Digital Display Interface (DDI) (3 interfaces) System Memory 1333 / 1600 MT/s 2 DIMMs / CH CH A CH B Intel ® Flexible Display Interface (Intel ® FDI) (x2) Direct Media Interface 2.0 (DMI 2.
• Intel ® Advanced Encryption Standard New Instructions (Intel ® AES-NI) • PCLMULQDQ Instruction • Intel ® Secure Key • Intel ® Transactional Synchronization Extensions (Intel ® TSX) • .
1.4 Thermal Management Support • Digital Thermal Sensor • Adaptive Thermal Monitor • THERMTRIP# and PROCHOT# support • On-Demand Mode • Memory Open and Closed Loop Throttling • Memory Thermal Throttling • External Thermal Sensor (TS-on-DIMM and TS-on-Board) • Render Thermal Throttling • Fan speed control with DTS 1.
Term Description eDP Embedded Display Port EPG Electrical Power Gating EU Execution Unit FMA Floating-point fused Multiply Add instructions FSC Fan Speed Control HDCP High-bandwidth Digital Content Pr.
Term Description NCTF Non-Critical to Function. NCTF locations are typically redundant ground or non-critical reserved, so the loss of the solder joint continuity at end of life conditions will not affect the overall product functionality.
Term Description T CONTROL T CONTROL is a static value that is below the TCC activation temperature and used as a trigger point for fan speed control. When DTS > T CONTROL , the processor must comply to the TTV thermal profile. TDP Thermal Design Power: Thermal solution should be designed to dissipate this target power level.
Document Document Number / Location Advanced Configuration and Power Interface 3.0 http:// www.acpi.info/ PCI Local Bus Specification 3.0 http:// www.pcisig.com/ specifications PCI Express Base Specification, Revision 2.0 http:// www.pcisig.com DDR3 SDRAM Specification http:// www.
2.0 Interfaces 2.1 System Memory Interface • Two channels of DDR3/DDR3L Unbuffered Dual In-Line Memory Modules (UDIMM) with a maximum of two DIMMs per channel.
2.1.1 System Memory Technology Supported The Integrated Memory Controller (IMC) supports DDR3/DDR3L protocols with two independent, 64-bit wide channels each accessing one or two DIMMs. The type of memory supported by the processor is dependent on the PCH SKU in the target platform.
Raw Card Version DIMM Capacity DRAM Device Technology DRAM Organization # of DRAM Devices # of Physical Devices Ranks # of Row / Col Address Bits # of Banks Inside DRAM Page Size A 1 GB 1 Gb 128 M X 8.
Dual-Channel Mode – Intel ® Flex Memory Technology Mode The IMC supports Intel Flex Memory Technology Mode. Memory is divided into symmetric and asymmetric zones.
2.1.3.1 System Memory Frequency In all modes, the frequency of system memory is the lowest frequency of all memory modules placed in the system, as determined through the SPD registers on the memory modules. The system memory controller supports one or two DIMM connectors per channel.
2.2 PCI Express* Interface This section describes the PCI Express* interface capabilities of the processor. See the PCI Express Base* Specification 3.0 for details on PCI Express*. 2.2.1 PCI Express* Support The PCI Express* lanes (PEG[15:0] TX and RX) are fully-compliant to the PCI Express Base Specification, Revision 3.
• Traditional AGP style traffic (asynchronous non-snooped, PCI-X Relaxed ordering). • Peer segment destination posted write traffic (no peer-to-peer read traffic) in Virtual Channel 0: DMI -> PCI Express* Port 0 • 64-bit downstream address format, but the processor never generates an address above 64 GB (Bits 63:36 will always be zeros).
Figure 3. PCI Express* Related Register Structures in the Processor PCI-PCI Bridge representing root PCI Express ports (Device 1 and Device 6) PCI Compatible Host Bridge Device (Device 0) PCI Express*.
Figure 4. PCI Express* Typical Operation 16 Lanes Mapping 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 X 16 Co ntroller Lane 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Lane 1 Lane 2 Lane 3 Lane 4 Lane 5 Lane 6 Lane 7 Lane 8 Lane 9 Lane 10 Lane 11 Lane 12 Lane 13 Lane 14 Lane 15 0 1 2 3 4 5 6 7 1 X 8 Controller 0 1 2 3 1 X 4 Cont ro ller 2.
• 5 GT/s point-to-point DMI interface to PCH is supported. • Raw bit-rate on the data pins of 5.0 GB/s, resulting in a real bandwidth per pair of 500 MB/s given the 8b/10b encoding used to transmit data across this interface. Does not account for packet overhead and link maintenance.
2.4 Processor Graphics The processor graphics contains a generation 7.5 graphics core architecture. This enables substantial gains in performance and lower power consumption over previous generations. Up to 20 Execution Units are supported depending on the processor SKU.
Figure 5. Processor Graphics Controller Unit Block Diagram 2.5.1 3D and Video Engines for Graphics Processing The Gen 7.5 3D engine provides the following performance and power-management enhancements. 3D Pipeline The 3D graphics pipeline architecture simultaneously operates on different primitives or on different portions of the same primitive.
Vertex Shader (VS) Stage The VS stage performs shading of vertices output by the VF function. The VS unit produces an output vertex reference for every input vertex reference received from the VF unit, in the order received. Geometry Shader (GS) Stage The GS stage receives inputs from the VS stage.
Logical 128-Bit Fixed BLT and 256 Fill Engine This BLT engine accelerates the GUI of Microsoft Windows* operating systems. The 128-bit BLT engine provides hardware acceleration of block transfers of pixel data for many common Windows operations.
• The HDMI* interface supports HDMI with 3D, 4K, Deep Color, and x.v.Color. The DisplayPort* interface supports the VESA DisplayPort* Standard Version 1, Revision 2. • The processor supports High-bandwidth Digital Content Protection (HDCP) for high-definition content playback over digital interfaces.
• Organizing pixels into frames • Optionally scaling the image to the desired size • Re-timing data for the intended target • Formatting data according to the port output standard DisplayPort*.
TMDS data and clock channels. These channels are used to carry video, audio, and auxiliary data. In addition, HDMI carries a VESA DDC. The DDC is used by an HDMI Source to determine the capabilities and characteristics of the Sink. Audio, video, and auxiliary (control/status) data is transmitted across the three TMDS data channels.
Embedded DisplayPort* Embedded DisplayPort* (eDP*) is an embedded version of the DisplayPort standard oriented towards applications such as notebook and All-In-One PCs. Digital Port D can be configured as eDP. Like DisplayPort, Embedded DisplayPort also consists of a Main Link, Auxiliary channel, and an optional Hot-Plug Detect signal.
Table 7. Valid Three Display Configurations through the Processor Display 1 Display 2 Display 3 Maximum Resolution Display 1 Maximum Resolution Display 2 Maximum Resolution Display 3 HDMI HDMI DP 4096.
2.7 Intel ® Flexible Display Interface (Intel ® FDI) • The Intel Flexible Display Interface (Intel FDI) passes display data from the processor (source) to the PCH (sink) for display through a display interface on the PCH. • Intel FDI supports 2 lanes at 2.
Figure 9. Example for PECI Host-Clients Connection V TT Host / Originator Q1 nX Q2 1X PECI C PECI <10pF/Node Q3 nX V TT PECI Client Additional PECI Clients Interfaces—Processor Intel ® Xeon ® Processor E3-1200 v3 Product Family June 2013 Datasheet – Volume 1 of 2 Order No.
3.0 Technologies This chapter provides a high-level description of Intel technologies implemented in the processor. The implementation of the features may vary between the processor SKUs. Details on the different technologies of Intel processors and other relevant external notes are located at the Intel technology web site: http://www.
• More reliable: Due to the hardware support, VMMs can now be smaller, less complex, and more efficient. This improves reliability and availability and reduces the potential for software conflicts.
• Descriptor-Table Exiting — Descriptor-table exiting allows a VMM to protect a guest OS from internal (malicious software based) attack by preventing relocation of key system data structures like IDT (interrupt descriptor table), GDT (global descriptor table), LDT (local descriptor table), and TSS (task segment selector).
Figure 10. Device to Domain Mapping Structures Root entry 0 Root entry N Root entry 255 Context entry 0 Context entry 255 Context entry 0 Context entry 255 (Bus 255) (Bus N) (Bus 0) Root entry table (.
• Memory controller and processor graphics comply with the Intel VT-d 1.2 Specification. • Two Intel VT-d DMA remap engines. — iGFX DMA remap engine — Default DMA remap engine (covers all devi.
Another aspect of the trust decision is the ability of the platform to resist attempts to change the controlling environment. The Intel TXT platform will resist attempts by software processes to change the controlling environment or bypass the bounds set by the controlling environment.
Intel recommends enabling Intel HT Technology with Microsoft Windows* 8 and Microsoft Windows* 7 and disabling Intel HT Technology using the BIOS for all previous versions of Windows* operating systems. For more information on Intel HT Technology, see http://www.
digital signal processing software. FMA improves performance in face detection, professional imaging, and high performance computing. Gather operations increase vectorization opportunities for many applications.
performance of fine-grain locking while actually programming using coarse-grain locks. Details on Intel TSX may be found in Intel ® Architecture Instruction Set Extensions Programming Reference. 3.8 Intel ® 64 Architecture x2APIC The x2APIC architecture extends the xAPIC architecture that provides key mechanisms for interrupt delivery.
• The semantics for accessing APIC registers have been revised to simplify the programming of frequently-used APIC registers by system software. Specifically, the software semantics for using the In.
4.0 Power Management This chapter provides information on the following power management topics: • Advanced Configuration and Power Interface (ACPI) States • Processor Core • Integrated Memory Controller (IMC) • PCI Express* • Direct Media Interface (DMI) • Processor Graphics Controller Figure 11.
4.1 Advanced Configuration and Power Interface (ACPI) States Supported This section describes the ACPI states supported by the processor. Table 9. System States State Description G0/S0 Full On Mode. G1/S3-Cold Suspend-to-RAM (STR). Context saved to memory (S3-Hot state is not supported by the processor).
Table 13. Direct Media Interface (DMI) States State Description L0 Full on – Active transfer state. L0s First Active Power Management low power state – Low exit latency. L1 Lowest Active Power Management – Longer exit latency. L3 Lowest power state (power-off) – Longest exit latency.
• Multiple frequency and voltage points for optimal performance and power efficiency. These operating points are known as P-states. • Frequency selection is software controlled by writing to processor MSRs. The voltage is optimized based on the selected frequency and the number of active processor cores.
Figure 13. Thread and Core C-State Entry and Exit C 1 C 1 E C 7 C 6 C 3 C 0 M WAIT (C 1 ), HLT C 0 M WAIT (C 7 ), P_ LV L4 I/O R e ad M WAIT (C 6 ), P_ LV L3 I/O R e ad M WAIT (C 3 ), P_ LV L2 I/O R e.
Note: When P_LVLx I/O instructions are used, MWAIT sub-states cannot be defined. The MWAIT sub-state is always zero if I/O MWAIT redirection is used. By default, P_LVLx I/O redirections enable the MWAIT 'break on EFLAGS.IF’ feature that triggers a wakeup on an interrupt, even if interrupts are masked by EFLAGS.
Core C6 State Individual threads of a core can enter the C6 state by initiating a P_LVL3 I/O read or an MWAIT(C6) instruction. Before entering core C6 state, the core will save its architectural state to a dedicated SRAM. Once complete, a core will have its voltage reduced to zero volts.
— For package C-states, the processor is not required to enter C0 state before entering any other C-state. — Entry into a package C-state may be subject to auto-demotion – that is, the processor.
Figure 14. Package C-State Entry and Exit C 0 C 1 C 6 C 7 C 3 Package C0 State This is the normal operating state for the processor. The processor remains in the normal state when at least one of its cores is in the C0 or C1 state or when the platform has not granted permission to the processor to go into a low power state.
Package C2 State Package C2 state is an internal processor state that cannot be explicitly requested by software. A processor enters Package C2 state when: • All cores and graphics have requested a .
Note: Package C6 state is the deepest C-state supported on discrete graphics systems with PCI Express Graphics (PEG). Package C7 state is the deepest C-state supported on integrated graphics systems (or switchable graphics systems during integrated graphics mode).
2. Active power-down (APD): This mode is entered if there are open pages when de- asserting CKE. In this mode the open pages are retained. Power-saving in this mode is the lowest. Power consumption of DDR is defined by IDD3P. Exiting this mode is defined by tXP – small number of cycles.
4.3.2.2 Conditional Self-Refresh During S0 idle state, system memory may be conditionally placed into self-refresh state when the processor is in package C3 or deeper power state. Refer to Intel® Rapid Memory Power Management (Intel® RMPM) for more details on conditional self- refresh with Intel HD Graphics enabled.
4.3.4 DDR Electrical Power Gating (EPG) The DDR I/O of the processor supports Electrical Power Gating (DDR-EPG) while the processor is at C3 or deeper power state.
package, and the application demand for additional processor or graphics performance. The processor core control is maintained by an embedded controller. The graphics driver dynamically adjusts between P-States to maintain optimal performance, power, and thermals.
5.0 Thermal Management This chapter provides both component-level and system-level thermal management. Topics convered include processor thermal specifications, thermal profiles, thermal metrology, fa.
5.1 Thermal Metrology The maximum Thermal Test Vehicle (TTV) case temperatures (T CASE-MAX ) can be derived from the data in the appropriate TTV thermal profile earlier in this chapter. The TTV T CASE is measured at the geometric top center of the TTV integrated heat spreader (IHS).
The Ψ CA point at DTS = -1 defines the minimum Ψ CA required at TDP considering the worst case system design T AMBIENT design point: Ψ CA = (T CASE-MAX – T AMBIENT-TARGET ) / TDP For example, for a 95 W TDP part, the T case maximum is 72.6 °C and at a worst case design point of 40 °C local ambient this will result in: Ψ CA = (72.
Table 18. Digital Thermal Sensor (DTS) 1.1 Thermal Solution Performance Above T CONTROL Processor TDP Ψ CA at DTS = T CONTROL 1, 2 At System T AMBIENT- MAX = 30 °C Ψ CA at DTS = -1 At System T AMBIENT-MAX = 40 °C Ψ CA at DTS = -1 At System T AMBIENT-MAX = 45 °C Ψ CA at DTS = -1 At System T AMBIENT- MAX = 50 °C 84 W 0.
Figure 17. Digital Thermal Sensor (DTS) Thermal Profile Definition Table 19. Thermal Margin Slope PCG Die Configuration (Native) Core + GT TDP (W) TCC Activation Temperature (°C) MSR 1A2h 23:16 Temperature Control Offset MSR 1A2h 15:8 Thermal Margin Slope (°C / W) 2013D 4+2 (4+2) 84 100 20 0.
Performance Targets The following table provides boundary conditions and performance targets as guidance for thermal solution design. Thermal solutions must be able to comply with the Maximum T CASE Thermal Profile.
Processor PCG 2 Package TDP 3 Platform TDP 4 Heatsink 5 T LA , Airflow, RPM, Ѱ CA 6 Maximum T CASE Thermal Profile 7 T CASE-MAX @ Platform TDP 8 2C/GT2 35 W 1 2013A 35 W 35 W Active Short (DHA-D) 45.4 °C, 3000 RPM, 0.597 °C/W y = 0.51 * Power + 48.
method to use on a dynamic basis. BIOS is not required to select a specific method (as with previous-generation processors supporting TM1 or TM2). The temperature at which Adaptive Thermal Monitor activates the Thermal Control Circuit is factory calibrated and is not user configurable.
A small amount of hysteresis has been included to prevent rapid active/inactive transitions of the TCC when the processor temperature is near the TCC activation temperature.
PROCHOT# Signal An external signal, PROCHOT# (processor hot), is asserted when the processor core temperature has exceeded its specification. If Adaptive Thermal Monitor is enabled (it must be enabled for the processor to be operating within specification), the TCC will be active when PROCHOT# is asserted.
Error and Thermal Protection Signals on page 83). THERMTRIP# activation is independent of processor activity. The temperature at which THERMTRIP# asserts is not user configurable and is not software visible.
5.9 Intel ® Turbo Boost Technology Thermal Considerations Intel Turbo Boost Technology allows processor cores and integrated graphics cores to run faster than the baseline frequency. During a turbo event, the processor can exceed its TDP power for brief periods.
5.9.2 Package Power Control The package power control allows for customization to implement optimal turbo within platform power delivery and package thermal solution limitations.
Power_Limit_2 for up to approximately 1.5 the Turbo Time Parameter. See the appropriate processor Thermal Mechanical Design Guidelines for more information (see Related Documents section).
6.0 Signal Description This chapter describes the processor signals. They are arranged in functional groups according to their associated interface or category.
Signal Name Description Direction / Buffer Type SA_DQ[63:0] Data Bus: Channel A data signal interface to the SDRAM data bus. I/O DDR3/DDR3L SA_ECC_CB[7:0] ECC Data Lines: Data Lines for ECC Check Byte. I/O DDR3/DDR3L SA_MA[15:0] Memory Address: These signals are used to provide the multiplexed row and column address to the SDRAM.
Signal Name Description Direction / Buffer Type SB_CKE[3:0] Clock Enable: (1 per rank). These signals are used to: • Initialize the SDRAMs during power-up. • Power-down SDRAM ranks. • Place all SDRAM ranks into and out of self-refresh during STR.
6.3 Reset and Miscellaneous Signals Table 26. Reset and Miscellaneous Signals Signal Name Description Direction / Buffer Type CFG[19:0] Configuration Signals: The CFG signals have a default value of '1' if not terminated on the board. • CFG[1:0]: Reserved configuration lane.
Signal Name Description Direction / Buffer Type SM_DRAMRST# DRAM Reset: Reset signal from processor to DRAM devices. One signal common to all channels. O CMOS TESTLO_x TESTLO should be individually connected to V SS through a resistor. Note: 1. PCIe bifurcation support varies with the processor and PCH SKUs used.
6.6 Direct Media Interface (DMI) Table 29. Direct Media Interface (DMI) – Processor to PCH Serial Interface Signal Name Description Direction / Buffer Type DMI_RXP[3:0] DMI_RXN[3:0] DMI Input from PCH: Direct Media Interface receive differential pair.
Signal Name Description Direction / Buffer Type TDO Test Data Out: This signal transfers serial test data out of the processor. This signal provides the serial output needed for JTAG specification support. O Open Drain TMS Test Mode Select: This is a JTAG specification supported signal used by debug tools.
6.10 Power Sequencing Table 33. Power Sequencing Signal Name Description Direction / Buffer Type SM_DRAMPWROK SM_DRAMPWROK Processor Input : This signal connects to the PCH DRAMPWROK.
6.13 Ground and Non-Critical to Function (NCTF) Signals Table 36. Ground and Non-Critical to Function (NCTF) Signals Signal Name Description Direction / Buffer Type VSS Processor ground node GND VSS_NCTF Non-Critical to Function: These pins are for package mechanical reliability.
7.0 Electrical Specifications This chapter provides the processor electrical specifications including integrated voltage regulator (VR), V CC Voltage Identification (VID), reserved and unused signals, signal groups, Test Access Points (TAP), and DC specifications.
Table 38. VR 12.5 Voltage Identification B i t 7 B i t 6 B i t 5 B i t 4 B i t 3 B i t 2 B i t 1 B i t 0 Hex V CC 0 0 0 0 0 0 0 0 00h 0.0000 0 0 0 0 0 0 0 1 01h 0.5000 0 0 0 0 0 0 1 0 02h 0.5100 0 0 0 0 0 0 1 1 03h 0.5200 0 0 0 0 0 1 0 0 04h 0.5300 0 0 0 0 0 1 0 1 05h 0.
B i t 7 B i t 6 B i t 5 B i t 4 B i t 3 B i t 2 B i t 1 B i t 0 Hex V CC 0 1 0 0 0 0 1 0 42h 1.1500 0 1 0 0 0 0 1 1 43h 1.1600 0 1 0 0 0 1 0 0 44h 1.1700 0 1 0 0 0 1 0 1 45h 1.1800 0 1 0 0 0 1 1 0 46h 1.1900 0 1 0 0 0 1 1 1 47h 1.2000 0 1 0 0 1 0 0 0 48h 1.
B i t 7 B i t 6 B i t 5 B i t 4 B i t 3 B i t 2 B i t 1 B i t 0 Hex V CC 1 0 0 0 0 1 1 0 86h 1.8300 1 0 0 0 0 1 1 1 87h 1.8400 1 0 0 0 1 0 0 0 88h 1.8500 1 0 0 0 1 0 0 1 89h 1.8600 1 0 0 0 1 0 1 0 8Ah 1.8700 1 0 0 0 1 0 1 1 8Bh 1.8800 1 0 0 0 1 1 0 0 8Ch 1.
B i t 7 B i t 6 B i t 5 B i t 4 B i t 3 B i t 2 B i t 1 B i t 0 Hex V CC 1 1 0 0 1 0 1 0 CAh 2.5100 1 1 0 0 1 0 1 1 CBh 2.5200 1 1 0 0 1 1 0 0 CCh 2.5300 1 1 0 0 1 1 0 1 CDh 2.5400 1 1 0 0 1 1 1 0 CEh 2.5500 1 1 0 0 1 1 1 1 CFh 2.5600 1 1 0 1 0 0 0 0 D0h 2.
7.4 Reserved or Unused Signals The following are the general types of reserved (RSVD) signals and connection guidelines: • RSVD – these signals should not be connected • RSVD_TP – these signal.
Signal Group Type Signals Single ended CMOS Output SM_DRAMRST# DDR3/DDR3L Data Signals 2 Single ended DDR3/DDR3L Bi- directional SA_DQ[63:0], SB_DQ[63:0] Differential DDR3/DDR3L Bi- directional SA_DQS.
Signal Group Type Signals Other SKTOCC#, PCI Express* Graphics Differential PCI Express Input PEG_RXP[15:0], PEG_RXN[15:0] Differential PCI Express Output PEG_TXP[15:0], PEG_TXN[15:0] Single ended Ana.
7.8 Voltage and Current Specifications Table 40. Processor Core Active and Idle Mode DC Voltage and Current Specifications Symbol Parameter Min Typ Max Unit Note 1 Operational VID VID Range 1.65 2013D: 1.75 2013C: 1.75 2013B: 1.75 2013A: 1.75 1.86 V 2 Idle VID (package C6/C7) VID Range 1.
Symbol Parameter Min Typ Max Unit Note 1 P MAX 2013D PCG P MAX — — 153 W 9 P MAX 2013C PCG P MAX — — 121 W 9 P MAX 2013B PCG P MAX — — 99 W 9 P MAX 2013A PCG P MAX — — 83 W 9 Notes: 1. Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical data.
Table 42. VCCIO_OUT, VCOMP_OUT, and VCCIO_TERM Symbol Parameter Typ Max Units Notes VCCIO_OUT Termination Voltage 1.0 — V ICCIO_OUT Maximum External Load — 300 mA VCOMP_OUT Termination Voltage 1.0 — V 1 VCCIO_TERM Termination Voltage 1.0 — V 2 Notes: 1.
Symbol Parameter Min Typ Max Units Notes 1 R ON_DN(CTL) DDR3/DDR3L Control Buffer pull-down Resistance 19 25 31 Ω 5, 11, 13 R ON_UP(RST) DDR3/DDR3L Reset Buffer pull-up Resistance 40 80 130 Ω — R ON_DN(RST) DDR3/DDR3L Reset Buffer pull-up Resistance 40 80 130 Ω — I LI Input Leakage Current (DQ, CK) 0 V 0.
Table 45. Embedded DisplayPort* (eDP) Group DC Specifications Symbol Parameter Min Typ Max Units V IL HPD Input Low Voltage 0.02 — 0.21 V V IH HPD Input High Voltage 0.84 — 1.05 V V OL eDP_DISP_UTIL Output Low Voltage 0.1*V CC — — V V OH eDP_DISP_UTIL Output High Voltage 0.
Symbol Parameter Min Max Units Notes 1 V IH Input High Voltage (other GTL) V CCIO_TERM * 0.72 — V 2, 4 R ON Buffer on Resistance (CFG/BPM) 16 24 Ω — R ON Buffer on Resistance (other GTL) 12 28 Ω — I LI Input Leakage Current — ±150 μA 3 Notes: 1.
Symbol Definition and Conditions Min Max Units Notes 1 V n Negative-Edge Threshold Voltage 0.275 * V CCIO_TERM 0.500 * V CCIO_TERM V — V p Positive-Edge Threshold Voltage 0.550 * V CCIO_TERM 0.725 * V CCIO_TERM V — C bus Bus Capacitance per Node N/A 10 pF — C pad Pad Capacitance 0.
8.0 Package Mechanical Specifications The processor is packaged in a Flip-Chip Land Grid Array package that interfaces with the motherboard using the LGA1150 socket.
mechanical system or component testing should not exceed the maximum limits. The processor package substrate should not be used as a mechanical reference or load- bearing surface for thermal and mechanical solution.
Table 52. Processor Materials Component Material Integrated Heat Spreader (IHS) Nickel Plated Copper Substrate Fiber Reinforced Resin Substrate Lands Gold Plated Copper 8.7 Processor Markings The following figure shows the top-side markings on the processor.
Figure 22. Processor Package Land Coordinates 8.9 Processor Storage Specifications The following table includes a list of the specifications for device storage in terms of maximum and minimum temperatures and relative humidity. These conditions should not be exceeded in storage or transportation.
Parameter Description Minimum Maximum Notes RH sustained storage The maximum device storage relative humidity for a sustained period of time. 60% @ 24 °C 5, 6 TIME sustained storage A prolonged or extended period of time; typically associated with customer shelf life.
9.0 Processor Ball and Signal Information This chapter provides processor ball information. The following table provides the ball list by signal name. Table 54.
Signal Name Ball # FDI0_TX0N1 C13 FDI0_TX0P0 A14 FDI0_TX0P1 B13 IST_TRIGGER C39 IVR_ERROR R36 PECI N37 PEG_RCOMP P3 PEG_RXN0 F15 PEG_RXN1 E14 PEG_RXN10 F6 PEG_RXN11 G5 PEG_RXN12 H6 PEG_RXN13 J5 PEG_RX.
Signal Name Ball # RSVD M38 RSVD N35 RSVD P33 RSVD R33 RSVD R34 RSVD T34 RSVD T35 RSVD T8 RSVD U8 RSVD W8 RSVD Y8 RSVD_TP A4 RSVD_TP AV1 RSVD_TP AW2 RSVD_TP B3 RSVD_TP C2 RSVD_TP D1 RSVD_TP H16 RSVD_T.
Signal Name Ball # SA_DQ6 AF37 SA_DQ60 AG2 SA_DQ61 AG3 SA_DQ62 AE2 SA_DQ63 AE1 SA_DQ7 AF40 SA_DQ8 AH40 SA_DQ9 AH39 SA_DQSN0 AE38 SA_DQSN1 AJ38 SA_DQSN2 AN38 SA_DQSN3 AU36 SA_DQSN4 AW5 SA_DQSN5 AP2 SA_.
Signal Name Ball # SB_DQ36 AR13 SB_DQ37 AP13 SB_DQ38 AM13 SB_DQ39 AM12 SB_DQ4 AD34 SB_DQ40 AR9 SB_DQ41 AP9 SB_DQ42 AR6 SB_DQ43 AP6 SB_DQ44 AR10 SB_DQ45 AP10 SB_DQ46 AR7 SB_DQ47 AP7 SB_DQ48 AM9 SB_DQ49.
Signal Name Ball # VCC B25 VCC B27 VCC B29 VCC B31 VCC B33 VCC B35 VCC C24 VCC C25 VCC C26 VCC C27 VCC C28 VCC C29 VCC C30 VCC C31 VCC C32 VCC C33 VCC C34 VCC C35 VCC D25 VCC D27 VCC D29 VCC D31 VCC D33 VCC D35 VCC E24 VCC E25 VCC E26 VCC E27 VCC E28 VCC E29 VCC E30 VCC E31 VCC E32 VCC E33 VCC E34 VCC E35 continued.
Signal Name Ball # VCC M13 VCC M15 VCC M17 VCC M19 VCC M21 VCC M23 VCC M25 VCC M27 VCC M29 VCC M33 VCC M8 VCC P8 VCC_SENSE E40 VCCIO_OUT L40 VCOMP_OUT P4 VDDQ AJ12 VDDQ AJ13 VDDQ AJ15 VDDQ AJ17 VDDQ A.
Signal Name Ball # VSS AH36 VSS AH4 VSS AH5 VSS AH8 VSS AJ11 VSS AJ14 VSS AJ16 VSS AJ18 VSS AJ19 VSS AJ22 VSS AJ23 VSS AJ26 VSS AJ27 VSS AJ30 VSS AJ31 VSS AJ32 VSS AJ33 VSS AJ34 VSS AJ35 VSS AJ36 VSS AJ37 VSS AJ40 VSS AJ5 VSS AJ8 VSS AK1 VSS AK10 VSS AK11 VSS AK12 VSS AK13 VSS AK14 VSS AK18 VSS AK19 VSS AK24 VSS AK25 VSS AK26 VSS AK27 continued.
Signal Name Ball # VSS AR14 VSS AR16 VSS AR17 VSS AR18 VSS AR19 VSS AR20 VSS AR21 VSS AR22 VSS AR23 VSS AR24 VSS AR27 VSS AR30 VSS AR31 VSS AR32 VSS AR33 VSS AR34 VSS AR35 VSS AR36 VSS AR37 VSS AR38 VSS AR39 VSS AR40 VSS AR5 VSS AT1 VSS AT10 VSS AT11 VSS AT12 VSS AT13 VSS AT14 VSS AT15 VSS AT16 VSS AT2 VSS AT24 VSS AT25 VSS AT26 VSS AT27 continued.
Signal Name Ball # VSS D24 VSS D26 VSS D28 VSS D30 VSS D32 VSS D34 VSS D36 VSS D37 VSS D5 VSS D6 VSS D7 VSS D9 VSS E10 VSS E18 VSS E20 VSS E22 VSS E23 VSS E3 VSS E36 VSS E38 VSS E6 VSS E7 VSS E8 VSS F1 VSS F12 VSS F14 VSS F16 VSS F19 VSS F21 VSS F22 VSS F24 VSS F26 VSS F28 VSS F30 VSS F32 VSS F34 continued.
Signal Name Ball # VSS L36 VSS L38 VSS L6 VSS L7 VSS L8 VSS L9 VSS M1 VSS M12 VSS M14 VSS M16 VSS M18 VSS M20 VSS M22 VSS M24 VSS M26 VSS M28 VSS M30 VSS M32 VSS M34 VSS M35 VSS M37 VSS M4 VSS M40 VSS M5 VSS M6 VSS M7 VSS M9 VSS N1 VSS N2 VSS N3 VSS N33 VSS N34 VSS N39 VSS N4 VSS N6 VSS N7 continued.
デバイスIntel BX80646E31230V3の購入後に（又は購入する前であっても）重要なポイントは、説明書をよく読むことです。その単純な理由はいくつかあります：
Intel BX80646E31230V3をまだ購入していないなら、この製品の基本情報を理解する良い機会です。まずは上にある説明書の最初のページをご覧ください。そこにはIntel BX80646E31230V3の技術情報の概要が記載されているはずです。デバイスがあなたのニーズを満たすかどうかは、ここで確認しましょう。Intel BX80646E31230V3の取扱説明書の次のページをよく読むことにより、製品の全機能やその取り扱いに関する情報を知ることができます。Intel BX80646E31230V3で得られた情報は、きっとあなたの購入の決断を手助けしてくれることでしょう。
Intel BX80646E31230V3を既にお持ちだが、まだ読んでいない場合は、上記の理由によりそれを行うべきです。そうすることにより機能を適切に使用しているか、又はIntel BX80646E31230V3の不適切な取り扱いによりその寿命を短くする危険を犯していないかどうかを知ることができます。
ですが、ユーザガイドが果たす重要な役割の一つは、Intel BX80646E31230V3に関する問題の解決を支援することです。そこにはほとんどの場合、トラブルシューティング、すなわちIntel BX80646E31230V3デバイスで最もよく起こりうる故障・不良とそれらの対処法についてのアドバイスを見つけることができるはずです。たとえ問題を解決できなかった場合でも、説明書にはカスタマー・サービスセンター又は最寄りのサービスセンターへの問い合わせ先等、次の対処法についての指示があるはずです。
