Analog DevicesメーカーADSP-21020の使用説明書/サービス説明書
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FUNCTIONAL BLOCK DIAGRAM EXTERNAL ADDRESS BUSES PROGRAM SEQUENCER EXTERNAL DATA BUSES DATA ADDRESS GENERATORS DAG 1 DAG 2 PROGRAM MEMORY ADDRESS PROGRAM MEMORY DATA DATA MEMORY DATA DATA MEMORY ADDRESS INSTRUCTION CACHE ARITHMETIC UNITS SHIFTER MULTIPLIER ALU REGISTER FILE TIMER JTAG TEST & EMULATION REV.
ADSP-21020 REV. C –2– • Instruction Cache The ADSP-21020 includes a high performance instruction cache that enables three-bus operation for fetching an instruction and two data values. The cache is selective—only the instructions whose fetches conflict with program memory data accesses are cached.
ADSP-21020 REV. C –3– the standard IEEE format, whereas the 40-bit IEEE extended- precision format has eight additional LSBs of mantissa for greater accuracy. The multiplier performs floating-point and fixed-point multiplication as well as fixed-point multiply/add and multiply/ subtract operations.
ADSP-21020 REV. C –4– in a specified register, either before (premodify) or after (postmodify) the access. To implement automatic modulo addressing for circular buffers, the ADSP-21020 provides buffer length registers that can be associated with each pointer.
ADSP-21020 REV. C –5– 4 1 × CLOCK CLKIN PMA PMD DMACK DMA DMD ADSP-21010 24 48 32 32 2 PMACK 4 DMPAGE PMPAGE FLAG3-0 JTAG 5 4 RCOMP TIMEXP ADDR DATA PROGRAM MEMORY SELECTS OE WE PMS1-0 PMRD PMWR DMRD DMWR DMTS DATA MEMORY ACK PERIPHERALS ADDR DATA ADDR DATA SELECTS SELECTS OE WE OE WE BR BG RESET IRQ3-0 PMTS DMS3-0 Figure 2.
ADSP-21020 REV. C –6– Pin Name Type Function DMPAGE O Data Memory Page Boundary. The ADSP- 21020 asserts this pin to signal that a data memory page boundary has been crossed. Memory pages must be defined in the memory control registers. DMTS I/S Data Memory Three-State Control.
ADSP-21020 REV. C –7– COMPUTE AND MOVE OR MODIFY INSTRUCTIONS 1. compute , | DM(Ia, Mb) = dreg1 | , | PM(Ic, Md) = dreg2 | ; | dreg1 = DM(Ia, Mb) || dreg2 = PM(Ic, Md) | 2. IF condition compute; 3a. IF condition compute , | DM(Ia, Mb) | = ureg ; | PM(Ic, Md) | 3b.
ADSP-21020 REV. C –8– Table II. Condition and Termination Codes Name Description eq ALU equal to zero ne ALU not equal to zero ge ALU greater than or equal to zero lt ALU less than zero le ALU les.
ADSP-21020 REV. C –9– Table III. Universal Registers Name Function Register File R15–R0 Register file locations Program Sequencer PC* Program counter; address of instruction cur- rently executin.
ADSP-21020 REV. C –10– Table V. Multiplier Compute Operations Rn = Rx * Ry ( SS F ) Fn = Fx * Fy MRF = Rx * Ry ( UUI MRB = Rx * Ry ( UU FR Rn = MRF + Rx * Ry ( SSF ) Rn = MRF – Rx * Ry ( SSF ) R.
ADSP-21020 REV. C –11– Table Vll. Multifunction Compute Operations Fixed-Point Rm=R3-0 * R7-4 (SSFR), Ra=R11-8 + R15-12 Rm=R3-0 * R7-4 (SSFR), Ra=R11-8 – R15-12 Rm=R3-0 * R7-4 (SSFR), Ra=(R11-8 .
RECOMMENDED OPERA TING CONDITIONS K Grade B Grade T Grade Parameter Min Max Min Max Min Max Unit V DD Supply Voltage 4.50 5.50 4.50 5.50 4.50 5.50 V T AMB Ambient Operating Temperature 0 +70 –40 +85 –55 +125 ° C Refer to Environmental Conditions for information on thermal specifications.
ADSP-21020 REV. C –13– TIMING PARAMETERS General Notes See Figure 15 on page 24 for voltage reference levels. Use the exact timing information given.
ADSP-21020 REV. C –14– Interrupts K/B/T Grade K/B/T Grade B/T Grade K Grade 20 MHz 25 MHz 30 MHz 33.3 MHz Frequency Dependency* Parameter Min Max Min Max Min Max Min Max Min Max Unit Timing Requir.
ADSP-21020 REV. C –15– Flags K/B/T Grade K/B/T Grade B/T Grade K Grade 20 MHz 25 MHz 30 MHz 33.3 MHz Frequency Dependency* Parameter Min Max Min Max Min Max Min Max Min Max Unit Timing Requirement.
ADSP-21020 REV. C –16– Bus Request/Bus Grant K/B/T Grade K/B/T Grade B/T Grade K Grade 20 MHz 25 MHz 30 MHz 33.3 MHz Frequency Dependency* Parameter Min Max Min Max Min Max Min Max Min Max Unit Ti.
ADSP-21020 REV. C –17– External Memory Three-State Control K/B/T Grade K/B/T Grade B/T Grade K Grade 20 MHz 25 MHz 30 MHz 33.3 MHz Frequency Dependency* Parameter Min Max Min Max Min Max Min Max M.
ADSP-21020 REV. C –18– Memory Read K/B/T Grade K/B/T Grade B/T Grade K Grade 20 MHz 25 MHz 30 MHz 33.3 MHz Frequency Dependence* Parameter Min Max Min Max Min Max Min Max Min Max Unit Timing Requi.
ADSP-21020 REV. C –19– CLKIN DATA DMACK, PMACK ADDRESS, SELECT DMPAGE, PMPAGE t DARL t DAP t DAAK t DCKRL t DRAK t SAK t HAK t DAD t DRLD t RWR t HDRH t RW t HDA DMWR, PMWR DMRD, PMRD Figure 10.
ADSP-21020 REV. C –20– Memory Write K/B/T Grade K/B/T Grade B/T Grade K Grade 20 MHz 25 MHz 30 MHz 33.3 MHz Frequency Dependency* Parameter Min Max Min Max Min Max Min Max Min Max Unit Timing Requ.
ADSP-21020 REV. C –21– CLKIN DATA DMACK, PMACK ADDRESS, SELECT DMPAGE, PMPAGE t DAWL t DAP t DAAK t DCKWL t DWAK t SAK t HAK t WDE t DWHA t WWR t DDWR t DDWH t WW t DAWH t HDWH DMWR, PMWR DMRD, PMRD Figure 11.
ADSP-21020 REV. C –22– IEEE 1149.1 Test Access Port K/B/T Grade K/B/T Grade B/T Grade K Grade 20 MHz 25 MHz 30 MHz 33.3 MHz Frequency Dependency* Parameter Min Max Min Max Min Max Min Max Min Max .
ADSP-21020 REV. C –23– TCK TMS,TDI TDO SYSTEM INPUTS SYSTEM OUTPUTS t STAP t HTAP t DTDO t SSYS t HSYS t DSYS t TCK Figure 12. IEEE 1149.1 Test Access Port.
ADSP-21020 REV. C –24– TEST CONDITIONS Output Disable Time Output pins are considered to be disabled when they stop driving, go into a high-impedance state, and start to decay from their output high or low voltage. The time for the voltage on the bus to decay by ∆ V is dependent on the capacitive load, C L , and the load current, I L .
ADSP-21020 REV. C –25– Capacitive Loading Output delays are based on standard capacitive loads: 100 pF on address, select, page and strobe pins, and 50 pF on all others (see Figure 14). For different loads, these timing parameters should be derated.
ADSP-21020 REV. C –26– ENVIRONMENTAL CONDITIONS The ADSP-21020 is available in a Ceramic Pin Grid Array (CPGA). The package uses a cavity-down configuration which gives it favorable thermal characteristics. The top surface of the package contains a raised copper slug from which much of the die heat is dissipated.
ADSP-21020 REV. C –27– All GND pins should have a low impedance path to ground. A ground plane is required in ADSP-21020 systems to reduce this impedance, minimizing noise. The EVDD and IVDD pins should be bypassed to the ground plane using approximately 14 high-frequency capacitors (0.
ADSP-21020 REV. C –28– TCK PMA21 PMPAGE TRST RCOMP DMACK TDO DMTS PMWR PMD47 PMD46 PMD44 PMD42 PMD41 PMD38 DMD22 EVDD DMD24 DMD25 DMD26 DMD23 DMD27 DMD28 DMD33 DMD29 DMD35 DMD36 DMD39 DMD34 NC DMS.
ADSP-21020 REV. C –29– DMD7 DMD8 DMA14 DMA13 DMD12 DMD14 DMD18 DMD21 DMD22 DMD26 DMD32 DMD33 DMD37 DMD39 DMA21 DMA17 DMA16 EVDD DMD23 DMD29 DMD34 DMA22 BG BR BOTTOM VIEW (PINS UP) PMD31 PMD35 PMD3.
ADSP-21020 REV. C –30– PGA PIN PGA PIN PGA PIN PGA PIN LOCATION NAME LOCATION NAME LOCATION NAME LOCATION NAME G16 DMA0 B5 DMD25 K1 PMD9 L16 TIMEXP G17 DMA1 B6 DMD26 L3 PMD10 U12 RCOMP F18 DMA2 D6.
ADSP-21020 REV. C –31– OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 223-Pin Ceramic Pin Grid Array D D A A 1 L 3 b 1 φ e h b φ j 1 j 2 AB CD EFGH J KL M NP RS T U 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 TOP VIEW e 1 e 1 INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A 0.
ADSP-21020 REV. C –32– C1601c–5–8/94 PRINTED IN U.S.A. ORDERING GUIDE Ambient Temperature Instruction Cycle Time Part Number* Range Rate (MHz) (ns) Package ADSP-21020KG-80 0 ° C to +70 ° C 20 50 223-Lead Ceramic Pin Grid Array ADSP-21020KG-100 0 ° C to +70 ° C 25 40 223-Lead Ceramic Pin Grid Array ADSP-21020KG-133 0 ° C to +70 ° C 33.
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Analog Devices ADSP-21020を既にお持ちだが、まだ読んでいない場合は、上記の理由によりそれを行うべきです。そうすることにより機能を適切に使用しているか、又はAnalog Devices ADSP-21020の不適切な取り扱いによりその寿命を短くする危険を犯していないかどうかを知ることができます。
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