LSIメーカー53C875Aの使用説明書/サービス説明書
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® S14047 LSI53C875A PCI to U ltra SCSI Controller TECHNIC AL MANU AL Dece mber 200 0 Ve r s i o n 2 . 0.
ii This doc ument co ntains prop rietary inf ormation o f LSI Logic Corpor ation. The inf ormation c ontain ed herei n is not to b e used b y or di sclo sed to third par ties withou t the e xpre ss written pe r miss ion of a n officer of L SI Log ic Corporatio n.
Pref ace iii Preface This book is th e pri mar y re f er ence an d technical manual for the LSI53C 875A PCI to Ultra SCSI Co ntrolle r . It co ntains a com plete functiona l desc rip tion f or th e prod uct and als o incl udes comp lete physical and elec tric al specifi catio ns.
iv Preface • Chap ter 6, Electr ical Sp ecifi cation s contains t he e lectr ica l character is tics and A C timin g diagrams. • Appen dix A, Regi ster Summ ary i s a r egiste r su mmar y .
Pref ace v PCI Spe cial Interest Gr oup 2575 N.E . Kather ine Hillsbo ro , OR 97214 (800) 433- 5177; (5 03) 693-623 2 (Inter nati onal); F AX (503) 69 3-8344 Con ventions Used in This Manual The word asser t m eans t o dri v e a sig nal tr ue or active .
vi Preface.
Contents vii Contents Chapter 1 General Description 1.1 New F e atures i n the LSI53 C875A 1-3 1.2 Benefits of Ultra S CSI 1-3 1.3 T olerANT ® Te c h n o l o g y 1 - 4 1.4 LSI53C 875A Bene fits S ummar y 1-4 1.4.1 SCSI P erf or m ance 1-5 1.4.2 PCI P erfor mance 1-6 1.
viii Cont ents 2.2.11 P ar ity Optio ns 2-24 2.2.12 DMA FIFO 2-27 2.2.13 SCSI B us Int erf ace 2-3 2 2.2.14 Select/R esele ct Dur ing S elect ion/Resel ection 2-33 2.2.15 Synchr onous Opera tion 2-34 2.2.16 Interr upt Ha ndling 2-37 2.2.17 Chained B lock Mov es 2-44 2.
Contents ix Chapter 4 Registers 4.1 PC I Confi gur atio n Regis ter s 4-1 4. 2 SC SI Regis ters 4-18 4.3 64-Bit SCRIP TS Selec tors 4-99 4.4 Phase Mi smatch Jump Regist ers 4-10 3 Chapter 5 SCSI SCRIPTS Instruction Set 5.1 Low Lev el Reg ister In terface Mode 5-1 5.
xC o n t e n t s 6.3 A C Character istic s 6-9 6.4 PCI and Exter nal Mem or y Interface Timing Diagrams 6 -11 6.4.1 T arget Timing 6-13 6. 4.2 In iti ato r Timi ng 6-19 6.
Contents xi 6. 9 PCI Co nfig ura tio n Regis ter Re ad 6- 13 6.10 PCI Con figuration Re giste r Wri te 6-14 6.11 32-Bit Op erating R egister /SCRIPTS RAM Rea d 6-15 6.12 64-Bit A ddre ss Operatin g Re gister/S CRIPTS R AM Read 6-16 6.13 32-Bit Op erating R egister /SCRIPTS RAM W rite 6-17 6.
xii Co ntent s B.3 128 Kbytes, 256 Kbytes, 512 Kbytes, or 1 M byte Interface with 150 ns Mem or y B-3 B.4 512 Kbyte Inter f ace with 15 0 ns Memo r y B-4 Ta b l e s 2.1 PCI Bus C ommand s and E ncoding T ypes for the LSI53C 875A 2-4 2.2 PCI Cac he Mod e Alignm ent 2-12 2.
Contents xiii 5. 2 SCSI I nf or mat ion T r ansf er Phase 5- 12 5.3 Rea d/Wr ite Instr uctions 5-24 5.4 T ransfer Control In stru ctions 5-26 5. 5 SCSI P hase Co mpa risons 5-29 6.1 Abs olu te Maxim um Stress Rat ings 6-2 6.2 Operat ing Condit ions 6-2 6.
xiv Co ntent s 6.30 Exter n al Memor y Wr ite 6-38 6.31 Nor mal/F as t Memo r y ( ≥ 1 28 Kbytes) Sing le Byte Access R ead Cycle 6-42 6.32 Nor mal/F as t Memo r y ( ≥ 1 28 Kbytes) Sing le Byte Acce ss Write Cycle 6-43 6.33 Slow Memo r y ( ≤ 128 K b ytes) Rea d Cycle 6-48 6.
LSI53C8 75A PCI to Ultra SCSI Controll er 1-1 Chapter 1 General D escri ption Chapter 1 is di vided in to the following secti ons: • Secti on 1.1, “New F eatures in the LSI 53C875A” • Section 1.2, “ Benefi ts of Ultra S CSI” • Secti on 1.
1-2 Gen eral De scription Figure 1.1 T ypical LSI53C875A Sys tem Application Figure 1 .2 T ypical LSI53C8 75A B oard Appl ication PCI Bus Interf ace Controller LSI53C875A P C It oW i d eU l t r a SCSI.
Ne w F eatu res in the LSI 53C875A 1-3 1.1 Ne w Features in the LSI53 C875A The LSI53C87 5A is a dro p-in replac ement f or the LSI53C875 PCI to Ultra SCSI C ontrolle r , with these addi tional be nefits: • Suppo r ts 32- bit PCI Int erf ace with 64-bi t addres sing .
1-4 Gen eral De scription synchr onous ne gotiation s f or Ultra SCSI rates and to enable the c loc k quadr upler . Chapte r 2, “F unctiona l De scri ption,” contains m ore inf or m ation on U ltra SCSI desi gn.
LSI53C8 75A Bene fits Summary 1-5 • Ease of Use • Fle xibilit y • Relia bility • T estabi lity 1.4. 1 SCSI P erf ormance T o improve SCSI perfor mance, the LSI53C8 75A: • Has integrated SE transc eivers. • Bursts up to 512 bytes ac ross th e PCI bus through i ts 944 byte FIFO.
1-6 Gen eral De scription • Suppo r ts a dditional ar ithme tic ca pability with the Exp anded Reg ister Mo v e instructi on. 1.4.2 PCI P erf ormance T o improve PCI perform ance, the LSI53 C875A: • Compli es with P CI 2.2 spec ific ation. • Suppo r ts 32- bit 33 MHz PCI in terface with 64-bit address ing.
LSI53C8 75A Bene fits Summary 1-7 • Up to on e megabyte of add -in memo r y suppor t for BIOS and SCR IPTS storag e. • Redu ced SC SI de v elop ment e ff or t. • Comp iler- compa tible with existin g LSI53 C7X X and L SI53C8X X f amily SC RIPT S.
1-8 Gen eral De scription • SCSI clock quad rupl er bits enable Ultra SCSI transfer r ates with a 20 or 40 MHz SCSI cl oc k input. • Selec table IRQ pin disable bit. • Abil ity to route sy stem cl ock to SCSI clock. • Compatible with 3.3 V and 5 V PCI.
LSI53C8 75A PCI to Ultra SCSI Controll er 2-1 Chapter 2 Funct ional Desc ription Chapter 2 is di vided in to the following secti ons: • Secti on 2.1, “P CI Func tional Descr iption ” • Secti on 2.2, “SCSI Functiona l Desc rip tion” • Sec tion 2.
2-2 Funct ion al De scr ipt ion Figure 2.1 LSI53C875A Bl oc k Dia gram 2.1 PCI Functional D escription The LS I53C 875 A impl ement s a PCI-to -Wid e Ult ra SCSI co ntr olle r . 2.1. 1 PCI Addres sing There a re three physical PCI- define d addres s space s: • PCI Con figuration s pace.
PCI Functio nal Description 2-3 2.1.1.1 Configuration Space The host proces sor uses the PCI config uration sp ace to initialize the LSI53C 875A through a defi ned set of configu r atio n space regi sters. The Config uration reg isters ar e acces sible only by sys tem BIOS duri ng PCI confi guration c ycles.
2-4 Funct ion al De scr ipt ion 2.1.2.1 Interrupt Ac knowledge Command The LSI5 3C875A does not r espond t o this command a s a slav e and it ne v er gen erates this comm and as a master . 2.1.2.2 Special C yc le Comma nd The LSI5 3C875A does not r espond t o this command a s a slav e and it ne v er gen erates this comm and as a master .
PCI Functio nal Description 2-5 2.1.2.3 I/O Read Command The I/O Read co mmand re ads data fr om an agen t mappe d in I/O address s pace. All 32 addre ss bits are dec oded. 2.1.2.4 I/O Write Comma nd The I/O Wr ite comm and wr ites dat a to an agent ma pped in I/O addr ess spac e.
2-6 Funct ion al De scr ipt ion 2.1.2.10 Memor y Read Mult iple Command This c ommand is ide ntica l to the Me mor y Re ad comman d e xcept that i t additi onally ind icates that the mas ter ma y intend to f etch more than one cach e lin e before disc onnect ing.
PCI Functio nal Description 2-7 line. This com mand i s intende d for use wit h bulk sequentia l data tran sf ers where the me mor y s ystem and th e request ing master might g ain some performa nce ad v antage by read ing to a ca che line b oundar y rather tha n a single memo r y cycle.
2-8 Funct ion al De scr ipt ion 2.1.2.13 Memor y Write and In validate Command The Memo r y Wr ite a nd Inv alidate c omman d is iden tical to t he Memo r y Write co mma nd, e xcept t hat it add iti o.
PCI Functio nal Description 2-9 After each data transfer , the chip re-ev alu ates the burst size based on the amount of rem aining dat a to transf er and again selec ts the highe st possible multipl e of the cac he line si ze , and n o larger tha n the DM A Mode (DMO DE) burst si ze .
2-10 Func tional Desc ription software e nabled or d isabled to allow the us er fu ll flexibility in usin g these comm ands. 2.1.3.1 Enabling Cache Mo de In orde r to enable the cache l ogic to i ssue.
PCI Functio nal Description 2-11 • T o issue Memor y Read M ultiple c omman ds , the R ead Mul tiple enable bit i n the DMA M ode (DMODE) regi ster mu st be set.
2-12 Func tional Desc ription • Multiple Me mor y Wr ite and Inv alidate s. • A singl e data res idual Me mor y W rit e to co mplete t he transf er .
PCI Functio nal Description 2-13 2. 1.3. 5 Exa mpl es: MR = M emor y Rea d, MRL = Me mor y R ead Line, MRM = M emor y Read Multiple, MW = Mem or y Wr ite, MWI = Memor y W rite and Inv alidate.
2-14 Func tional Desc ription Re ad Exam ple 3 – Burst = 16 Dwords, Cache Line Size = 8 Dwords: Write E xample 1 – B u r s t=4D w o r d s ,C a c h e L i n eS i z e=4D w o r d s : Ct oE : MRM (21 b.
PCI Functio nal Description 2-15 Write E xample 2 – B u r s t=8D w o r d s ,C a c h e L i n eS i z e=4D w o r d s : Dt oF : MW (1 5 bytes) MWI (16 byt es) MW (1 byte) At oH : MW ( 15 bytes ) MWI (16.
2-16 Func tional Desc ription Write E xample 3 – Burst = 16 Dwords, Cache Line Size = 8 Dwords: 2.1.3.6 Memor y-to-Me mory M o ves Memor y -to-Me mor y Mov es a lso sup por t P CI cache commands, as descr ibed a bov e, wit h one li mitation .
SCSI Functio nal Description 2-17 acce ssed as a regi ster- orie nted device . Er ror recov er y a nd/or diag nostic procedu res use the abili ty to sam ple and/or ass er t any signal on the SCSI bus. In supp or t o f SCSI lo opback diagn ostics, the SCS I core may perform a self-sel ection an d operate as both an initiator and a tar get.
2-18 Func tional Desc ription The Pha se Mi smatch Jump l ogic powers up disabled a nd must be enabled by setting the Pha se Mism atch Jump Enable bit (ENP MJ , bit 7 in the Chip Con trol 0 (CCNTL0) register).
SCSI Functio nal Description 2-19 2.2.3 64- Bit Addre ssing i n SCRIPT S The LSI5 3C875A has a 32- bit PCI in terface which provide s 64-bi t address capa bility in th e init iator mod e. D ACs can be generated for all SCRIP TS operation s. There are s ix sele ctor regis ters wh ich hold the upper Dword of a 64-b it address.
2-20 Func tional Desc ription 2.2.5 Des igning an Ultra SCSI Syst em Since U ltra SCSI is ba sed on existing SCSI stan dards, it can use e xi sting dri v er pro grams as lon g as the s oftware is able to n egotiat e f or Ult r a SCS I synchr onous transfer rates.
SCSI Functio nal Description 2-21 S t e p3 . H a l tt h eS C S Ic l o c k b ys e t t i n gt h eH a l tS C S IC l o c kb i t ( SCSI T est Three (STEST3) ,b i t5 ) . Step 4. Se t the clock c onv ers ion f a ctor using the SCF and CC F fiel ds in the SCSI Co ntrol Three ( SCNTL3) register .
2-22 Func tional Desc ription • On ev e r y Store instr ucti on. The S tore ins tr uction m a y also be use d to place modifi ed code di rectly into m emor y . T o av oi d inad v e r t ently flushin g the pr ef etch unit conten ts use the No Flus h optio n f or all Store operati ons that do not modify code within the next 8 Dwords.
SCSI Functio nal Description 2-23 Load an d Store i nstruc tions, refer to Chapter 5, “SCSI S CRIPTS Instr uction S et.” 2.2.9 J T A G Boundary Scan T esting The LSI5 3C875A include s suppor t for JT A G bo undar y sc an test ing in acco rdance wi th the IEEE 1 149.
2-24 Func tional Desc ription 2.2.11 P arity Opt ions The LSI5 3C875A impleme nts a fl e xible par ity sche me that a llows contr ol of the pari ty sense, allows parity che c king to be tur ned on or o ff , an d has the ability to deliberately sen d a b yte wi th bad par ity ov er the SCSI bus to test par ity error recov er y p roce dures.
SCSI Functio nal Description 2-25 T able 2.3 Bits Used f or Parity Control and Gen eration Bit Name Locatio n Description Asser t SA TN/ on P ar ity Errors SCSI Control Zer o (SCNTL0) ,B i t1 C au ses th e LS I53C 875 A to aut omat ical ly as ser t S A TN / when it detects a SCSI parity error while ope ratin g as an initia tor .
2-26 Func tional Desc ription T ab le 2.4 SCSI P a rity Contr ol EPC 1 1. EPC = Ena ble P ar ity Ch ecking (bi t 3 SCSI C ontrol Zero (SCNTL0) ). ASEP 2 2. ASEP = Assert SCSI Even P arity (bit 2 SCSI C ontr ol O ne (S CNT L1) ). Descrip tion 0 0 Does n ot che ck f or parity errors .
SCSI Functio nal Description 2-27 Figure 2.2 P arity Checki ng/Generation 2.2. 12 DMA F IFO The DMA FIF O is 8 bytes wid e by 118 transfers deep. The DMA FIFO is illu strated i n Fi gure 2.3 . Th e def aul t DMA FI FO size is 11 2 bytes to assu re compa tibil ity wi th olde r produ cts in the LSI53 C8XX family .
2-28 Func tional Desc ription Figure 2.3 DMA F IFO S ections The LSI5 3C875A aut omatical ly suppo r ts misa ligned DMA tran sf ers. A 944-byte FIFO all ows the LSI53C 875A to s uppor t 2, 4, 8, 16, 32, 6 4, or 128 Dword bursts across t he PCI bus interf ace.
SCSI Functio nal Description 2-29 Figure 2.4 LSI53C87 5A Host Interface SCS I Data P at hs The following steps deter mine if any bytes remain i n the data p ath when the chip halts an operation : Asynch ro nous SCSI Send – Step 1.
2-30 Func tional Desc ription bits of the DBC r egister fr om the 10-bi t v alue of the DMA F IFO Byte Offset Cou nter , whi ch consists of bi ts [1:0] in the CTEST 5 registe r and bi ts [7:0] of th e DMA FI FO reg ister . A ND the res ult with 0x 3FF for a b yte c ount bet ween zero and 94 4.
SCSI Functio nal Description 2-31 then the lea st significa nt b yte or the mos t significan t byte in the SODR register i s full, res pectively . Asynchr onous SCSI Receive – Step 1.
2-32 Func tional Desc ription AND the r esult with 0x 3FF f or a byte count be tween zero and 944. Ste p 2. Re ad th e SCSI Status One (S ST A T1) regist er and examine bits [7:4], th e binar y r eprese ntation of the number of valid b y tes in the SCSI FIFO , to deter m ine if any b yte s are left in the SCSI FIFO .
SCSI Functio nal Description 2-33 Figure 2.5 Regulated T e rmination f or Ultra SCSI 2.2. 14 Select /Resele ct During Sel ection/Re selec tion In multit hreaded S CSI I/O environm ents, it is no t unco mmon to be sele cted or resel ected while tr ying to perfor m selecti on/res electio n.
2-34 Func tional Desc ription situa tion may occur whe n a SCS I control ler (op erating in the initia tor mode ) tries to sele ct a tar get and is r esele cted b y anothe r . The Sele ct SCRIPT S ins truc tion ha s an alt er nate ad dress to w hich the SCR IPTS w ill jump w hen thi s situati on occur s.
SCSI Functio nal Description 2-35 Figure 2.6 Determining the Sync hron ous T ransfer Rate SCLK Clock Quadrup ler QCLK SCF Di vi der CCF Divider Synchronous Divider Asynchronous SCSI Logic Divide b y 4 SCF2 SCF1 SCF0 SCF Divisor 00 1 1 01 0 1 .
2-36 Func tional Desc ription 2.2.15.2 SCSI Control Thr ee (SCNTL3) Regi ster , Bits [6: 4] (SCF[2 :0]) The SCF[2: 0] bits s elect the factor by which the freque ncy of S CLK is divided before being p resented to the sy nchronou s SCSI c ontrol logi c.
SCSI Functio nal Description 2-37 • Ultra SCSI Enab l e bit, SCSI Control Thr ee (SCNTL 3) register bit 7. Settin g this bit enables Ultra SCSI sync hronous transfers in systems that u se the in ternal SCSI cl oc k quadrupl er . • T oler ANT Enable bit , SCSI T est Thre e (STEST 3) r egist er bit 7.
2-38 Func tional Desc ription polle d when polled int errupts ar e used. It is also the first regi ster that shoul d be read after the I RQ/ pi n is ass er te d in ass ociation with a hardware in terrupt. The IN TF (In terr upt-on-the- Fly) bi t should b e the firs t interr upt ser viced.
SCSI Functio nal Description 2-39 condi tions ca used the DMA -typ e interr upt, and c lears t hat DMA inte rru pt condi tion. Bi t 7 in D ST A T , DFE , is pure ly a s tatus bit ; it wi ll not generate an interr upt under any circum stances a nd will not be clear ed when rea d.
2-40 Func tional Desc ription Pur po se Time r Expire d (GEN), an d Handsha k e- to-Handsh ake Timer Expir ed (HTH) inter rup ts are no nf atal. When o perating in the T ar get mode, CMP , SEL, RSL, T arget mode: SA TN/ act ive (M/A) , GEN, and HTH ar e nonf atal.
SCSI Functio nal Description 2-41 Interr upts c an be disa b led by setting SYNC_IR QD bit 0 in the Inte rru pt Status O ne (IST A T1) r egister . If an i nterr upt is a lready as ser ted and SYNC_I RQD is then set, the in terrupt wi ll remain as ser ted until ser viced.
2-42 Func tional Desc ription generates a n interr upt, th e bit c orrespond ing to the ear lier m asked nonf atal inter rupt is st ill set. A relate d situation t o interr up t stacking is wh en two interr upts oc cur simulta neously .
SCSI Functio nal Description 2-43 • If the i nstruc tion is a JUMP/ CALL W HEN/IF <p hase>, th e DMA SCR IPTS P o inter (D SP) is upd ated to t he transfer address bef ore halting. • All othe r instruc tions may halt bef o re comp letion. 2.
2-44 Func tional Desc ription 2.2. 17 Chaine d Bloc k Mo ves Since th e LSI53 C875A has the capab ility to transf er 16-bi t wide S CSI data, a unique situatio n occ urs when dealing w ith odd bytes.
SCSI Functio nal Description 2-45 Figure 2.7 Block Mo ve and Chained Block Mo ve Instructions 2.2.17.1 Wide S CSI Send B it The WS S bit is set whenev er th e SCSI control ler is sen ding data (Data-O.
2-46 Func tional Desc ription two b ytes are se nt out ac ross the bus, rega rdless of the type of Blo ck Mov e ins truc tion (nor mal or chain ed). Th e flag is automat ically cleare d when the “ma rri ed” word is sent. The flag is alter nate ly cleared through SCRIPT S or by the m icroproc esso r .
SCSI Functio nal Description 2-47 2.2.17.5 Chained Bloc k Mo ve SCRIPTS Instruction A chai ned Block Move SCRIPTS instr uction is pr imar ily use d to t ransf er cons ecutive data send or data receive b locks.
2-48 Func tional Desc ription send c ommand, th e first byte of th e data send command is ass umed t o be the high-o rder byte and is “marr ied” with th e low-order byte stored in the lower byte of the SC SI Out put Data L atch (S ODL) regi ster bef ore the two bytes are sen t across th e SCSI bus.
P arallel R OM Interfa ce 2-49 The LSI5 3C875A su ppor ts a v ar iety of sizes and sp eeds of expansio n R OM, using pull-d own resistors on the M AD[3:0] pins. The en coding o f pins MAD[3:1 ] allows the user to define how much e x ter nal memo r y is a vailable to the LSI53C8 75A.
2-50 Func tional Desc ription 2.4 Serial EE PROM Inte rface The LS I53 C875 A impl eme nts an in ter f ace th at al low s att achme nt of a ser ial E EPROM device to t he GPIO 0 and G PIO1 pi ns. There a re two modes of opera tion rela ting to the se r ial EEP R OM a nd the S ubsyst em ID and Subs ystem V en dor ID register s .
P ow er Man ageme nt 2-51 2.4.2 No Do wnload Mode When M AD7 is pu lled u p through an e xter n al resi stor , the auto matic download i s disabled and no data is autom aticall y loaded into chip registe rs at power-up.
2-52 Func tional Desc ription The LS I53 C875 A po wer s tate s sho wn in Ta b l e 2 . 8 are ind ependen tly control led through two power state bits tha t are located in the PCI Po w e r Ma nagem ent C ontr ol /St atus (P MCS R) regis ter 0x44.
P ow er Man ageme nt 2-53 2.5. 3 P ow er State D2 P ower state D2 is a lower power state than D1 . In this state the LSI53C 875A cor e is pla ced in the co ma mode.
2-54 Func tional Desc ription.
LSI53C8 75A PCI to Ultra SCSI Controll er 3-1 Chapter 3 Signal D escript ions This c hapter pres ents the LSI 53C875A pi n configu ration an d signal defini tions usin g tables and illu strations. This c hapter co ntains the f ollowin g sec tions: • Secti on 3.
3-2 Signa l Descripti ons 3.1 LSI53C875A Functional Signal Grouping Figure 3.1 present s the LSI53C87 5A si gnals by func tional group . Figure 3.1 LSI53C875A Functional S ignal Gr ouping LSI53C875A C.
Signa l Descripti ons 3-3 3.2 Signal Descriptions The Sig nal Descr ipti ons are d ivided i nto P CI Bus Interface Signal s , SCSI Bus Inte rf ace Si gnals , GPIO Sign als, ROM Fla sh an d Memo r y Int erf ace Signa ls , T est In terface Sign als ,a n d Po wer and Gr ound Sig nals .
3-4 Signa l Descripti ons 3.3 PCI Bus Interface Signal s The PCI Bus Int erf ace Signa ls sect ion conta ins tables descr ibin g the sign als for the f o llowing sig nal groups : Syst em Signals , Addres s and Data Signa ls , Inter f a ce Con trol Signal s , Arbi tration Signa ls , Error Repor ting S ignals , and Inte rru pt Signal .
PCI Bus In terf ace Sig nals 3-5 3.3. 2 Address and Data Signals Ta b l e 3 . 3 descr ibes Addr ess and Data si gnals. T able 3.3 Address and Data Signals Name PQF P B GA T ype Strength Desc ription A.
3-6 Signa l Descripti ons 3.3.3 I nterface Control Signals Ta b l e 3 . 4 descr ibes th e In terf ace Control s ignals. T able 3.4 Interface Contr ol Signals Name PQFP BG A T ype Str ength Descr iption FRAME/ 16 F2 S/T/S 8 mA PCI Cycle Frame is driv en by t he curr ent maste r to indi cate th e begin ning a nd durat ion o f an acces s.
PCI Bus In terf ace Sig nals 3-7 3.3.4 Arbitration Signals Ta b l e 3 . 5 de scribe s Arbit rat ion si gnals . 3.3.5 Error Repor ting Signals Ta b l e 3 .
3-8 Signa l Descripti ons 3.3.6 Interrupt Signal Ta b l e 3 . 7 descr ibes th e Inter rupt signa l. 3.4 SCSI Bus Interf ace Signals The SCS I Bus Interface sig nals secti on contai ns tables descr ibing th e sign als f or the f ollowing sig nal groups : SCSI Bus Inter f ace Sign als , SCSI Signa ls ,a n d SC SI Cont rol Sig nals .
SCSI Bus Interf ace Signals 3-9 3.4.2 SCSI Signals Ta b l e 3 . 9 descr ibes th e SCSI signals. 3.4.3 S CSI Contr ol Signals Ta b l e 3 . 1 0 des cr ibes t he SCSI Control s ignals.
3-10 Signa l Descriptions 3.5 GPIO Si gnals Ta b l e 3 . 1 1 des cr ibes t he SCS I GPIO s ignals. T able 3.11 GPIO Signals Name PQFP BGA T ype Strength Description GPIO0_FETCH / 53 N 5 I/O 8 mA SCSI General Purpose I/O pin. Opt ionally , when d r iven LO W , indica tes t hat the n e xt bus requ est w il l be for an o pcod e fetch.
ROM Fla sh a nd M emor y In terface S ig nals 3- 11 3.6 ROM Flash and Memor y Interface Signals Ta b l e 3 . 1 2 des cr ibes t he ROM Fla sh and Memor y In terface sign als. T a ble 3 .12 R OM F las h and Mem ory Int erfa ce Sig nal s Name PQFP BGA T ype Strength Descrip tion MWE/ 139 C7 O 4 mA Me mor y Wr ite En able .
3-12 Signa l Descriptions 3.7 T e st In terf ace Sig nals Ta b l e 3 . 1 3 des cr ibes T e st Inte rf ace s ignal s . MAD[7:0 ] 59–6 2, 64–6 7 L7, M7, N7, K7, M8, N8, L8, K8 I/O 4 mA Memory Address/Data Bus.
P ow er and Ground Signals 3-13 3.8 P ow er and Ground Signals Ta b l e 3 . 1 4 des cr ibes t he P ower and Gr ound sig nals. T able 3.14 P ower and Gr ound Signals Name PQFP BGA T ype Strength Descri.
3-14 Signa l Descriptions 3.9 MAD Bus Programming The MAD[7 :0] pins, in ad ditio n to ser vin g as the ad dress/d ata bus f o r the loca l memor y inter f ac e, also are used t o program power-up opti ons for the chip.
MAD Bus Progr amming 3-15 • The MAD[ 0] pin i s the slow ROM pin. When pu lled up, it enables two e xtra cycles of dat a acces s time to a llow use of sl ow er m emor y de vices.
3-16 Signa l Descriptions.
LSI53C8 75A PCI to Ultra SCSI Controll er 4-1 Chapter 4 Regi sters This chap ter descr ib es all LSI53 C875A regis ters and is divi ded into th e f ollowin g sec tions: • Secti on 4.1 “PCI Configuration Reg isters ” • Section 4.2 “S CSI Register s” • Secti on 4.
4-2 Re gist ers bits that are cur rently suppor ted by the L SI53C875A are des cri bed i n this chapt er . Reser ved bits sho uld not be accessed . Regist er s: 0x00–0 x01 V endor ID Read Only VID V e ndor ID [15:0] This 16 -bi t regis ter id entif ie s the man uf actur er of the de vice.
PCI Con fi gura tio n Reg ist ers 4-3 Regist er s: 0x02–0 x03 Device ID Read Only DID Device ID [15:0] This 16 -bi t r egister id entif ie s the par ticu lar de vice .
4-4 Re gist ers R Reser ved 5 WIE Write and In validate Enable 4 This b it allows the L SI53C875A to gene r ate w rit e and inv alidat e command s on th e PCI bus. The W IE bit i n the DMA Contr ol (DCNTL) regi ster must a lso be se t for the de vice to generate Wr ite a nd Inv alida te comman ds.
PCI Con fi gura tio n Reg ist ers 4-5 Regist er s: 0x06–0 x07 Statu s Read/Write Reads to this r egister b ehav e nor mal ly . Writes ar e slightly di ff erent in that bits can be cl eared, but not set. A bit is clear ed whenev er the register is writ ten, and the data in the cor respon ding bit loc ation is a one.
4-6 Re gist ers These b its are read onl y and sho uld indi cate th e slowest time th at a device asser ts DEVS EL/ for any b us comm and e xcept Configu ration Re ad and Co nfiguratio n Wri te.
PCI Con fi gura tio n Reg ist ers 4-7 Regist er s: 0x09–0 x0B Class Code Read Only CC Class Code [23:0] This 24-bi t registe r is used to identi fy the gen eric func tion of the d e v ice.
4-8 Re gist ers Regist er: 0x0D Latenc y Timer Read/Write L T Latency Ti mer [7 :0] The Late ncy Ti mer reg ister spe cifie s, in units o f PCI bus clocks, the value of th e Latency Timer f o r this P CI bus maste r . The LS I53C875 A suppor ts this timer .
PCI Con fi gura tio n Reg ist ers 4-9 Regist er s: 0x10–0 x13 Base Address Register Zero (I/O) Read/Write B A R0 Base Address Regist er Zero - I/O [31:0] This ba se addres s regis ter is u sed to ma p the ope r atin g reg ist er set i nto I/ O space .
4-10 R egist er s Regist er s: 0x18–0 x1B Base Address Register T w o (SCRIPTS RAM) Read/Write B A R2 Base Address Regist er T wo [31:0] This b ase reg ister is us ed to map the S CRIP TS RA M into memor y space. Th e def ault v alue of th is regis ter is 0x000000 00.
PCI Con fi gura tio n Reg ist ers 4- 11 contro ller instal led on them (and the ref ore the sa me V endor ID and Device ID). If the exter nal s eria l EEPROM in terf ace is enabled (MAD [7] LOW), this.
4-12 R egist er s v alue that s hould b e stored in the exter nal ser ial EEPROM i s vendor s pecifi c. Pl ease s ee the Section 2.4 “Ser ial EE PROM Inter f ace” in Chapter 2 f or a dditio nal inf or m ation on downlo ading a value f or thi s registe r .
PCI Con fi gura tio n Reg ist ers 4- 13 Regist er: 0x34 Capabilities P o inter Read Only CP Capabilities P ointer [7:0] This reg ister i ndica tes that the first extend ed capabi lity registe r is locate d at offset 0x40 in the PCI Co nfiguration .
4-14 R egist er s Regist er: 0x3D Interrupt Pin Read Only IP Interrupt Pin [7:0] This reg ister indica tes which in terr upt pin the de vice uses. Its v a lue is set to 0x01 f o r the INT A / signal. Regist er: 0x3E Min_Gnt Read Only MG MIN_GNT [7:0] This re gist er is used to sp ecify th e desir ed settin gs f or latenc y timer values.
PCI Con fi gura tio n Reg ist ers 4- 15 Regist er: 0x40 Capability ID Read Only CID Cap_ID [7:0] This regi ster indi cates th e type of data str uctur e curre ntly being used.
4-16 R egist er s D2S D2_Support 10 The LSI5 3C875A sets this bit to in dicate s uppor t f or power manage ment st ate D2. D1S D1_Support 9 The LSI5 3C875A sets this bit to in dicate s uppor t f or power manage ment st ate D1.
PCI Con fi gura tio n Reg ist ers 4- 17 DSCL Data_ Scale [14:13] The LSI5 3C875A does not s uppor t the d ata regist er . Therefore, these two bits are alway s c leared. DSL T Data_Sel ect [12:9] The LSI5 3C875A does not s uppor t the d ata regist er .
4-18 R egist er s Regist er: 0x47 Data Read Only D A T A Data [7:0] This reg ister provides an o ptional m echanism for the function to repor t state -depende nt operating data. T he LSI53C 875A do es not use this regi ster and always returns 0x00. 4.
SCSI Registers 4-19 T able 4.2 SCSI Re gister A ddress Map 31 16 15 0 SCNTL3 SCNTL2 SCNTL1 SCNTL0 0x00 GPREG0 SDID SXFER SCID 0x 04 SBC L SSI D SOCL SFBR 0x08 SST A T 2 SST A T1 SST A T0 DST A T 0x0C .
4-20 R egist er s Regist er: 0x00 SCSI Contr ol Zer o (SCNTL0) Read/Write ARB[1:0] Arbitration Mode Bits 1 and 0 [7:6] Sim ple Ar bitr ation 1. Th e LSI53C875A waits f or a bus free con dition to occu r . 2. It as ser ts SBSY / and i ts SCSI ID (contain ed in t he SCSI Chip ID (SCID) register ) onto the SCSI bus.
SCSI Registers 4-21 Full Ar bitration , Selection/R eselect ion 1. Th e LSI53C875A waits f or a bus free con dition . 2. It as ser ts SBS Y/ and its S CSI ID ( the highes t pr iori ty ID stored i n the SCSI Chip ID (SCID ) registe r) onto the SCSI b us .
4-22 R egist er s W A TN Select with SA TN/ on a Start Sequence 4 When thi s bit is set and the LS I53C875A is i n the initiato r mode, the SA TN/ s ignal is asse r ted d urin g selecti on of a SCS I targ et de vic e . This is t o inf orm the tar get th at th e LSI5 3C87 5A has a messa ge to se nd.
SCSI Registers 4-23 ( SET TARGE T or CLEAR TA RGET ). When this bit is se t, the chip is a target device by def ault. Whe n this bit is cl eared, the LS I53C8 75A is a n initiato r device by default.
4-24 R egist er s ma y transfer up to three addit ional bytes before halting to synchr onize be tween inter n al core cells. Du ring synchr onous op eration, the LSI 53C8 75A tr ansfers data until the re are no outsta nding synchr onous offs ets.
SCSI Registers 4-25 SCSI Co ntrol Zer o (SCNTL0) regis ter are s et for full arbitration a nd sele ction b ef o re setti ng this bi t. Arb itr at ion is re tried un til w on. At that p oint , the LSI53C 875A holds SB SY and SS EL ass er te d, and waits f o r a select or res elect seq uence.
4-26 R egist er s Caution : Wri ting to thi s regis ter wh ile not co nnecte d may cause th e loss of a sele ction /resele ction by clear ing the Connec ted bit. Regist er: 0x02 SCSI Contr ol T wo (SCNTL2) Read/Write SDU S CSI Disconnect Unexpected 7 This bit is valid in the i nitiator m ode only .
SCSI Registers 4-27 combi ned with t he firs t byte from the subsequ ent transfer so that a wide transfer is complet ed. SLPMD S LP A R Mode 5 If this bit is cle ared, the SCS I Longitu dinal Parity (SLP AR ) registe r functions as a byte-wide long itudi nal pari ty registe r .
4-28 R egist er s group codes. If this bit is set , the de v ice does not rel oad the Block Move b yte cou nt, regardl ess of th e group cod e. WSR Wide SCSI R eceive 0 When re ad, this bit retu rn s the value of th e Wide SCSI Receive (WSR) flag. Set ting this bit c lears the WSR fl ag.
SCSI Registers 4-29 SCF[2:0] Synchr onous Cloc k Con v er sion F actor [6:4] These b its sel ect a factor by which t he fre quency of SCLK i s divi ded before being p resented to the synchr onous S CSI co ntrol log ic. W rite these to th e same v alue as t he Clock Conv er sion F actor bits bel ow unless f a st SCS I operation is desi red.
4-30 R egist er s Regist er: 0x04 SCSI Chip ID (SCID ) Read/Write R Reser ved 7 RRE Enable Response to Reselection 6 When t his bi t is s et, the LSI53C 875A is enabled to respond to bus-initi ated res election at the chi p ID in th e Respo nse ID Zero (R ES PID0) and Respon se ID One (RES PID1 ) registe rs.
SCSI Registers 4-31 Regist er: 0x05 SCSI T ransfer (SX FER ) Read/Write Note: Wh en using T ab le Ind irect I/ O comma nds, bits [7: 0] of th is registe r are loade d from the I/O da ta str ucture.
4-32 R egist er s (This SCSI s ynchrono us core c loc k is deter m ined in SCNTL3 b its [6:4], E xtCC = 1 i f SCNTL1 b it 7 is as ser ted and the LSI53C 875A is sen ding da ta. ExtCC = 0 if th e LSI53C 875A is r eceiv ing data.) SXFER P = 1 00 ÷ 25 = 4 Where: Ta b l e 4 .
SCSI Registers 4-33 Ta b l e 4 . 4 s hows e xampl e transf er per iod s and rates for f ast SCSI-2 a nd Ultra SCSI. MO[4:0] Max SCSI Synchr onous Offset [4:0] These bi ts des cribe the max imum SCS I synchro nous offset used by the LSI 53C8 75A when transferri ng synchr onous SC SI data in eit her the initiato r or target mode.
4-34 R egist er s T able 4.5 Maxim um Synchr onous Offset MO4 MO3 MO2 MO1 MO0 Synchrono us Offset 00000 0 - A s y n c h r o n o u s 00001 1 00010 2 00011 3 00100 4 00101 5 00110 6 00111 7 01000 8 0100.
SCSI Registers 4-35 Regist er: 0x06 SCSI Dest ination ID (SDID) Read/Write R Reser ved [7:4] ENC Encoded Dest ination S CSI ID [3:0] Wri ting th ese bits se t the SCSI ID of the in tended i nitiator or targe t dur ing SC SI resel ectio n or sel ection ph ases, respectively .
4-36 R egist er s is als o poss ible to pro gr am these sign als as l ive inputs and sense them th rough a SCRIPT S regist er to register Mo ve I nstruc tio n. GPI O4 ma y be used t o enab le or disa b le V PP , the 12 V ol t power supply to the ex ter nal flash memor y .
SCSI Registers 4-37 ab y t es t o r e di ns y s t e mm e m o r y ,t h eb y t em u s tf i r s tb e mov ed to an in ter mediate LS I53C87 5A regis ter (such as a SCRA TC H regist er), and then to the S FBR.
4-38 R egist er s Regist er: 0x0A SCSI Se lector ID (SSI D) Read Only V AL SCSI V alid 7 If V AL i s asser te d, then the two SCS I IDs are d etected on the bus durin g a b us-ini tiated sele ction or re selecti on, and the encod ed destinati on SCSI ID bits below are v alid .
SCSI Registers 4-39 REQ SREQ/ Stat us 7 AC K S AC K / S t a t u s 6 BSY SBSY/ Status 5 SEL SS EL/ Statu s 4 AT N S A T N / S t a t u s 3 MSG SMSG/ St atus 2 C_D SC_D/ Status 1 I_O SI_O/ St atus 0 Regi.
4-40 R egist er s MDPE Master D ata P arity E rror 6 This b it is set wh en the LS I53C 875A as a mas ter de tect s a data par ity err or , or a targe t de vice sig nals a par ity erro r duri ng a data phase. This bit is co mpletely di sabled b y th e Mast er P ari ty Err or E nab le bit ( bit 3 of Chi p T es t F our (CTEST4) ).
SCSI Registers 4-41 • Duri ng a T ransfer Control i nstruc tion, t he Compare Data (bit 18 ) and Co mpare Pha se (bit 17 ) bits ar e set in the DMA Byte Coun ter (DBC) reg ister whil e the LSI53C 875A is i n tar get mode.
4-42 R egist er s Regist er: 0x0D SCSI Sta tus Zer o (SST A T0) Read Only ILF SIDL Least S ignifican t Byte Full 7 This bit is set whe n the least sign ificant byte in the SCSI In put Dat a Latch (S IDL ) regi ster con tains dat a.
SCSI Registers 4-43 AIP Arbitration in Pr ogress 4 Arbitration in Progre ss (AIP = 1) indica tes that the LSI53C 875A has de tected a Bus F ree cond ition, as ser ted SBSY , and as ser ted its SCSI ID ont o the SCSI bus.
4-44 R egist er s synchr onous da ta transfers, or up to 31 wo rds f or wide. V alue s ov er 31 will not occ ur . T able 4.6 SCSI Synch ronous Data FIFO W ord Count FF4 (SST A T2 bit 4) FF3 FF2 FF1 FF.
SCSI Registers 4-45 SDP0 L La tc hed SCSI P arity 3 This bit r eflects the SCSI p arity signal ( SDP0/), corre sponding to th e data latched i n the SCSI Inpu t Data Latch ( SIDL) . It cha nges whe n a ne w byte is latched i nto the lea st signi ficant byte of the SIDL registe r .
4-46 R egist er s Regist er: 0x0F SCSI Status T w o (SST A T2) Read Only ILF1 SIDL Most Significant Byte Full 7 This bit i s set when t he mos t signifi cant byte in the SCSI In put Da ta Latc h (SID L) cont ains d ata.
SCSI Registers 4-47 fi eld, s ee the d efi nit ion f or SCSI Stat us One (SST A T1) bits [7:4] . SPL1 Latched SCSI P arity f or SD[15:8] 3 This a ctiv e HIGH bi t reflec ts the SCS I odd pa rity s ignal corre sponding to the da ta latched into th e most s i g n i f i c a n tb y t ei nt h e SC SI Input Data Latch (S IDL) registe r .
4-48 R egist er s Regist er: 0x14 Interrup t Status Zero (IS T A T0) Read/Write This r egister is acces sible by the host CP U whil e a LSI5 3C875A is e x ecuting SCRIP TS (without inte rf eri ng in the operation of the function ). It is use d to poll for interr upts if har dware interr upts a re disabled.
SCSI Registers 4-49 clea r the ID Mod e bit or a ny of the PCI co nfigura tion registe rs. This bit is no t self- clear in g; it must be c leared to clear the reset cond ition (a hardware rese t also clears this bit).
4-50 R egist er s the SCRIPTS pr ocesso r is s til l e xecuting a SCRIPTS program. If this bit is set when th e Interr upt Sta tus Zero (IST A T0) or Interr upt Stat us One ( IST A T1) regi sters ar e read th e y are n ot automat ically c leared. T o c lear this b it, writ e it to a one.
SCSI Registers 4-51 • A bus f ault i s dete cted • An abo r t c ondition i s detect ed • A SCRIPT S instr uction i s ex ecuted in si ngle step mode • A SCRIPT S inter rupt i nstr uction is e x.
4-52 R egist er s additi on, this bit ma y be read and wr itten while SCR IPTS are ex e cuting. Regist er: 0x16 Mailbox Zero (MBO X0) Read/Write MBO X0 Mail bo x Zer o [7:0] These are general pu r pose bits that may be read or writ ten whil e SCRIP TS are r unnin g.
SCSI Registers 4-53 Regist er: 0x18 Chip T est Ze r o (CTEST 0) Read/Write FMT Byte E mpty in DM A FIFO [7:0] These bits iden tify the bottom bytes in the DM A FIFO that are empty . E ach bit cor respond s to a byte lane in the DMA FIFO . For example, if byte lane three is empty , then FMT3 will be set.
4-54 R egist er s Regist er: 0x1A Chip T est T w o (CTEST2) Read Only (bit 3 write) DDIR Data T ransfer Di rection 7 This st atus bit indic ates whic h direc tion d ata is being transferred. When th is bit is s et, the d ata is transferred from the S CSI bus to the host bus.
SCSI Registers 4-55 Base Addr ess Re gister One (M EMOR Y) .T h i si st h e memor y mapped o perating register base addr ess. Bits [9:0] wi ll be 0. The SCRA TCHB r egister contains bits [31:13] of the RA M Base Addr ess value from the PCI Base Addre ss Regis ter T wo (S CRIP TS RAM) .
4-56 R egist er s Regist er: 0x1B Chip T est Th ree (CT EST3) Read/Write V C h i pR e v i s i o nL e v e l [ 7 : 4 ] These b its iden tify th e chip revision lev el for software pur pos es. It sho uld hav e the same value as t he lower nibble of the PCI Re vis ion ID (Re v ID) re gister , at a ddress 0x08 in t he con figuration spa ce.
SCSI Registers 4-57 WRIE Write and Inv alidate Enable 0 This b it, when set, caus es the is suing of Wr ite and Inv al idate comma nds on the PCI b us whenev er legal. The Wr ite an d Inv a lidat e Enable bit in the PCI Config uration Comm and reg ister must al so be set i n order for the chip to gene rate Wr ite an d Inv a lidate comm ands.
4-58 R egist er s while data is be ing transferred between t he two cor es. Once the chip has stop ped transferring data, thes e bits ar e s tabl e. The DMA F IFO (D FIF O) regist er counts th e number of b yte s transf erred between the DMA c ore and th e SCSI cor e.
SCSI Registers 4-59 Regist er: 0x21 Chip T est Four (CTEST4) Read/Write BDIS Bur st Disable 7 When set , this bit caus es the LSI5 3C875A to perf or m bac k-to-b ac k cyc les f or al l tra nsf ers . Whe n thi s bit is clea red, back-to-back transf ers for opc ode f e tches and b ur st tr ans f e rs f or data mov es are per f or med.
4-60 R egist er s LSI53C 875A is inf or med of the error by the PERR/ pin being asser ted by the t arget. Whe n this bi t is clea red, th e LSI53C 875A does not in terr upt if a master parit y error occu rs.
SCSI Registers 4-61 the curr ent DBC value. This bit auto matic ally cle ars itse lf after inc rementi ng the DNAD register . BBCK Cloc k Byte Counter 6 Settin g this bi t decrem ents th e byte count co ntaine d in the 24-bi t DBC r egister .
4-62 R egist er s BO[9:8] DMA FIFO Byte Offset Counter , Bits [9:8] [1:0] These a re the upp er two bits of the DFBO C . The DFB OC cons ists of th ese bits, and the DMA FIFO (DFIFO) registe r , b its [7 :0].
SCSI Registers 4-63 LSI53C 875A. Th e DBC c ounter is decr emente d each time da ta is transferred on the PCI bus. It is de cremente d b y a n amount equal to th e number of bytes that are transf erred. The maximum numbe r of b ytes that ca n be transf erred in any one Blo ck Mov e c ommand is 16,7 77,215 bytes.
4-64 R egist er s Regist er s: 0x28–0 x2B DMA Next Address (DNA D) Read/Write DNAD DMA Next Ad dress [31:0] This 32- bit regis ter contai ns the general pur pose addr ess pointer . At the s tar t of some S CRIPTS operations, i ts v alue is copi ed from the DMA SCRIPTS P ointer Sa ve (DSP S) regi ster .
SCSI Registers 4-65 Regist er s: 0x30–0 x33 DMA SCRI PTS P oin ter Save (D SP S) Read/Write DSPS DMA SCRI PTS P ointer S ave [31:0] This register c ontains the second Dword of a SCRIPTS instr uct ion. It i s ov erwr itten each time a S CRIPT S instr uct ion is f etched .
4-66 R egist er s Regist er: 0x38 DMA Mode (DMODE) Read/Write BL[1:0] Burs t Length [7:6] These b its cont rol th e maximum numb er of D words transf erred per bus ownership , regardl ess of whether the transfers are back-to-b ack, b urst, o r a comb inatio n of both.
SCSI Registers 4-67 SIOM Source I/O Me mory En able 5 This bit is defined as an I/O Memor y Enable bit f or the sour ce addr ess of a Memo r y Move or Blo c k Mov e Comman d. If this bit i s set, then the s ource ad dress is in I/O space; and if clear ed, then the source add ress is in memor y s pace.
4-68 R egist er s ERMP Enable Read Multiple 2 If this bi t is set a nd cache mode i s enabled, a Rea d Multi ple comm and is used on a ll read c ycles w hen it is legal . BOF B urst Opcode Fetc h Enable 1 Settin g this bit caus es the LSI53C 875A to f etch ins tructions in burs t mode .
SCSI Registers 4-69 Regist er: 0x39 DMA Interrupt Enable (DIEN) Read/Write R Reser ved 7 MDPE Master D ata P arity E rror 6 BF Bus Fault 5 ABRT Aborted 4 SSI Sin gle Step Interrupt 3 SIR SC RIPTS In t.
4-70 R egist er s F or more informat ion on interr upts, see Chapter 2, “Functi onal Descrip tion” . Regist er: 0x3A Scratch By te Register (SBR) Read/Write SBR Scratch Byte Re gister [7:0] This i s a ge neral pur pose re gister . Apar t fr om CPU acce ss, only r egister Read/Wr ite and Memor y Mov es i nto this re gister a lter its co ntents.
SCSI Registers 4-71 the LSI53C 875A to make more efficient use of the syst em PCI b us, t hus imp ro vin g ov eral l syste m performa nce. The unit wi ll flush whene v er th e PFF bit is set, as well .
4-72 R egist er s STD S tart DM A Operation 2 The LSI5 3C875A fetches a SCS I SCRIPT S inst r uction from the a ddress containe d in the DMA S CRIPTS P ointer (DSP) regis ter when thi s bit is set.
SCSI Registers 4-73 Regist er s: 0x3C– 0x3F Adder Sum Outpu t (ADDER) Read Only ADDER Adder Sum Output [31:0] This reg ister c ontains th e outpu t of t he inte rn al add er , and is used pr imar ily f or test pur pose s. The power-up v alue f or thi s regis ter is i ndeter m inate.
4-74 R egist er s CMP Fun ction Complete 6 Indicate s full arbi tration and s electio n sequenc e is compl eted. SEL S ele cted 5 Indicate s the LSI53C 875A is s elected b y a SCSI initiato r de vice. Set th e Enable Res ponse to Selec tion bit in the SCSI Chip ID (SCI D) reg ist er f or thi s to occur .
SCSI Registers 4-75 RST SCSI Reset Condition 1 Indicate s ass er tion of th e SRST/ s ignal by t he LSI53C 875A or any othe r SCSI device. This condi tion is edge-tr ig gered, s o multiple i nterru pts canno t occu r because of a si ngle SRS T/ pulse.
4-76 R egist er s HTH Handshake-to- Handshake Timer Expire d 0 The han dshake-to-h andsh ak e t imer is expire d. The ti me measu red is the S CSI Req uest-to-Req uest (tar get) or Acknowledge-to- Acknowledge (ini tiator) peri od.
SCSI Registers 4-77 target . In target mode, this bi t is set wh en the S A T N/ sign al is asser ted by the initiator . CMP Fun ction Complete 6 This b it is set whe n an ar bitration o nly or fu ll arbitration seque nce i s comple ted. SEL S ele cted 5 This b it is se t when the LSI53C 875A i s selected by anothe r SCSI device.
4-78 R egist er s • Residual data in the synchr onous da ta FIFO – a transfer other tha n syn chronou s data receive is star ted wi th data l eft in the s ynchr onous data FIFO .
SCSI Registers 4-79 (SIEN1) register or not. E ach bit tha t is set indicate s an occ urrence of the corres ponding con ditio n. Readin g the S IST1 cl ears the inter rupt c onditio n.
4-80 R egist er s check byte are rec eived from the S CSI bus (all signals are shown ac tiv e HIG H): A one in any bit po sition of the fi nal SLP AR value would i n d i c a t eat r a n s m i s s i o ne r r o r . The SLP AR re gister is also use d to generate the check b yte s f or SCSI send o peration s.
SCSI Registers 4-81 W h i c hb y t ei sa c c e s s e di sc o n t r o l l e db y t h eS L P H B E Nb i t in the SCSI Control T wo (SCNTL2) register . Regist er: 0x45 SCSI Wide Residue (SW IDE) Read/Wri.
4-82 R egist er s DW R D a t a W r i t e 3 This bi t is used t o defin e if a data write is c onside red t o be a lo cal m emor y acce ss. DRD Data Read 2 This bit is used to define if a data r ead is consi dered to be a lo cal m emor y acce ss.
SCSI Registers 4-83 LEDC LED_CNTL 5 The inte rn al con nected si gnal (bi t 3 of the Inte rrupt S tat us Zero (IST A T0 ) reg ist er) wi ll be pres ente d on GP IO0 i f th is bit is s et and b it 6 of GP CNTL0 is cleare d and the c hip is no t in progress of perfor ming a n EEP R OM autodownlo ad regar dless of the sta te of bi t 0 (GPI O0).
4-84 R egist er s SEL[ 3:0] Select ion Time-Ou t [ 3:0] Thes e bits sel ect t he SCSI s elect ion/r e sel ectio n time- out pe riod. When th is timi ng (plu s the 200 µ s sel ection a bor t time) is e xceede d, the S T O bi t in the SC SI Inter rup t Status O ne (SIST1 ) registe r is set.
SCSI Registers 4-85 Regist er: 0x49 SCSI Timer One (STIME1) Read/Write R Reser ved 7 HTHB A Hands hake-to-Handshake Timer Bus Activity Enable 6 Settin g this bit caus es this time r to begin tes ting for SCSI REQ/, ACK/ activ ity as soon as SBSY/ is as ser ted, regard less of the agents par ticipat ing in the transfer .
4-86 R egist er s Regist er: 0x4A Re spon se ID Zer o (RES PID0 ) Read/Write RESPIO0 Response ID Zero [7:0] RESPID0 a nd Respon se ID One (RESPID1) contain the sele ction or resele ction IDs. In ot her words, these two 8-bit r egister s contain the I D that the c hip respo nds to o n the SCSI bus.
SCSI Registers 4-87 c h i pc a na r b i t r a t ew i t ho n l yo n eI Dv a l u ei nt h eS C I D registe r . Regist er: 0x4C SCSI T est Zero ( STEST0) Read Only SSAID SCSI Sele cted As ID [7:4] These bi ts contai n the encoded value o f the SCSI ID th at the LSI53C 875A is selec ted duri ng a SCSI selectio n phase.
4-88 R egist er s SOM SCSI Synchr onous Offset Maxim um 0 This bi t ind icate s that the cu rren t synch ronou s SREQ/ , SA CK/ of fse t is the maxi mum specifi ed by bits [3:0 ] in the SCSI T ran sfer (SXFER ) reg ister . This bit is not la tched and may change at any time.
SCSI Registers 4-89 QSEL SCLK Qua drup ler Select 2 This bit , when s et, sel ects the output of the in ter nal cl oc k quadr upler f or use a s the inte r nal SCS I clock. Whe n clea red, this b it selects the c lock presente d on SCLK for use as th e inter n al SCSI c loc k.
4-90 R egist er s SZM SCSI Hi gh Imp edance Mode 3 Settin g this bi t place s all th e open drain 48 mA SCSI dri v ers in to a high impedan ce st ate. This is to allow inter na l loopback mo de operation wit hout affecting the SCSI bus.
SCSI Registers 4-91 Regist er: 0x4F SCSI T est Three (STE ST3) Read/Write TE T oler ANT Enable 7 Settin g this bi t enables th e active negatio n por tion of LSI Lo gic T oler ANT tec hnology .
4-92 R egist er s f o r test pur poses or to lower I DD during a po wer -do wn mode. DSI Dis abl e Sin gl e Ini ti ator Re sp ons e 4 If this bi t is set, the LS I53C875 A ignores a ll bus-initiated sele ction atte mpts that empl o y th e single in itiator opti on from SCS I-1.
SCSI Registers 4-93 STW SC SI FIFO T es t Wri te 0 Settin g this bit place s the SC SI core i nto a tes t mode i n which the FIF O is easily read or writ ten. While this bit is set, wr ites to the le ast sign ificant byte of th e SCS I Out put Data Latch (SO DL) regis ter caus e the en tire word conta ined in the SODL to be loaded into the FIFO .
4-94 R egist er s Regist er: 0x52 SCSI T est Four (STEST4) Read Only R Reser ved [7:6] LOCK Frequency Loc k 5 This bi t is use d when en abling the S CSI clock quadr upl er , whic h all o ws the LSI 53C 875A to tr ans f er data at Ul tr a SC SI rates.
SCSI Registers 4-95 Regist er: 0x56 Chip Contr ol 0 (CCNTL0) Read/Write ENPMJ E na ble Phase Mis match Jump 7 Upon se tting this bit, any phas e misma tches do not interr upt b ut force a jump to an al ter nate l ocation to handl e the phase mism atch.
4-96 R egist er s ENNDJ Enable Jump on Nond ata Phase Mismatches 5 This bit con tro ls whe ther or not a jum p is tak en during a no ndata p hase mis match (i.
SCSI Registers 4-97 Regist er: 0x57 Chip Contr ol 1 (CCNTL1) Read/Write ZMO DE Hig h Impe dan ce Mod e 7 Settin g this b it ca uses t he LSI53C 875A t o pl ace all ou tput and bidir ecti onal pins e xcep t MAC/_TEST OUT , in to a high im pedance sta te.
4-98 R egist er s Inde x Mode 1 (64TIMO D set) table entr y f or mat: EN64TIBMV Ena ble 64-Bit T able Indirect BMO V 1 Settin g this bi t enables 64 -bit addr essin g f or T able Indirec t BMO Vs using th e upper byte (bit [24:31]) of the first Dwor d of the table entr y .
64-Bit SCRIPTS Selec tors 4-99 Regist er: 0x5A– 0x5B Rese rved Regist er s: 0x5C– 0x5F Scratch Regi ster B (SCRA TCHB) Read/Write SCRA TCHB Scrat ch Register B [31:0] This i s a ge neral pur pose use r defi nable scratch pad registe r .
4-100 Reg isters operation i s performed , one of the si x selector regist ers below will be used t o generate a 6 4-bit add ress. If the s elector f o r a par ticul ar device operation is zero , then a s tandard 32-bit a ddress cycle w ill be gen erated.
64-Bit SCRIPTS Selec tors 4-10 1 Regist er s: 0xA4–0x A7 Memor y Move Wri te Selecto r (MMW S) Read/Write MMWS Memor y Move Write Selector [31:0] Suppl ies the upper Dword of a 64-bit addr ess duri ng data writ e operations du rin g Memor y-to- Memor y Moves and absolute addre ss ST O RE operations.
4-102 Reg isters Write s to the SF S regis ter ar e unaf f ected . Clea ring the PCI Confi guratio n Into En able bit causes the S FS regis ter to retur n to nor m al operatio n.
Phase M isma tch Jump Re gis ters 4 -1 03 Regist er s: 0xB4–0x B7 Dynamic Blo ck Mo ve Sel ector (DBM S) Read/Write DBMS Dyn amic Block Move Select or [ 31:0] Suppl ies the u pper Dword of a 64- bit add ress du ring b lock mov e operatio ns, reads or wr ites.
4-104 Reg isters Regist er s: 0xC0–0x C3 P h a s eM i s m a t c hJ u m pA d d r e s s1( P M J A D 1 ) Read/Write PMJAD1 Phase Mismat ch J ump A ddress 1 [31:0] This r egister contain s the 3 2-bit address that will be jumpe d to upon a ph ase mism atch.
Phase M isma tch Jump Re gis ters 4 -1 05 Regist er s: 0xC8–0x CB Remaining Byte Count (RBC) Read/Write RBC Remaining Byte Count (RBC) [31:0] This regi ster co ntains the byte coun t that re mains for the BMO V th at w as e x ecuti ng when the phase mism atch occu rred.
4-106 Reg isters In the c ase of a S CSI dat a receive, if ther e is a byte in the SCSI Wi de Resid ue (SWI DE) register th en this addre ss will poin t to the location where tha t byte must be stored. The S WIDE byte must be manually wr itten to memor y and th is addr ess must be increm ented pr ior t o updati ng any scatte r/gather entr y .
Phase M isma tch Jump Re gis ters 4 -1 07 Regist er s: 0xD4–0x D7 Instruct ion Address ( IA) Read/Write IA Instruction Addr ess [31: 0] This r egister alwa ys conta ins th e addres s of the BMO V instr uct ion tha t was ex ecuti ng when the phase m isma tch occu rred.
4-108 Reg isters canno t be counte d f or th is BMO V as it was act ually p ar t of the byte coun t for the pre vious B MO V . Regist er: 0xDB Rese rved Registers: 0x DC–0xDF Cum ulative SCSI Byte C.
LSI53C8 75A PCI to Ultra SCSI Controll er 5-1 Chapter 5 SCSI SCRIPTS Instruction Set The LSI5 3C875A co ntains a S CSI SCR IPTS proc essor that per mits bot h DMA an d SCSI com mands to be fetched from host m emor y or inter nal SCRI PTS RAM . Algo rith ms wr itten i n SCSI S CRIPT S contro l the ac tions of the S CSI and DMA cores.
5-2 SCSI SCRIPTS Instruction Set requir e cer tain uni que timings or bus sequence s to operate properl y . Anothe r f eature al lowed at the low le v el is l oopback testin g. In loopback m o d e ,t h eS C S Ic o r ec a nb ed i r e c t e dt ot a l k t ot h eD M Ac o r et ot e s t inter nal data p aths all the way out to the c hip’ s pi ns.
High Le v el SCSI SCRIPTS Mode 5-3 Each instr ucti on co nsists of two or thre e 32-bit w ords. The f irst 32-bi t wo rd is alw a ys loaded in to the DMA Command (DCM D) and DMA By te Counter (DBC) regi ster s, the s econd into t he DMA S CRIPTS P o inter Sav e (D SPS ) register .
5-4 SCSI SCRIPTS Instruction Set • The LSI5 3C875 A typic ally fetches two Dwo rds (64 bit s) an d deco des the hig h order byte of the fi rst longword a s a SCRIPTS instr uction. If the instr u ction is a B lock Mov e, the lower three bytes of the f irst longword ar e store d and inter preted as the number of bytes to be mov ed.
High Le v el SCSI SCRIPTS Mode 5-5 Figure 5.1 SCRIPTS O verview System Proces sor System Memory SCS I Initiator Write Exam ple × Select A TN 0, alt _addr × Move from iden tify_msg_buf, when MSG_ OUT.
5-6 SCSI SCRIPTS Instruction Set 5.3 Bloc k M o ve Instru ction P erformi ng a Bl oc k Move instr uctio n, bit 5, Sou rce I/ O - Memor y Enable (SIOM) a nd bit 4, Des tination I /O - Memor y E nable (DIOM) in the DMA Mode (DMO DE) regi ster dete rm ines whet her the sourc e/destina tion address resid es in memo r y or I/O space.
Bloc k Mo ve Inst ruction 5-7 Direct Addressi ng The b yte count a nd abs olut e addr ess ar e: Indirect Addressing Use the f etched byte count, b ut f e tch the data address from the address in the ins truc tion. Once the data po inter add ress i s loaded, it is e xecuted as when th e chip operates i n the dire ct mod e.
5-8 SCSI SCRIPTS Instruction Set the data str ucture. Sign e xtende d v alues of all ones f or negati v e values ar e allowed, but bits [31:24] ar e ignored . Note: Do n ot use indire ct and ta ble indir ect add ressin g simulta neously ; use only one a ddress ing metho d at a time.
Bloc k Mo ve Inst ruction 5-9 OPC OpCode 27 This 1 -bit OpC ode field d efines th e type of Block Mov e (MO VE ) Instru ction to be p ref or med i n T a rget and Initi ator mode. T arget Mode In T arget mode, the Op Code bit define s the following operations : These i nstruc tions pe rf or m the following st eps: 1.
5-10 SCSI SCRIPTS Instruction Set registe r contai ns 0x000 000, an illegal instr ucti on interr upt is ge nerated. 4. The LSI5 3C875A t r ans f e rs the number of bytes specifi ed in the DBC regist er sta r tin g at the a ddress sp ecified in the DMA Next Address (DNAD) r egist er .
Bloc k Mo ve Inst ruction 5-11 registe r . Thes e phase l ines a re latched when SRE Q/ is asse r ted . 4 . I ft h eS C S Ip h a s eb i t sm a t c ht h ev a l u es t o r e di nt h eS C S I SCSI Statu .
5-12 SCSI SCRIPTS Instruction Set TC[23:0] T ra nsfer Counte r [23:0] This 24 -bit fi eld speci fies th e number of d ata bytes to be mov ed between the LSI53C8 75A and system mem or y . The fie ld is stor ed in the DMA Byte Cou nter (DBC ) registe r .
I/O Ins tr uc tio n 5- 13 5.3.2 S econd Dw or d Star t Address [31:0] This 32-b it field s pecif ies the sta r tin g addre ss of the data to mov e to/from mem or y .
5-14 SCSI SCRIPTS Instruction Set 5.4.1 F irst Dw or d IT[1:0] Instruc tion T ype - I/O Instruc tion [31:30] The IT bit co nfiguration (01) de fines an I/O I nstr uction Ty p e .
I/O Ins tr uc tio n 5- 15 This wa y the SCR IPTS can m o v e on to the ne xt instr uct ion before the r esele ction compl etes. It con tinues e x ecuting SCRIPTS u ntil a SCRIPT th at req uires a respons e from th e Initiator is enc ountered .
5-16 SCSI SCRIPTS Instruction Set When t he SACK/ or SA TN/ b its are clear ed, the corre sponding bits a re clea red in the SCSI O utput C ontrol La tch ( SOCL) r egister .
I/O Ins tr uc tio n 5- 17 the LSI53 C875A to Initi ator mode if it is res elected , or to T arget mod e if it is selecte d. If the S elect with SA TN/ fiel d is set, the SA T N/ signal is asse r ted duri ng the s elect ion ph ase.
5-18 SCSI SCRIPTS Instruction Set RA Rela tive Addressing Mode 26 When this bit is set , the 24-bit signed value in the DMA Ne xt Addres s (DNAD) r egister is us ed as a relative disp lacement fro m the current DMA SCRI PTS P ointe r (DSP) address.
I/O Ins tr uc tio n 5- 19 Use this b it only in con junc tion with the S elect , Rese lect, W ai t Selec t, and Wait Reselec t instr uct ions. Use bits 25 and 26 individ ually or in = co mbinat ion to produce the f o llowin g cond itions: Direct Uses the de vice ID and physical add ress i n the instr u ction .
5-20 SCSI SCRIPTS Instruction Set T able Rel ative T reats the al ter nate ju mp addres s as a rel ativ e jum p and f e tches the device ID , synchron ous offse t, and synchr onous p er iod indi rectly .
I/O Ins tr uc tio n 5- 21 R Reser ved [8:7] A C K Set/ Clear SA CK / 6 R Reser ved [5:4] A TN Set/Clear S A TN/ 3 These two bit s are u sed i n conjun ction wi th a Se t or Cle ar instr uct ion to asser t or d easse r t th e corr espon ding SC SI contr ol signa l.
5-22 SCSI SCRIPTS Instruction Set If rela tive or table re lative address ing is used, th is value is a 24- bit sign ed offs et relative to the c urrent DMA SCR IPTS P o inter (D SP) regis ter value.
Read /Wr it e Instr u ctio ns 5- 23 A[6:0] Register Address - A[6:0] [22: 16] It is poss ible to change re gister values from S CRIPTS in read-m odify-wr ite cy cles or move to/from SF BR cycle s. A[6:0] se lects an 8-bit so urce /destinati on registe r within the LSI53C 875A.
5-24 SCSI SCRIPTS Instruction Set 5.5.4 M o ve T o/From SFBR Cyc les All opera tions ar e read-modi fy-wr ites. Howe ver , two regis ters are inv o lved, one o f whic h is al wa ys th e SFBR . Ta b l e 5 . 3 sho ws the possi bl e read-m odify-wr ite o peration s.
T rans fer C ontrol Ins tructions 5-25 Misce llaneo us Notes: • Substi tute the desired reg ister nam e or address for “ R egA” i n the syntax e xamples . • dat a8 in dic ate s eigh t bi ts of dat a. • Use SFBR instead o f data8 t o add tw o register v alues.
5-26 SCSI SCRIPTS Instruction Set 5.6.1 F irst Dw or d IT[1:0] Instruct ion T ype - T ransfer Contr ol Instruc tion [31: 30] The IT bit con figuration (10) de fines the T ransfer Control Inst ruction T ype. OPC[2:0] Op Code [29:27] This 3 -bit f ield spec ifies t he type of T ransfer Contr ol Instr uction t o e x ecute.
T rans fer C ontrol Ins tructions 5-27 DMA SCRIPTS P ointe r Sav e (DSPS) regis ter . T he DSP registe r now contains th e address of the ne xt inst ruct ion.
5-28 SCSI SCRIPTS Instruction Set If the compar iso ns are f alse, the LSI 53C875A fetches t he ne xt inst ruc tion from the add ress poi nted to by the DSP registe r and the instr ucti on pointer is not m odifie d.
T rans fer C ontrol Ins tructions 5-29 RA Rela tive Addressing Mode 23 When this bit is set , the 24-bit signed value in the DMA SCR IPTS P o inter Sav e (D SPS) regi ster is used a s a relative offset fr om the current DMA SCRIPT S P ointer (DSP ) address ( which is poi nting to the next instr uction, not the o ne current ly ex ec uting).
5-30 SCSI SCRIPTS Instruction Set sign ed (2’ s compleme nt), the jump can be f orward or backward. A relati v e transfer can be to any address wi thin a 16 Mbyte segment. The program counte r is combined with the 24-b it signed offset (usi ng addition or subtracti on) to f o r m the new e x ecuti on address.
T rans fer C ontrol Ins tructions 5-31 CD Compare Data 18 When t his bit i s set, the fi rst byte recei v ed from the S CSI data bus (contained in the SCSI First Byt e Receiv ed (SFBR) register) is compar ed with the Data to be Compared Field i n the T ransfer Control instr uction.
5-32 SCSI SCRIPTS Instruction Set DCV Data Compare V alue [7:0] This 8-bit f ield is the data comp ared aga inst the regi ster . These bits are use d in conjunction with the D ata Compare M ask Fiel d to test for a par ticular da ta value.
Memo r y Mov e Ins tr uctio ns 5-33 • Indirec t addres ses a re not all ow ed. A b ur st of da ta is f etch ed from the sour ce address, put in to the DMA FIFO and th en writte n out to the desti nation address. T he mov e conti nues until t he byte count decreme nts to zero , t hen anoth er SCRIPTS i s f etched fr om syste m memor y .
5-34 SCSI SCRIPTS Instruction Set 5.7.2 Rea d/Wr ite Sy stem Memo ry f rom SCRIPTS By usin g the Me mor y M ov e instr uction, single o r multip le regis ter values are transferred to or f rom syste m memor y .
Load and Store Instructio ns 5-35 5.7.4 Third Dw or d TEMP Re gister [31:0] These b its cont ain the destinati on addres s for the Memor y M ov e. 5.8 Lo ad and Store Instructions The Load and Stor e .
5-36 SCSI SCRIPTS Instruction Set The SIOM and DIOM bits in th e DMA Mode ( DMODE) regi ster deter mine whether the de stinat ion or sourc e address of th e instr uction i s in Memor y spac e or I/O s pace, as il lustra ted in th e f ollowing table.
Load and Store Instructio ns 5-37 Note: This b it has no e ff ect unl ess the P ref etch En ab le bit in the DMA Contr ol (DCNTL) re giste r is se t. LS Load and Store 2 4 When t his bit i s set, the instr u ction is a Load . When clea red, it is a Store.
5-38 SCSI SCRIPTS Instruction Set.
LSI53C8 75A PCI to Ultra SCSI Controll er 6-1 Chapter 6 Electrical Specific ations This s ection s pecifie s the LS I53C87 5A electr ic al and mec hanic al character is tics. It is di vided i nto the following se ctions: • Secti on 6 .1, “ DC Ch aract er isti cs” • Secti on 6.
6-2 Elect ri cal Spe cif icati ons T able 6.1 Absolute M aximum Stress R atings 1 1. Stress es be yond thos e listed abo v e ma y cause permanent damag e to the de vice .
DC Characteristi cs 6-3 T able 6.4 Bidirectional Signals—MAD [7:0], MAS/[1:0], M CE/, MOE/, MWE/ Symbol P arameter Min Max Unit T est Conditions V IH Input h igh v oltage 2.0 5.25 V – V IL Input lo w v oltage V SS − 0.5 0.8 V – V OH Output high v oltage 2.
6-4 Elect ri cal Spe cif icati ons T able 6.6 Bidir ectional Signals—AD[31:0 ], C_BE[3:0]/, FRAME/, I RD Y/, TRD Y/, D E V S E L / ,S T O P / ,P E R R / ,P A R Symb ol Pa rameter Min Max Unit T est Conditions V IH Input high v oltage 0.5 V DD 5.25 V – V IL In put low volt age V SS 0.
T olerANT T echn olog y Electrical Char acteristic s 6 -5 6.2 T olerANT T echnolog y Elect rical Characteristi cs The LSI5 3C875 A features T o lerANT techno log y , which in clude s active negati on on th e SCSI d rivers and input s ignal fi lter ing on the SCS I rece iv ers.
6-6 Elect ri cal Spe cif icati ons T able 6.11 T oler ANT T echnology Elect rical Ch aracteri stics for SE S CSI Sign als Symbo l P arameter Min 1 1. Thes e va lues are gu aran teed b y periodic char acterizat ion; the y are not 100% tested on e v er y device.
T olerANT T echn olog y Electrical Char acteristic s 6 -7 Figure 6.1 Rise a nd F a ll Time T e st Condition Figure 6.2 SCSI Input Filter ing Figure 6 .3 Hyste resis o f SC SI Receivers + − 2.5 V 47 Ω 20 pF REQ/ or SA CK/ Input t 1 V TH Note: t 1 is the input filtering period.
6-8 Elect ri cal Spe cif icati ons Figure 6.4 Input Current a s a Function of Input V olta ge Figure 6.5 Output Current as a Function of Output V oltage +40 +20 0 − 20 − 40 − 4 0 4 8 12 16 − 0.7 V 8.2 V HIGH-Z OUTPUT AC T I V E Input V oltage (V olts) Input Current (milliAmperes) 14.
A C Char acteristi cs 6-9 6.3 A C Character istics The AC character istics d escr ibed in this sec tion appl y ov er the e ntire range of ope rating cond itions (refer to the DC Character istics se ction ). Chip tim ings are ba sed on s imulatio n at worst ca se voltage, temperature, and proces sing.
6-10 Electrical Sp ecificat ions Ta b l e 6 . 1 3 and F igure 6.7 provide Reset I nput tim ing da ta. Figure 6.7 Reset Input Ta b l e 6 . 1 4 and F igure 6.
PCI and Ex ternal Memo r y Interf ace Timin g Diag rams 6-11 Figure 6.8 Interrupt Output 6.4 PCI and External Memor y Interface Timi ng Diagrams Figure 6.9 throu gh Figure 6.32 represent signal a ctiv ity whe n the LSI53C 875A a ccesse s the PCI bus. This s ection i ncludes timin g diagrams for access to thr ee groups of m emor y c onfigurati ons.
6-12 Electrical Sp ecificat ions – Burst Read, 32-Bit A ddress an d Data – Burst Read, 64-Bit A ddress an d Data – Burst Write , 32-Bi t Addr ess a nd Data – Burst Write , 64-Bi t Addr ess and.
PCI and Ex ternal Memo r y Interf ace Timin g Diag rams 6-13 6.4. 1 T arget Timing The t ables and figur es in th is sect ion des cr ibe tar get timin gs.
6-14 Electrical Sp ecificat ions Figure 6.10 PCI Conf iguration Register Write T able 6.16 PCI Configuration Regis ter Write Symb ol P arame ter Min M ax Unit t 1 Shared s ignal inp ut setu p time 7 .
PCI and Ex ternal Memo r y Interf ace Timin g Diag rams 6-15 Figure 6.11 32-Bit Operating Register/SCRIPTS RAM Read T able 6.17 32-Bit Operating Register/SCRIPTS RA M Read Symb ol P arame ter Min Max .
6-16 Electrical Sp ecificat ions Figure 6 .12 64-Bit Address Operating Register /SCRIPTS RAM Read T able 6.18 64-Bit Addr ess Operat ing Reg ister/SCRI PTS RAM Read Symb ol P arame ter Min Max Unit t .
PCI and Ex ternal Memo r y Interf ace Timin g Diag rams 6-17 Figure 6.13 32-Bit Ope rating Re gister/SCRIPTS RA M Write T able 6.19 32-Bit Operating Regis ter/SCRIPTS RA M Write Symb ol P arame ter Mi.
6-18 Electrical Sp ecificat ions Figure 6 .14 64-Bit Address Operating Register /SCRIPTS RAM Write T able 6.20 64-Bit Addr ess Ope rating Re gister/SCRI PTS RAM Write Symb ol P arame ter Min Max Unit .
PCI and Ex ternal Memo r y Interf ace Timin g Diag rams 6-19 6.4.2 Initiator Timing The t ables and figures in th is sect ion des cr ibe LS I53C875 A initiat or timin gs.
6-20 Electrical Sp ecificat ions Figure 6.15 Nonbur st Opcode Fetch, 32-Bit Address and D ata CLK (Driven by System) FRAME/ (Dr iv en b y LSI53C8 75A) AD (Dr iv en b y LSI53C8 75A- C_BE/ (Dr iv en b y.
PCI and Ex ternal Memo r y Interf ace Timin g Diag rams 6-21 T able 6.22 Burst Opco de Fetch, 32-Bi t Address and Data Symb ol P arame ter Min Max Unit t 1 Shar ed si gnal in put se tup ti me 7 – ns.
6-22 Electrical Sp ecificat ions Figure 6.16 Burst Opcode Fetch, 32-Bit Address a nd D ata CLK (Driven by System) FRAME/ (Dr iv en b y LSI53C8 75A) AD (Dr iv en b y LSI53C8 75A- C_BE/ (Dr iv en b y LS.
PCI and Ex ternal Memo r y Interf ace Timin g Diag rams 6-23 T able 6.23 Back-to-Back Read, 32-Bit Address and Data Symbol P arameter Min Max Unit t 1 Shar ed s ign al inp ut set up tim e 7 – ns t 2.
6-24 Electrical Sp ecificat ions Figure 6.17 Back-to-Back Read, 32-Bit Address and Data CLK (Dr iv en by Syst em) FRAM E/ (Dr iven by LSI53C8 75A) AD (Dr iven by LSI53C8 75A- C_BE/ (Dr iven by LSI53C8.
PCI and Ex ternal Memo r y Interf ace Timin g Diag rams 6-25 T a ble 6 .24 Ba ck -to -B ac k Writ e, 32- Bit Ad dr ess an d Data Symb ol P arame ter M in Max Un it t 1 Shar ed si gnal in put se tup ti.
6-26 Electrical Sp ecificat ions Fig ure 6. 18 Bac k-t o-B ac k W rite, 32-Bi t Add re ss and Dat a CLK (Driven by System) FRAME/ (Dr iv en b y LSI53C8 75A) AD (Dr iv en b y LSI53C8 75A- C_BE/ (Dr iv .
PCI and Ex ternal Memo r y Interf ace Timin g Diag rams 6-27 T able 6.25 Burst Read, 32 -Bit A ddress and Da ta Symb ol P arame ter Min Max Unit t 1 Shared s ignal inp ut setu p time 7 – ns t 2 Shar.
6-28 Electrical Sp ecificat ions Figure 6.19 Burst Read, 32-Bit Address and Data t 1 t 2 CLK GPIO0_FETCH/ (Driven by LSI53C875A) GPIO1_M ASTER/ (Driven by LSI53C875A) REQ/ (Driven by LSI53C875A) PA R .
PCI and Ex ternal Memo r y Interf ace Timin g Diag rams 6-29 T able 6.26 Burst Read, 64 -Bit A ddress and Da ta Symb ol P arame ter M in Max Un it t 1 Shar ed si gnal in put se tup ti me 7 – ns t 2 .
6-30 Electrical Sp ecificat ions Figure 6.20 Burst Read, 64-Bit Address and Data t 1 t 2 CLK GPIO0_FETCH/ (Driven by LSI53C875A) GPIO1_M ASTER/ (Driven by LSI53C875A) REQ/ (Driven by LSI53C875A) PA R .
PCI and Ex ternal Memo r y Interf ace Timin g Diag rams 6-31 T able 6.27 Bur st Write , 32-Bit Address and Data Symb ol P arame ter Min Max Unit t 1 Shared s ignal inp ut setu p time 7 – ns t 2 Shar.
6-32 Electrical Sp ecificat ions Figure 6.21 Burst Write, 32-Bit Addr ess and Data t 1 CLK (Dr iv en by Syst em) GPIO0_FET CH/ (Driven by LSI53C875A) GPIO 1_MASTER / (Driven by LSI53C875A) REQ/ (Drive.
PCI and Ex ternal Memo r y Interf ace Timin g Diag rams 6-33 T a ble 6 .28 Bur st Wri te, 64- Bit A ddr ess and 32- Bit D ata Symb ol P arame ter M in Max Un it t 1 Shar ed si gnal in put se tup ti me.
6-34 Electrical Sp ecificat ions Figure 6.22 Burst Write, 64-Bit Addr ess and 32-Bit Data t 1 CLK (Dri v en b y Syst em) GPIO0_F ETCH/ (Driven by LSI53C875A) GPIO1_M ASTER/ (Driven by LSI53C875A) REQ .
PCI and Ex ternal Memo r y Interf ace Timin g Diag rams 6-35 6.4. 3 External M emory Timing The tables an d figures in th is sect ion des cr ibe LSI 53C875 A e xter na l timin gs. The Ext er nal Me mor y W rit e timin gs st ar t o n page 6 -40 . T a ble 6 .
6-36 Electrical Sp ecificat ions Figure 6.23 External M emory Read 12 3 4 5 6 7 8 9 CLK (Driven by System) PA R (Dr iv en by Master-Addr ; IRD Y/ (Driven by Master) TRD Y/ (Driven by LSI53C875A) ST OP.
PCI and Ex ternal Memo r y Interf ace Timin g Diag rams 6-37 Figure 6.23 External Me mory Read (Cont.) MAD (Addr dr iv en by LSI53C875A; Data driven by Memor y) 11 12 13 14 15 16 17 18 19 20 21 10 CLK.
6-38 Electrical Sp ecificat ions T a ble 6 .30 Ext erna l Memo ry Write Symb ol P arame ter Min Max Unit t 1 Shared s ignal inp ut setu p time 7 – ns t 2 Shared sig nal input hold time 0 – ns t 3 .
PCI and Ex ternal Memo r y Interf ace Timin g Diag rams 6-39 The Ex ter nal Memor y Wr ite timi ngs star t on pa ge 6-40 ..
6-40 Electrical Sp ecificat ions Figure 6.24 External M emory Write 12 3 4 5 6 78 9 CLK (Driven by System) PA R (Dr iv en by Master-Addr ; IRD Y/ (Driven by Master) TRD Y/ (Driven by LSI53C875A) ST OP.
PCI and Ex ternal Memo r y Interf ace Timin g Diag rams 6-41 Figure 6.24 External M emory Write (Cont.) MAD (Addr dr iv en by LSI53C875A; Data driven by Memor y) 11 12 13 14 15 16 17 18 19 20 21 10 CL.
6-42 Electrical Sp ecificat ions Figure 6.25 Normal/Fast Memory ( ≥ = 128 K b ytes) S ingle By te Access Read Cycle T able 6.31 Normal/Fast Memory ( ≥ = 128 Kbytes) Sin gle Byte A ccess Read Cycle.
PCI and Ex ternal Memo r y Interf ace Timin g Diag rams 6-43 Figure 6.26 Normal/Fast Memory ( ≥ = 128 K b ytes) S ingle By te Access Writ e Cycle T able 6.
6-44 Electrical Sp ecificat ions Figure 6.27 Normal/Fast Memory ( ≥ = 128 Kbytes) M ultiple Byte Access R ead Cycle MAD (Addr D riven by LSI53C87 5A; MAS1/ (Driven by LSI53C875A) MAS0/ (Driven by LS.
PCI and Ex ternal Memo r y Interf ace Timin g Diag rams 6-45 Figure 6.27 Normal/Fast Memory ( ≥ = 128 Kbytes) M ultiple Byte Access R ead Cycle (Cont.
6-46 Electrical Sp ecificat ions Figure 6.28 Normal/Fast Memory ( ≥ = 128 Kbytes) M ultiple Byte Access W rite Cycle MAD (Dr iv en b y LSI53C8 75A) MAS1 / (Dr iv en b y LSI53C8 75A) MAS0 / (Dr iv en.
PCI and Ex ternal Memo r y Interf ace Timin g Diag rams 6-47 Figure 6.28 Normal/Fast Memory ( ≥ = 128 Kbytes) M ultiple Byte Access W rite Cycle (Cont.
6-48 Electrical Sp ecificat ions Figure 6.29 Slow Me mory ( ≤ = 128 Kbytes) Read Cycle T able 6.33 Slo w Mem ory ( ≤ = 128 Kbytes) Read C ycle Symb ol P arame ter Min Max Unit t 11 Address s etup .
PCI and Ex ternal Memo r y Interf ace Timin g Diag rams 6-49 Figure 6.30 Slow Me mory ( ≤ = 128 Kb yt es) Wri te Cyc le T able 6.34 Slo w Mem ory ( ≤ 128 Kb ytes) W rite C yc le Symb ol P arame te.
6-50 Electrical Sp ecificat ions Figure 6.31 ≤ 64 Kbytes ROM Re ad Cycle Ta b l e 6 . 3 5 ≤ = 64 Kbytes ROM Read Cycle Symb ol P arame ter Min Max Unit t 11 Address s etup to MAS/ H IGH 25 – ns .
PCI and Ex ternal Memo r y Interf ace Timin g Diag rams 6-51 Figure 6.32 ≤ 64 Kbyte ROM Write C ycle Ta b l e 6 . 3 6 ≤ = 64 Kbyte ROM Writ e Cycle Symb ol P arame ter Min Max Unit t 11 Address s .
6-52 Electrical Sp ecificat ions 6.5 S CSI T iming Diagrams The tables and diagrams in this secti on descr ibe the LS I53C875A SC SI timin gs. Figure 6.
SCSI Timing Diagr ams 6-53 Figure 6.34 Initiator As ynchr onous Receive T able 6.38 Initiator Asynchronous Receive Symb ol P arame ter Min Max Unit t 1 SA CK/ ass er ted from SRE Q/ asse r ted 5 – n.
6-54 Electrical Sp ecificat ions Figure 6.35 T arget Asynchr onous Send T ab le 6.39 T ar get Asynchr onous Send Symb ol P arame ter Min Max Unit t 1 SREQ/ dea sser ted from SA CK/ asse r ted 5 – ns.
SCSI Timing Diagr ams 6-55 Figure 6.36 T arget Asynchr onous Re ceive T able 6.40 T arget Asynchr onous Receive Symb ol P arame ter Min Max Unit t 1 SREQ/ dea sser ted from SA CK/ asse r ted 5 – ns .
6-56 Electrical Sp ecificat ions T able 6.42 SCSI-2 Fast T r ansfers 10.0 Mbytes (8-Bi t T rans f ers) or 2 0.0 Mbytes (16-Bit T ransfers) 40 MHz Cloc k Symb ol P arame ter Min Max Unit t 1 Send SREQ/.
SCSI Timing Diagr ams 6-57 Figure 6.37 Initiator a nd T arget Synchronou s T ransfer SREQ/ or SACK/ Send Data SD[15:0]/, SDP[1:0]/ Receiv e Data SD[15:0]/, SDP[1:0]/ t 3 t 4 t 1 t 2 t 5 t 6 nn + 1 V a.
6-58 Electrical Sp ecificat ions 6.6 P ac kage Dia grams This s ection o f the manual has a packag e drawing and pino ut for both the PQFP and BGA . Figure 6 .38 LSI5 3C875A 160-Pin PQFP Mechanical Dra wing Important: This drawing may not be the latest version.
P ackage D iagra ms 6- 59 Figure 6.38 160-pin PQ FP (P3) Mechanic al Drawing (Sheet 2 of 2) Important: This drawing may not be the latest version. For board lay out and m anufacturing, obtain the most recent eng ineering drawings fr om your LSI L ogic marketing representati ve by requesting the outline d rawing f o r packa ge code P 3.
6-60 Electrical Sp ecificat ions T able 6.44 160 P QFP Pin List b y Location NC 121 NC 122 VSSIO 123 NC 124 NC 125 TE ST_H SC / 126 TE ST_R ST/ 1 27 VDDIO 128 VDD A 129 TCK 130 TRST/ 131 VSSA 132 VSSI.
P ackage D iagra ms 6- 61 Figure 6.39 169-Pin BGA Mechanical Drawing Important: This drawing may not be the latest version. For board lay out and m anufacturing, obtain the most recent eng ineering drawings fr om your LSI L ogic marketing representati ve by requesting the outline d rawing f o r packa ge code G V .
6-62 Electrical Sp ecificat ions T able 6.4 5 169 BGA Pin List by L oc ation VSSIO K12 SIO K13 PCI_AD[9] L1 PCI_AD[8] L2 PCI_AD[4] L3 PCI_AD[2] L4 VDDCORE L5 VSSCORE L6 MAD[ 7] L7 MAD[ 1] L8 GPIO[4] L.
LSI53C8 75A PCI to Ultra SCSI Controller A-1 Appendix A Regi ster S ummar y T able A.1 LSI53C875A PCI Re gister Map Register Nam e Address Read /Write P age Base Addres s Regis ter One (ME MOR Y) 0x14.
A-2 Register Summ ar y P ow er Manage ment Capabi lities (PM C) 0x4 2–0x4 3 Read Only 4- 15 P ow er Manage ment Con trol/Stat us (PMCSR) 0x44–0 x45 Read /Write 4-16 Reser ved 0x28 –0x 2B – 4-1.
Regis ter Summary A-3 DMA C omma nd (DC MD) 0x 27 Read/ Wr ite 4- 63 DMA Control (DCNTL) 0x3B Read/Write 4 -70 DMA FIFO (DFIFO) 0x20 Read/Write 4-57 DMA Interrupt Enab le (DIEN) 0x39 Read/Write 4-69 D.
A-4 Register Summ ar y Remai ning Byt e Count (RBC ) 0xC8–0x CB Read/Write 4-105 Reser ved 0x53 – 4-94 Reser ved 0x5A –0x5 B – 4-99 Reser ved 0xBC –0x BF – 4-103 Reser ved 0xDB – 4-108 R.
Regis ter Summary A-5 SCS I Inte rr upt E nable Zer o (SI EN0) 0x40 Rea d/W rit e 4-73 SCSI Interrupt Stat us One (SIST1) 0x43 Read Only 4-78 SCSI Interrupt Stat us Zero ( SIST0) 0x42 Read Only 4-76 S.
A-6 Register Summ ar y.
LSI53C8 75A PCI to Ultra SCSI Controller B-1 Appendix B External Memory Interface D iagram Examples Appen dix B has e xamp le e x ter nal mem or y inter f a ce diagrams.
B-2 External Memor y Interf ace Diagram Ex amples Figure B.2 64 Kb yte Interf ace with 150 ns Memory LSI53C875A 27C512-15/ MOE/ OE MCE/ CE D0 8 MAD[7:0] Bus CK Q0 8 A[7:0] QE 6 A[15:8] V DD MAS0 / MAS1 / Note: MAD 3, 1, 0 pulled LOW internally . MA D b us sense logic enabled f or 64 Kbyte of f ast memor y (150 ns de vices @ 33 MHz).
External Memory Interf ace Diagr am Example s B-3 Figure B.3 128 Kb yte s, 256 Kb y tes, 512 Kbytes, or 1 Mb yte Interface w ith 150 ns Memor y LSI53C875A 27C020-15/ MOE/ OE MCE/ CE 8 MAD[7:0] Bus 8 A[7:0] 6 A[15:8] V DD MAS0/ MAS1/ Note: MAD[2:0] pulled LOW internally .
B-4 External Memor y Interf ace Diagram Ex amples Figure B .4 512 Kb yte Interface w ith 150 ns Memory OE WE D[7:0] A0 A16 . . . LSI53C875A MOE/ 8 MAD[7:0] Bus A[7:0] D0 CK Q0 QE 8 A[15:8] V DD MAS0/ MAS1/ Note: MAD2 pulled LOW internally .
LSI53C8 75A PCI to Ultra SCSI Controller IX-1 Inde x Sym bol s (64T IMOD) 4- 97 (A7) 5-23 (AAP) 4-2 2 (ABRT) 4-40 , 4-48 (ACK) 4-37 , 4- 39 (ADB) 4-23 (ADCK) 4-60 (ADDER) 4-73 (AESP) 4-24 (AIP) 4-43 (.
IX-2 In de x (ERBA) 4-1 2 (ERL) 4- 67 (ERM P) 4-68 (ESA) 4-1 06 (EWS ) 4-2 9 (EXC) 4-2 3 (EXT) 4-90 (FBL3) 4- 59 (FE) 4- 82 (FF[ 3:0]) 4- 43 (FF4 ) 4-4 6 (FFL ) 4-5 3 (FLF) 4-56 (FLSH ) 4-51 (FM) 4-5 .
Inde x IX-3 (SGE) 4-7 4 , 4-77 (SI) 4-51 (SID) 4-1 1 (SIEN0) 4- 73 (SIEN1) 4- 75 (SIGP) 4- 49 , 4-54 (SIOM) 4-67 (SIP) 4-50 (SIR) 4-4 0 (SIST 0) 4-76 (SIST 1) 4-78 (SLB) 4-8 9 (SLPAR) 4-79 (SLPHBEN) 4.
IX-4 In de x burst ( Cont.) length ( BL[1:0]) 4- 66 length b it 2 (B L2) 4-61 opcode fet ch enab le (BOF) 4-6 8 size selection 2-6 bus comma nd and byte enables 3- 5 fault (B F) 4-4 0 , 4-69 byte coun.
Inde x IX-5 DMA interru pt (Con t.) pendin g (DI P) 4-50 mode ( DMOD E) 4-66 SCRIPTS pointer ( DSP) 4-64 pointer save (DSPS) 4- 65 status ( DSTAT) 4- 39 DMA next address (DNAD) 4-64 addre ss 64 (DNA D.
IX-6 In de x IDSEL 2-3 , 3-6 signal 2- 5 illega l instructio n detec ted (IID) 4-40 , 4-69 immedia te arbitra tion (IARB) 4-2 4 data 5-23 indirect add ressi ng 5-6 initialization device se lect 3-6 in.
Inde x IX-7 memo ry (Cont .) read li ne co mmand 2- 6 read multiple 2- 10 , 2-11 read multiple comm and 2-6 space 2-2 , 2-3 to me mory 2-16 to me mory move s 2-1 6 write 2-10 , 2-11 write and invalida.
IX-8 In de x reset 3-4 input 6- 10 SCSI offset (ROF) 4-89 response ID one (RESPID1) 4-86 response ID zero (RESPID0) 4-86 return inst ruction 5-27 revision ID (RID) 4- 6 ROM flash and memory interface .
Inde x IX-9 SEL 2-39 select 2-17 instruction 5-16 with ATN/ 5- 20 with SA TN/ on a sta rt sequ ence (WAT N) 4-22 selected (SEL) 4-7 4 , 4-77 selection or r eselectio n time-o ut (S TO) 4- 75 , 4-79 se.
IX-10 Inde x Ultra SCSI (Cont.) single-e nded tr ansfer s 20.0 M bytes (16-b it tr ansfers ) quadr upled 4 0 MHz clock 6-56 20. 0 Mbyt es (8-b it tran sf ers) 40 MHz clo ck 6-56 sync hronous dat a tra.
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デバイスLSI LSI53C875Aの購入後に（又は購入する前であっても）重要なポイントは、説明書をよく読むことです。その単純な理由はいくつかあります：
LSI LSI53C875Aをまだ購入していないなら、この製品の基本情報を理解する良い機会です。まずは上にある説明書の最初のページをご覧ください。そこにはLSI LSI53C875Aの技術情報の概要が記載されているはずです。デバイスがあなたのニーズを満たすかどうかは、ここで確認しましょう。LSI LSI53C875Aの取扱説明書の次のページをよく読むことにより、製品の全機能やその取り扱いに関する情報を知ることができます。LSI LSI53C875Aで得られた情報は、きっとあなたの購入の決断を手助けしてくれることでしょう。
LSI LSI53C875Aを既にお持ちだが、まだ読んでいない場合は、上記の理由によりそれを行うべきです。そうすることにより機能を適切に使用しているか、又はLSI LSI53C875Aの不適切な取り扱いによりその寿命を短くする危険を犯していないかどうかを知ることができます。
ですが、ユーザガイドが果たす重要な役割の一つは、LSI LSI53C875Aに関する問題の解決を支援することです。そこにはほとんどの場合、トラブルシューティング、すなわちLSI LSI53C875Aデバイスで最もよく起こりうる故障・不良とそれらの対処法についてのアドバイスを見つけることができるはずです。たとえ問題を解決できなかった場合でも、説明書にはカスタマー・サービスセンター又は最寄りのサービスセンターへの問い合わせ先等、次の対処法についての指示があるはずです。
