ARMメーカーVERSION 1.2の使用説明書/サービス説明書
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Co pyr igh t © 200 0, 20 01 AR M L im ited . Al l rig hts re s erved . ARM DU I 00 68 B AR M ® D e v eloper Suite V er si on 1. 2 Asse mb ler Gui de.
ii C opyr igh t © 200 0, 20 01 AR M L im ited . A ll rig hts re s erved . ARM DU I 00 68 B ARM Deve loper Suite Assem bler Guide Copyri ght © 200 0, 2001 ARM Limite d. Al l rights reserv ed. Rel eas e I nf orm ati on The fol lo win g changes hav e be en mad e to t his boo k.
ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. iii Contents ARM Developer S u i t e Assembler Guide Pre face Abou t this boo k ... ... ..... .. ..... .. ..... ... ..... .. ..... .. ..... ... ..... .. ..... .. ...
Co nten ts iv C opyr igh t © 200 0, 20 01 AR M L im ited . A ll rig hts re s erved . ARM DU I 00 68 B 3.2 F orm at of s ou rce lin es . .... ... ..... .. ..... .. ..... ... ..... .... ... ..... .. ..... ... .... ... ..... .. ..... .. .. 3 -8 3.3 Predef ined re gister and coproce ssor nam es .
ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. v Pref ace This pref ace introd uces the docum entation for th e A RM D ev el ope r Su i te (ADS) asse mbler s and assembly la nguage. It co ntains the foll owing secti ons: • About this book on page vi • F eedbac k on pa g e ix.
Pr efa ce vi C opyr igh t © 200 0, 20 01 AR M L im ited . A ll rig hts re s erved . ARM DU I 00 68 B Ab out th is boo k This book pro vides tutori a l and referenc e informat ion for the ADS assemble rs ( armasm , the free -sta nding ass embler , an d i nline a ssembler s in the C and C++ compi lers ).
Pr efac e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. vii T ypographi cal conventions The fol lowi ng typographic al con vent ions are used in this b ook: monospace Denote s te xt that can be en tered at t he ke yboard, suc h as commands , fi le and progra m names, and sourc e code.
Pr efa ce vi ii C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B • ADS Link e r and Util ities Gui de (ARM DUI 01 51) • C ode W a rri or I DE G uid e (ARM DU.
Pr efac e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. ix Feed back ARM Limite d welcomes feedback on bot h ADS and the document ation. Feedback on the ARM Developer Su ite If you ha ve any pro blems wit h ADS, please cont act your supp lier .
Pr efa ce x C opyr igh t © 200 0, 20 01 AR M L im ited . A ll rig hts re s erved . ARM DU I 00 68 B.
ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 1-1 Chapter 1 Intr oduction This cha pter int roduces the ass emblers pr ov ided with ARM Dev eloper Sui te (ADS) ver s i on 1.2. It co ntains the foll owing secti ons: • About the ARM Develo per Suit e assemblers on page 1-2.
Int rod ucti on 1-2 C op yri ght © 2 000, 20 01 A RM Lim it ed. A ll rig hts r es erv ed. AR M D UI 0068 B 1 .1 About the AR M Deve loper Su ite assem blers ARM Dev eloper Sui te (ADS) has: • a fre estandi ng ass embler , armasm • an o pti miz i ng in lin e as sem b le r built in t o the C and C++ co mpil ers .
ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 2-1 Chapter 2 Writing ARM a nd Th umb A ssembl y Langua g e This cha pter pro vides an intr oducti on to the gene ral prin ciple s of writing ARM and Thumb as sembly la nguage .
Wri tin g ARM and Th umb A sse mbly Lan guag e 2-2 C op yri ght © 2 000, 20 01 A RM Lim it ed. A ll rig hts r es erv ed. AR M D UI 0068 B 2.1 I nt rod uc tio n This cha pter gi ves a basic, practi cal unders tandi ng of ho w to wr ite ARM and Thumb asse mbly langua ge modul es.
Wri tin g ARM and Thumb A ssemb ly La ngua ge ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 2-3 2. 2 Ove rview o f the A RM ar c hitect ure This se ction gi ves a brie f ove rvie w of the ARM archite cture.
Wri tin g ARM and Th umb A sse mbly Lan guag e 2-4 C op yri ght © 2 000, 20 01 A RM Lim it ed. A ll rig hts r es erv ed. AR M D UI 0068 B 2.2.3 Processor m ode ARM proc e ss ors su pport up to se ven processor m o des, de pendin g on t he archi tecture ver sion .
Wri tin g ARM and Thumb A ssemb ly La ngua ge ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 2-5 In User mode, r14 is used as a l ink r egi s t er (lr) to store the return address when a subro utine call is made.
Wri tin g ARM and Th umb A sse mbly Lan guag e 2-6 C op yri ght © 2 000, 20 01 A RM Lim it ed. A ll rig hts r es erv ed. AR M D UI 0068 B 2.2.5 ARM ins truction se t overview All ARM ins tructi ons are 32 bit s long.
Wri tin g ARM and Thumb A ssemb ly La ngua ge ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 2-7 Single register load an d store instructions The se inst ruc tio ns l o ad or st ore t he val ue of a sin gle regi ster fr om or t o me mo ry .
Wri tin g ARM and Th umb A sse mbly Lan guag e 2-8 C op yri ght © 2 000, 20 01 A RM Lim it ed. A ll rig hts r es erv ed. AR M D UI 0068 B 2.2.6 ARM ins t ruction capabilities The fol lowi ng genera l points appl y to ARM instruc tions : • Con ditiona l execu tion • Re gi ster access • Acc ess t o the inli ne barr el shif ter .
Wri tin g ARM and Thumb A ssemb ly La ngua ge ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 2-9 2.2.7 Thumb instruction set overv iew The functi onality of the Thumb instru ction set is a lmost e xactly a su bset of the funct i ona lity of the ARM in s truc tion set .
Wri tin g ARM and Th umb A sse mbly Lan guag e 2-1 0 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B Ref er t o Chap ter 5 Thumb In struct ion R efer ence for a c omple te lis t of t he Thumb dat a proce ssing instru c t ions that ca n access the high reg isters .
Wri tin g ARM and Thumb A ssemb ly La ngua ge ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 2-1 1 Single register load an d store instructions Thes e inst ructio ns l oad or s tore t he v alu e of a sin gle lo w re gist er f ro m or to memo ry .
Wri tin g ARM and Th umb A sse mbly Lan guag e 2-1 2 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 2 .3 Struct ure of ass embl y l angua ge modul es Assem bly langua ge is the la nguage th at the ARM assemble r ( armasm ) parses and asse mbles to prod uce obje ct code.
Wri tin g ARM and Thumb A ssemb ly La ngua ge ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 2-1 3 La bels Labels are s ymbol s tha t repr esent a ddresses. T he add ress gi ven b y a labe l is calcula ted dur ing asse mbly .
Wri tin g ARM and Th umb A sse mbly Lan guag e 2-1 4 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B Co nst ant s C ons ta nt s ca n b e nu m eri c, bo ole an ,.
Wri tin g ARM and Thumb A ssemb ly La ngua ge ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 2-1 5 2.3.2 An example ARM assem bl y language modul e Exampl e 2-1 ill ustrates some of the core co nstituents of an a ssembly l a n guage modul e.
Wri tin g ARM and Th umb A sse mbly Lan guag e 2-1 6 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B In an ARM asse mbly languag e source f ile, the sta rt of a sectio n is marked by the AR EA dir ect ive. Thi s dir ec tive name s th e se ctio n an d se ts its a ttr ibutes .
Wri tin g ARM and Thumb A ssemb ly La ngua ge ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 2-1 7 2.3.3 Calli ng s ubrou tine s T o call subro utines, u se a branch and link in s t ructi on.
Wri tin g ARM and Th umb A sse mbly Lan guag e 2-1 8 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 2.3.4 An exam ple Th umb ass embly langu a ge mod ule Example 2-3 illus trate s some of the core cons titu e nt s of a Thum b assembly la nguage modul e.
Wri tin g ARM and Thumb A ssemb ly La ngua ge ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 2-1 9 2. 4 Usin g the C p repr ocesso r Y ou can include the C preproc essor command #include in your asse m bly la nguage sourc e f ile.
Wri tin g ARM and Th umb A sse mbly Lan guag e 2-2 0 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 2 .5 Condit ional e xecu tion In ARM s tate , each da ta pr.
Wri tin g ARM and Thumb A ssemb ly La ngua ge ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 2-2 1 2.5.2 Execution co nditions The relat ion of conditio n code s uf fix e s to the N , Z , C and V flag s is shown in T a ble 2- 1.
Wri tin g ARM and Th umb A sse mbly Lan guag e 2-2 2 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 2.5.3 Using conditional execution in ARM state Y ou can use condi tional ex ecution of ARM i nstructions to reduce t he number of branch inst ructi ons in your cod e.
Wri tin g ARM and Thumb A ssemb ly La ngua ge ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 2-2 3 Beca use of the numb er of branches, th e cod e is se ven ins truct ions lo ng. Ev ery time a branc h is tak en, the pr oc es sor mus t ref ill the pi peline and conti nue from the ne w loca tion.
Wri tin g ARM and Th umb A sse mbly Lan guag e 2-2 4 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B Co n vert ing t o Thumb Beca use B is the only T humb inst ruction that c an be e xecu ted c onditi ona l ly , the gcd algori thm must be w r itten with con ditiona l branch es in Thumb code.
Wri tin g ARM and Thumb A ssemb ly La ngua ge ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 2-2 5 2 .6 Loadi ng con stant s into r egiste rs Y ou cannot l oad an a rbit rary 3 2-bit im mediate consta nt into a regi ster i n a singl e inst ructi on witho ut perform ing a data load fr om memory .
Wri tin g ARM and Th umb A sse mbly Lan guag e 2-2 6 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 2.6.1 Direct loading with MO V and M VN In ARM state, you c.
Wri tin g ARM and Thumb A ssemb ly La ngua ge ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 2-2 7 Direc t l oading w it h MO V in T humb st ate In Thumb st ate you can use t he MOV ins tr uction to l oad c onst ants i n the ra nge 0 -255.
Wri tin g ARM and Th umb A sse mbly Lan guag e 2-2 8 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B P lac in g li te ral poo ls The a ssem bler pl aces a liter al p ool at the end of eac h secti on.
Wri tin g ARM and Thumb A ssemb ly La ngua ge ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 2-2 9 LDR r2, =0xFFFFFFFF ; => MVN R2, #0 MOV pc, lr LTORG ; Lite.
Wri tin g ARM and Th umb A sse mbly Lan guag e 2-3 0 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 2 .7 L o ading addr ess es into regist ers It is oft en necessa ry to load an addre s s int o a re gister .
Wri tin g ARM and Thumb A ssemb ly La ngua ge ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 2-3 1 Not e T he label us ed with ADR or ADRL mu st be w ith in th e sam e cod e se ctio n. Th e ass em bler f aults refe rences to l abels tha t are out of range in the same sec tion.
Wri tin g ARM and Th umb A sse mbly Lan guag e 2-3 2 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B Implementing a jump table with ADR Example 2-7 on page 2-33 sho ws ARM code that i mplements a j ump table. It is suppl ied as jump.
Wri tin g ARM and Thumb A ssemb ly La ngua ge ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 2-3 3 Example 2-7 ARM code jump table AR EA Jump, CODE, READONLY ; N.
Wri tin g ARM and Th umb A sse mbly Lan guag e 2-3 4 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B Co n vert ing t o Thumb Example 2-8 sho ws the im plement ation of the jump tab le con vert ed to Thumb code. Most of the Thumb v ersion is the same as the ARM c ode.
Wri tin g ARM and Thumb A ssemb ly La ngua ge ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 2-3 5 2.7.2 Loading addresses wi th L DR Rd, = label The LDR Rd,= pseudo -inst ruction can load any 32-b it consta nt into a re gister .
Wri tin g ARM and Th umb A sse mbly Lan guag e 2-3 6 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B ; Literal Pool 1] LDR r 1, =Darea + 12 ; => LDR R1,[PC, .
Wri tin g ARM and Thumb A ssemb ly La ngua ge ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 2-3 7 An LDR Rd, =label example: string copying Exampl e 2-10 sho ws an ARM c ode routi ne that ov erwrites one strin g with an other stri ng.
Wri tin g ARM and Th umb A sse mbly Lan guag e 2-3 8 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B Co n vert ing t o Thumb There i s no po st-in dex ed ad dressin g mode f or Thumb LDR and STR i nstr ucti ons.
Wri tin g ARM and Thumb A ssemb ly La ngua ge ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 2-3 9 2 .8 L oad and stor e mu ltiple reg iste r instruc tions The AR M and Thumb i nstructi on sets inc lude i nstructi ons that loa d a n d store mu ltipl e reg isters to and from memory .
Wri tin g ARM and Th umb A sse mbly Lan guag e 2-4 0 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 2.8.1 ARM LDM and STM ins t r uctions The l oad (or st or e) m ult ipl e inst ru ctio n l oad s (sto res ) any sub set of th e 1 6 gener al-purpos e re gisters from (to) memor y , using a sing le instruc tion.
Wri tin g ARM and Thumb A ssemb ly La ngua ge ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 2-4 1 Usage See Implementing stac ks wit h LDM an d STM on page 2-42 and B l ock copy wit h LDM and ST M on pa ge 2-4 4.
Wri tin g ARM and Th umb A sse mbly Lan guag e 2-4 2 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 2. 8. 3 I mp lem en ti n g st ack s w it h L DM and STM The load and stor e m u ltiple instructions can upda te the base r egiste r .
Wri tin g ARM and Thumb A ssemb ly La ngua ge ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 2-4 3 Stacking re gisters for nested subroutine s Stack operat ions are v ery u s eful at sub routine entry a n d exi t.
Wri tin g ARM and Th umb A sse mbly Lan guag e 2-4 4 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 2.8.4 Block copy w ith LDM and STM Example 2-11 is an ARM code ro utine tha t copie s a set of words from a source loc ation to a desti na t ion by cop ying a single word at a time.
Wri tin g ARM and Thumb A ssemb ly La ngua ge ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 2-4 5 Exam ple 2-12 AREA Block, CODE, READONLY ; name this block of .
Wri tin g ARM and Th umb A sse mbly Lan guag e 2-4 6 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 2.8.5 Thumb L DM an d S TM instructions The Thumb ins truc .
Wri tin g ARM and Thumb A ssemb ly La ngua ge ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 2-4 7 Exam ple 2-13 AR EA Tblock, CODE, READONLY ; Name this block o.
Wri tin g ARM and Th umb A sse mbly Lan guag e 2-4 8 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 2. 9 Usin g macr os A ma cro de fini tion is a b lock of c ode enc losed be tween MACRO and MEND di rect ives.
Wri tin g ARM and Thumb A ssemb ly La ngua ge ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 2-4 9 2.9.2 Unsig ned integer divisi on macro e xa mple Exampl e 2-14 shows a macro th at performs an unsigned inte ger d ivi s ion.
Wri tin g ARM and Th umb A sse mbly Lan guag e 2-5 0 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B The macr o che cks that no two parame ters use the same re gis ter . It also opt imizes t he code prod uced if onl y the re mainder is requ ired.
Wri tin g ARM and Thumb A ssemb ly La ngua ge ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 2-5 1 2 .10 Desc ribing data st ructure s with MAP an d FIELD d irective s Y ou can use t he MAP and FIELD di rect ives to d escr ibe da ta stru ctu res.
Wri tin g ARM and Th umb A sse mbly Lan guag e 2-5 2 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 2. 10. 1 Re lat ive maps T o access da ta more than 4KB awa.
Wri tin g ARM and Thumb A ssemb ly La ngua ge ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 2-5 3 2.10.2 Reg ister-b ase d maps In man y case s, you c a n use t he same regi ster as the base re gist er ev ery time you access a data structure .
Wri tin g ARM and Th umb A sse mbly Lan guag e 2-5 4 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 2.10.3 P r o gram-r elative maps Y ou can use the program count e r (r15) as t he base re gis ter for a map.
Wri tin g ARM and Thumb A ssemb ly La ngua ge ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 2-5 5 2.10.4 Findin g th e en d of th e allocated data Y ou can u se the FIELD direct iv e with an opera nd of 0 to l abel a lo catio n withi n a stru cture.
Wri tin g ARM and Th umb A sse mbly Lan guag e 2-5 6 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 2. 10. 5 F or ci ng co rr ect al ig nm ent Y ou are lik ely to ha ve prob lems if you inc lude some cha racte r v ariables in the data stru cture, as in Exa mple 2-20.
Wri tin g ARM and Thumb A ssemb ly La ngua ge ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 2-5 7 Exam ple 2-21 StartOfData EQU 0x1000 EndOfData EQU 0x2000 MAP .
Wri tin g ARM and Th umb A sse mbly Lan guag e 2-5 8 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 2.10.6 Using regi ster -b ased MAP and FIELD directives Regi ster-b a sed MAP and FIELD directi ves def ine regi ster -based symbol s.
Wri tin g ARM and Thumb A ssemb ly La ngua ge ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 2-5 9 Setting up a C-typ e structure Ther e ar e tw o sta ges to using str uctur es in C: 1. De clari ng the fi elds th at t he s truc tu re con ta ins.
Wri tin g ARM and Th umb A sse mbly Lan guag e 2-6 0 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B Making faster acce ss possible T o gain fast er ac cess to a sect ion of memo ry: 1. Describe the memory secti on as a structure .
Wri tin g ARM and Thumb A ssemb ly La ngua ge ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 2-6 1 Exampl e 2-23 on page 2-60 conta ins sepa rate LDR pseudo -inst ruction s to load th e addre ss of each of the data i tems.
Wri tin g ARM and Th umb A sse mbly Lan guag e 2-6 2 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B If you us e th e sa me tec hnique f or a s ection of m emor.
Wri tin g ARM and Thumb A ssemb ly La ngua ge ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 2-6 3 2.10.7 Usi ng two register-based structu res Somet imes you need to ope rate on tw o struct ures of the same type at the same tim e.
Wri tin g ARM and Th umb A sse mbly Lan guag e 2-6 4 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 2.10.8 Av o iding problems with MAP and FIELD directives Using MAP and FIELD dir ectiv es can help you to produce maintai nable da ta str uctures.
Wri tin g ARM and Thumb A ssemb ly La ngua ge ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 2-6 5 Exampl e 2-27 on page 2-64 l oads the f irst s ix it e ms in t he arra y Misc_data . The ar ra y is a si ngle ele m ent a nd ther e for e c ove rs con tiguous memory l ocati ons.
Wri tin g ARM and Th umb A sse mbly Lan guag e 2-6 6 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 2. 11 Usin g frame d irectiv es Y ou must use f rame direct.
ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 3-1 Chapter 3 As sem b le r Re f ere nce This chapter provid e s g eneral r e feren ce materi al on the ARM assemblers .
Assembler Re ference 3-2 C op yri ght © 2 000, 20 01 A RM Lim it ed. A ll rig hts r es erv ed. AR M D UI 0068 B 3 .1 Comma nd syntax This sect ion rela tes onl y to armasm . The inline a ss emblers ar e part of the C and C+ + compile rs, an d h av e no command synt ax of their o wn.
Assembler Refere nce ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 3-3 /ropi s peci fies th a t the con t ent of inputfile is rea d-only posit ion-inde pendent . The defa ult is /noropi . /pic i s a sy no nym fo r /ropi .
Assembler Re ference 3-4 C op yri ght © 2 000, 20 01 A RM Lim it ed. A ll rig hts r es erv ed. AR M D UI 0068 B -md instru cts the a ssemble r to w rite so urce f ile depende ncy list s to inputfile.d . -errors errorfile instru cts the assem bler to outpu t e rro r messages to erro rfile .
Assembler Refere nce ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 3-5 -help inst ruct s the a s se m bl er to dis play a su mmary of t he ass e m bler command -li ne options.
Assembler Re ference 3-6 C op yri ght © 2 000, 20 01 A RM Lim it ed. A ll rig hts r es erv ed. AR M D UI 0068 B -nocache tur ns of f sour ce cac hing. By de fault the asse mbler ca ches source fi les on the fi rst pass and reads the m from m emo ry on the second pa ss.
Assembler Refere nce ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 3-7 Not e A v oiding lar ge mult iple regis ter t ransfe rs i ncrea ses c ode si ze and decre ases performanc e slightl y .
Assembler Re ference 3-8 C op yri ght © 2 000, 20 01 A RM Lim it ed. A ll rig hts r es erv ed. AR M D UI 0068 B 3.2 Format of sour ce lin es The general form of s ource line s i n an ARM as sembly la.
Assembler Refere nce ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 3-9 3 .3 Predef ined re gister and copr ocessor n am e s All register an d c op rocesso r names are case -sensit i ve .
Assembler Re ference 3-1 0 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 3.4 Bu i lt- i n vari a bles T a ble 3 -1 li s ts t he bui l t-i n var i able s defi ne d by the A R M a ssem b le r . Built -in v ariab les cannot be set us ing the SETA , SETL , or SETS dir ectiv es.
Assembler Refere nce ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 3-1 1 |ads$version| must be all lo wer case.
Assembler Re ference 3-1 2 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 3.5 S ym bo ls Y ou can use symb ols to re present v aria bles, a ddresse s, and numeri c constan ts. Symbols re pres enti ng add res ses ar e als o c alled label s .
Assembler Refere nce ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 3-1 3 3.5.2 V ar iables The v alue of a v ari abl e can be chan ged as as semb ly pr oceeds . V ar iab les a re of th re e types : • nume ric • logic a l • stri ng.
Assembler Re ference 3-1 4 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 3.5.4 Assem bl y time substitution of variabl es Y ou can use a s tring v ariable for a whole l ine of assembl y langu a ge, or any pa rt of a line.
Assembler Refere nce ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 3-1 5 3.5.5 Labels Labels are symbols rep re sen ting the a d dresses in memory o f ins tructi ons or data . They can be program-re lati ve, regis ter -relati ve , or absolute.
Assembler Re ference 3-1 6 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 3.5.6 Local l abels A local l abel is a number in the range 0-9 9, optiona lly foll ow ed by a name. Th e same numbe r can be used for more tha n one loca l label in an ELF se ction.
Assembler Refere nce ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 3-1 7 If routname is spec ifi ed in ei ther a label or a ref erence to a l abel, the ass embl er che cks it agai nst th e name of the neares t prec eding ROUT direc ti ve.
Assembler Re ference 3-1 8 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 3. 6 Expr essions, lit er a ls, and o perat ors This section contain s th e follo win.
Assembler Refere nce ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 3-1 9 3.6.1 String expressio ns String e xpressions con sist of combin a t ions of strin g lit erals, stri ng va riables, stri ng manipul a t ion operators , and parenth e ses.
Assembler Re ference 3-2 0 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 3.6.3 Num eric expressi ons Numeric e xpr essions con sist of combi nations of numeric co nstants , numeric v aria bles, ordina ry numeri c liter als, binary oper a t ors, and parenthe ses.
Assembler Refere nce ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 3-2 1 3.6.4 Num eric literals Numeri c lite rals can take any of the fo llo wing forms : • .
Assembler Re ference 3-2 2 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 3.6 .5 Fl o atin g -po in t lit er als Floa ting-po int lit erals ca n tak e any of the foll owing forms: {-} digits E{-} digits {-}{ digits }.
Assembler Refere nce ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 3-2 3 3.6.6 Register-relative and program-rel ative exp re ssions A regis ter -rela ti ve expre ssion e v a lu ates to a named re gister plus or minus a numeri c cons tant (see MAP on pa g e 7-1 5 ).
Assembler Re ference 3-2 4 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 3. 6.9 Ope r ator prec e d enc e The as semble r incl udes an e xten si ve s et of operat ors for u se in e xpressions.
Assembler Refere nce ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 3-2 5 Th e hi ghest prec edence opera to rs a re at the top o f th e li st. The highes t precede nce operato rs are ev aluated f irst. Op era tor s of eq ual pr eced en ce are ev a lua ted fro m l eft to ri ght .
Assembler Re ference 3-2 6 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 3.6.10 Un ary operato r s Unary oper a to rs have the highe st preced ence and are e valuat ed fi rst. A unary opera tor prece des its op erand.
Assembler Refere nce ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 3-2 7 Example of use of :SB_OF FSET_19 _12: a nd :SB_OFFSET_1 1_ 0 MyIndex EQU 0 AREA area1, .
Assembler Re ference 3-2 8 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 3.6.11 Binar y operators Binary opera tors are writ ten betwe en the pair of sub expre ssions they opera te on. Binary op erator s hav e lo we r prec edence than u na ry opera tors.
Assembler Refere nce ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 3-2 9 Shift operato r s Shi ft opera tors act on numeric e xpressions, s h ifting or rotating t he fi rst opera nd by th e amou nt specif ied by the s econd.
Assembler Re ference 3-3 0 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B Relational operators T able 3-9 sho ws t he relat ional operators. These act o n two o pe rands of t he same type to produce a logica l va lue.
Assembler Refere nce ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 3-3 1 Boo lean op erat ors The se a re t he o per ato rs wi th t he l o we st pre ced enc e. T hey p er form th e s tan dar d lo gic al opera tions on t he i r opera nds.
Assembler Re ference 3-3 2 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B.
ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 4-1 Chapter 4 ARM Inst ruction Reference This chapter desc ribes the ARM instruc tions tha t are supp orted b y the ARM assemb ler .
ARM Instructi on Reference 4-2 C op yri ght © 2 000, 20 01 A RM Lim it ed. A ll rig hts r es erv ed. AR M D UI 0068 B T able 4-1 Location of ARM inst ructions Mnemoni c Brief descript ion P age Arch .
AR M Inst ruc tio n Refe renc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 4-3 MUL Mu ltip ly pa ge 4-4 0 2 MVN Mo ve not page 4- 32 All ORR Logi cal OR page.
ARM Instructi on Reference 4-4 C op yri ght © 2 000, 20 01 A RM Lim it ed. A ll rig hts r es erv ed. AR M D UI 0068 B 4 .1 Condit ional e xecu tion Almost a l l ARM i nstruc tions ca n includ e an op tional conditi on code. This is sho wn in synt ax descrip tions as { cond } .
AR M Inst ruc tio n Refe renc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 4-5 Some i nstructi ons update a subs et of the flags. T he othe r flags are unchanged b y these ins tr uct ion s. D eta il s are s pec ified in th e des cr ipt ion s of the in str uct io ns.
ARM Instructi on Reference 4-6 C op yri ght © 2 000, 20 01 A RM Lim it ed. A ll rig hts r es erv ed. AR M D UI 0068 B 4. 2 ARM m emory a ccess ins t r uctions This section contain s th e follo wing subsect ions: • LDR and STR, wor ds and un signed byt e s on pa g e 4-7 Load regi ster a nd store r egist er , 32-bit word or 8-bit unsigned byte.
AR M Inst ruc tio n Refe renc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 4-7 4.2.1 LDR an d STR, words and unsi gned bytes Load reg ister and store re gist er , 32- bit w ord or 8 -bit u nsigned byte . Byt e loads a re zero- exte nded to 32 bit s .
ARM Instructi on Reference 4-8 C op yri ght © 2 000, 20 01 A RM Lim it ed. A ll rig hts r es erv ed. AR M D UI 0068 B FlexOffset is a fle xible off s e t appl ied to the v alue i n Rn (see Fle xible o ffs et synt ax on page 4-9). label is a p ro gr am-r ela tive expre ss io n.
AR M Inst ruc tio n Refe renc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 4-9 Flex ible offs et synt ax Both pre - indexe d and post-ind exe d of fsets c a n be e ither of the follo wi ng: # expr {-} Rm {, shift } where: - is a n opti onal min us sign .
ARM Instructi on Reference 4-1 0 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B Address alignm ent f or word transfers In most cir cumstance s, you must ensure t hat addres ses for 32-bi t transfers are 32-bit word-al igned.
AR M Inst ruc tio n Refe renc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 4-1 1 Saving from r15 In general, avoi d sav i ng from r15 if pos sible. If you do sa ve from r15, t he va lue sa ved is the address of the current i nstructi on, plus an impleme ntation-de fine d const ant.
ARM Instructi on Reference 4-1 2 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 4.2.2 LDR and STR, halfwords and sig ned bytes Load regi ster , signe d 8-bit byt es and sig ned and unsigned 16-bi t ha l fwor ds.
AR M Inst ruc tio n Refe renc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 4-1 3 label is a progr am-relati ve exp ression . See Re gister -r ela tive and pr ogr am-r ela tive ex pre ssions on pag e 3-23 for more inform ation.
ARM Instructi on Reference 4-1 4 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B Rm is a regi s ter c ontaini ng a v alue t o b e used as the of fset. The of fset synta x is t he same for LDR and STR, doub lewo r ds o n page 4- 15.
AR M Inst ruc tio n Refe renc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 4-1 5 4.2.3 LDR and STR, dou bl ew ords Load t wo consec uti ve regi ste rs and sto re two con secuti ve re gist ers, 64-bi t dou ble word.
ARM Instructi on Reference 4-1 6 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B Ze r o off set The value in Rn is us ed as th e add ress for t he t ransf er . Pre-indexed offset The of fset i s app lied t o the va lue in Rn bef or e the tra nsf ers t ake p lac e.
AR M Inst ruc tio n Refe renc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 4-1 7 If your system has a sys tem c oprocess or , you can e na bl e align m ent checking . Non double word-aligne d 64-bit trans fers caus e an alignment e xcepti on if align ment che ck ing is ena ble d.
ARM Instructi on Reference 4-1 8 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 4.2.4 LDM and ST M Load and st ore mult iple regi ster s. An y c ombinatio n of re gisters r0 t o r15 can b e transferred . Syn tax op { cond } mode Rn {!}, reglist {^} where: op is ei ther LDM or STM .
AR M Inst ruc tio n Refe renc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 4-1 9 Non word-aligned addresses These i nstructi ons ignor e bits [1:0] of the addre ss .
ARM Instructi on Reference 4-2 0 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 4.2.5 PLD Cach e pr el oad . Syn tax PLD [ Rn {, FlexOffset }] where: Rn is the re gister on whic h the memory address is based . FlexOffset is an opt ional f le xibl e offs et app lied to th e val ue in Rn .
AR M Inst ruc tio n Refe renc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 4-2 1 Usage Use PLD to hint t o t he memory syste m t hat there is like ly to be a l oad fr om th e spec if ied addre ss within th e next fe w instructi ons.
ARM Instructi on Reference 4-2 2 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 4.2.6 SWP Swap dat a between re gist ers and memory . Use SWP to imple ment sema phores. Syn tax SWP{ cond }{B} Rd , Rm , [ Rn ] where: cond is an opt ional co ndition code (see Conditi onal e xecution on pa ge 4-4) .
AR M Inst ruc tio n Refe renc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 4-2 3 4 .3 ARM ge neral d ata pr ocessing in struct ions This sect ion cont ains t.
ARM Instructi on Reference 4-2 4 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 4.3.1 Flexible second operan d Most ARM gene ral da ta pro cessi ng ins truct ions hav e a flex ible secon d op erand. T his i s shown a s Operand2 in the descri ptions of the synt ax of eac h instruc tion.
AR M Inst ruc tio n Refe renc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 4-2 5 ASR Ari thmet ic shi ft rig ht by n bits di vides the v alue con taine d i n Rm by 2 n , if th e con ten ts are reg ard ed a s a two ’ s com plement sign ed int eger .
ARM Instructi on Reference 4-2 6 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B Figur e 4-2 RRX The carr y flag The car ry flag i s update d to the l ast bit s.
AR M Inst ruc tio n Refe renc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 4-2 7 4.3.2 ADD, SUB, RSB, ADC, SBC, and RSC Add, s u btract , and re ver se s ub tra ct, ea ch wit h or with o ut car ry . Syn tax op { cond }{S} Rd , Rn , Operand2 where: op is one of ADD , SUB , RSB , ADC , SBC , or RSC .
ARM Instructi on Reference 4-2 8 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B Condition fl ags If S is s pecif ied, the se inst ruct ions up date the N, Z , C and V fl ags a ccordi ng to the re sult. Use of r15 If you use r15 as Rn , the v alue u sed is the addre ss of the ins truction plu s 8.
AR M Inst ruc tio n Refe renc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 4-2 9 ADDS r4,r0,r2 ; adding the lea st significant words ADC r5,r1,r3 ; adding th.
ARM Instructi on Reference 4-3 0 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 4.3.3 AND, ORR, EOR, and BIC Logic al AND, OR, Exclusi ve OR and Bi t Clear . Syn tax op { cond }{S} Rd , Rn , Operand2 where: op is one of AND , ORR , EOR , or BIC .
AR M Inst ruc tio n Refe renc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 4-3 1 Use of r15 If you use r15 as Rn , the v alue u sed is the addre ss of the ins truct ion plus 8. If you use r15 as Rd : • Exe cutio n branche s to the address correspond ing to the result.
ARM Instructi on Reference 4-3 2 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 4. 3. 4 MO V an d MV N M ove a n d Move N ot . Syn tax MOV{ cond }{S} Rd , Operand2 MVN{ cond }{S} Rd , Operand2 where: cond is an opt ional co ndition code (see Conditi onal e xecution on pa ge 4-4) .
AR M Inst ruc tio n Refe renc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 4-3 3 Use of r15 If you use r15 as Rn , the v alue u sed is the addre ss of the ins truct ion plus 8. If you use r15 as Rd : • Exe cutio n branche s to the address correspond ing to the result.
ARM Instructi on Reference 4-3 4 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 4.3.5 CM P an d CMN Comp ar e an d Comp are N eg ati v e. Syn tax CMP{ cond } Rn , Operand2 CMN{ cond } Rn , Operand2 where: cond is an opt ional co ndition code (see Conditi onal e xecution on pa ge 4-4) .
AR M Inst ruc tio n Refe renc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 4-3 5 Ar chitectures The se in str uct ion s are avail abl e in al l versi on s of th e ARM arc hit ectu re.
ARM Instructi on Reference 4-3 6 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 4.3.6 TST an d TE Q T es t and T e st E quiv alence. Syn tax TST{ cond } Rn , Operand2 TEQ{ cond } Rn , Operand2 where: cond is an opt ional co ndition code (see Conditi onal e xecution on pa ge 4-4) .
AR M Inst ruc tio n Refe renc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 4-3 7 Ar chitectures The se in str uct ion s are avail abl e in al l versi on s of th e ARM arc hit ectu re.
ARM Instructi on Reference 4-3 8 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 4.3.7 CLZ Cou nt Le ad ing Ze roe s. Syn tax CLZ{ cond } Rd , Rm where: cond is an opt ional co ndition code (see Conditi onal e xecution on pa ge 4-4) .
AR M Inst ruc tio n Refe renc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 4-3 9 4.4 ARM m u ltipl y instructio ns This sect ion cont ains the f ollo wing sub sect ions: • MUL and MLA on pa ge 4-4 0 Multi ply and m ultip ly-acc umulate (32-bit by 32-bit , bott om 32-bit res ult).
ARM Instructi on Reference 4-4 0 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 4.4.1 M UL and ML A Multip ly and mult iply-acc umulate (32 -bit b y 32-b it, bott om 32- bit re sult).
AR M Inst ruc tio n Refe renc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 4-4 1 Examples MUL r10,r2,r5 MLA r10,r2,r1,r5 MULS r0,r2,r2 MULLT r2,r3,r2 MLAVCS .
ARM Instructi on Reference 4-4 2 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 4.4 .2 U MU LL, UM LAL , SMUL L and SM LAL Unsig ned and signe d long multi ply and multi ply accumu late (32 -bit by 32-bi t, 64-bit ac cum u late o r re su lt) .
AR M Inst ruc tio n Refe renc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 4-4 3 Condition fl ags If S is spe cif ied, th ese in stru cti ons: • up date th.
ARM Instructi on Reference 4-4 4 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 4.4.3 SMU Lxy Sign ed multipl y (16-bi t by 16- bit, 32-bi t resu lt). Syn tax SMUL< x >< y >{ cond } Rd , Rm , Rs where: < x > is ei ther B or T .
AR M Inst ruc tio n Refe renc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 4-4 5 Incorrect exam ples SMULBT r15,r2,r0 ; use of r15 not allowed SMULTTS r0,r6,.
ARM Instructi on Reference 4-4 6 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 4.4.4 SMLAxy Sign ed mult iply-accu m ul ate (16- bit b y 16-bit, 32-bit a ccumu late ). Syn tax SMLA< x >< y >{ cond } Rd , Rm , Rs , Rn where: < x > is ei ther B or T .
AR M Inst ruc tio n Refe renc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 4-4 7 Ar chitectures This instr uction is a v ail a bl e in all E va ri ants of ARM arc hit ectur e v5 and abov e.
ARM Instructi on Reference 4-4 8 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 4.4.5 SMU L Wy Sign ed mult iply (32-bi t by 16-bit , top 32 -bit res ult). Syn tax SMULW< y >{ cond } Rd , Rm , Rs where: < y > is ei ther B or T .
AR M Inst ruc tio n Refe renc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 4-4 9 4.4.6 SMLA Wy Sig ned multipl y-accu mulate (32-b it by 16-bi t, top 32-bi t accumul ate). Syn tax SMLAW< y >{ cond } Rd , Rm , Rs , Rn where: < y > is ei ther B or T .
ARM Instructi on Reference 4-5 0 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B Ar chitectures This instr uction is a v ail able in all E v ar iant s of ARM arc hit ectur e v5 and a bov e.
AR M Inst ruc tio n Refe renc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 4-5 1 4.4.7 SMLALxy Sig ned mult iply-ac cumul ate (16- bit by 16- bit, 64-bit accu mula te). Syn tax SMLAL< x >< y >{ cond } RdLo , RdHi , Rm , Rs where: < x > is ei ther B or T .
ARM Instructi on Reference 4-5 2 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B Examp les SMLALTB r2,r3,r7,r1 SMLALBTVS r0,r1,r9,r2 Incorrect exam ples SMLALTT.
AR M Inst ruc tio n Refe renc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 4-5 3 4.4.8 M IA, MIAPH, and MIAxy XSca le c opro cessor 0 inst ructio ns. Multi ply with inte rnal ac cumulat e (32-b it b y 32-bit, 40-b it accu mulate ).
ARM Instructi on Reference 4-5 4 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B The MIAxy instru ction mult iplies the si gned inte ger from the selecte d half of Rs by t he si gne d in t ege r fr om the se le ct ed h alf of Rm , an d adds t he 32- bit r esul t to the 40-bi t va lue in Acc .
AR M Inst ruc tio n Refe renc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 4-5 5 4.5 ARM s aturating arith metic instr uctions The se o perat ion s are saturating ( SAT ).
ARM Instructi on Reference 4-5 6 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B Not e All v alues are t reate d as two ’ s comple m ent s ign ed inte ger s by the se inst ruction s . Condition fl ags The se in str uct ion s do no t affect the N , Z, C, an d V flag s .
AR M Inst ruc tio n Refe renc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 4-5 7 4.6 AR M br an ch ins t ruc ti on s This sect ion cont ains the f ollo wing sub sect ions: • B an d BL o n page 4- 58 Br anch , a nd Bra n ch w ith Li nk • BX on pa g e 4-59 Br anch an d ex cha nge in stru cti on set.
ARM Instructi on Reference 4-5 8 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 4.6.1 B and BL Br anch , a nd Bra nch wi th Lin k. Syn tax B{ cond } label BL{ cond } label where: cond is an opt ional co ndition code (see Conditi onal e xecution on pa ge 4-4) .
AR M Inst ruc tio n Refe renc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 4-5 9 4.6.2 BX Br anch , an d opt ion all y ex chan ge in str uct ion s et. Syn tax BX{ cond } Rm where: cond is an opt ional c onditio n code (see Cond itional exe cution on page 4-4 ).
ARM Instructi on Reference 4-6 0 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 4.6.3 BLX Branc h with Link, and opt ionally e xchange i nstru ction set .
AR M Inst ruc tio n Refe renc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 4-6 1 Ar chitectures This instr uction is a v ail a bl e in all T va ri ants of ARM arc hit ectur e v5 and abov e.
ARM Instructi on Reference 4-6 2 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 4 .7 ARM copr ocesso r inst r u ctions This se ction do es not des cribe V ector Floa ting-po int instruc tions (se e Chapter 6 Ve c t o r Float ing-poin t P r ogrammi ng ).
AR M Inst ruc tio n Refe renc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 4-6 3 4.7.1 CDP , CDP2 Copr ocessor d a t a ope rations.
ARM Instructi on Reference 4-6 4 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 4.7.2 MCR, MCR2, MCRR Mov e to coproce ssor from AR M regist e rs. D epe nding on th e coproc e ss or , you might b e able to spe cify v arious ope rations in a ddition .
AR M Inst ruc tio n Refe renc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 4-6 5 4.7.3 MRC, MRC2 Mov e to ARM re giste r from coprocess or . Dependin g on the copr ocess or , you might be able to spe c i fy va rious ope ration s in addition .
ARM Instructi on Reference 4-6 6 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 4.7.4 MRRC Mov e to tw o ARM reg isters fr om coproc essor . De pendin g on t he coproc essor , you might b e able to spe cify v a ri ous operati ons in additi on.
AR M Inst ruc tio n Refe renc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 4-6 7 4.7.5 LDC , S TC T rans fer da ta betwe en memory a n d copro c essor . Syn tax The se in str uct ion s have th ree p oss ibl e form s : • zero of fset • pre-in dexed of fset • post -inde xed offs et.
ARM Instructi on Reference 4-6 8 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B Ar chitectures LDC and STC ar e a vail abl e in AR M arch ite ctu re v ersi ons 2 a n d abov e.
AR M Inst ruc tio n Refe renc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 4-6 9 4.7.6 LDC 2, STC2 Transf er data b etw een me mo ry a nd cop roc es sor, alte rn ative instr uc tio ns.
ARM Instructi on Reference 4-7 0 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B Ar chitectures LDC2 and STC2 ar e a vail abl e in AR M arch ite ctu re v ersi ons 5 a n d abov e.
AR M Inst ruc tio n Refe renc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 4-7 1 4. 8 Mi scellaneo u s ARM instr uction s This sect ion cont ains the f ollo .
ARM Instructi on Reference 4-7 2 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 4.8.1 SWI Softwar e interrupt. Syn tax SWI{ cond } immed_24 where: cond is an opt ional co ndition code (see Conditi onal e xecution on pa ge 4-4) .
AR M Inst ruc tio n Refe renc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 4-7 3 4.8.2 MRS Move the conten ts of the CPSR or SPSR to a general-pur pose re gist er . Syn tax MRS{ cond } Rd , psr where: cond is an opt ional c onditio n code (see Cond itional exe cution on page 4-4 ).
ARM Instructi on Reference 4-7 4 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 4.8.3 MSR Load speci f ied fields of the CPS R or SPSR with an immediat e c on stant, or f rom the conte nts of a general-p urpose regis ter .
AR M Inst ruc tio n Refe renc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 4-7 5 Example MSR CPSR_f, r5.
ARM Instructi on Reference 4-7 6 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 4.8.4 BKPT Break poin t. Syn tax BKPT immed_16 where: immed_16 is an expre ssion e val uating to an int eger in the range 0-65535 (a 16-bit inte ger).
AR M Inst ruc tio n Refe renc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 4-7 7 4.8.5 M AR, MRA XSca le c opro cessor 0 inst ructio ns. T rans fer betwe en two general -pur pose regi sters an d a 40-bi t internal accu mulator .
ARM Instructi on Reference 4-7 8 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 4 .9 ARM p seudo -ins truct ions The ARM assemble r s u pports a number of p seudo-ins truct ions that are tra nsla ted into the app ropri ate combinat ion of ARM or T humb inst ruc t ions a t assembly t ime.
AR M Inst ruc tio n Refe renc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 4-7 9 4.9.1 ADR ARM pseudo-instruction Load a pr ogram-rela ti ve or re gist er-re lati ve a ddr ess i nto a reg ister . Syn tax ADR{ cond } register , expr where: cond is an opt ional c onditio n code .
ARM Instructi on Reference 4-8 0 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 4.9.2 ADRL ARM pseu do-instru ction Load a p rogra m-r elati ve o r reg is te r- rel at iv e addr ess in to a re gis ter . It is sim il ar to th e ADR pse udo-instruc tion.
AR M Inst ruc tio n Refe renc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 4-8 1 If expr is p rog ram -re la tive, i t m us t evalua te t o an add res s in t he sa me cod e se ct ion as t he ADRL pseud o-inst ructio n.
ARM Instructi on Reference 4-8 2 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 4.9 .3 LD R ARM ps eudo -in struct ion Load a reg ister wi th ei ther: • a 32- bit cons tant value • an ad dr ess . Not e This sect ion descri bes the LD R pse udo -ins tructi on only .
AR M Inst ruc tio n Refe renc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 4-8 3 Usage The LDR pseudo -inst ruction i s used for two main pur poses: • T o .
ARM Instructi on Reference 4-8 4 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 4.9.4 NO P ARM pseud o-instruction NOP generate s the pref erred ARM no-ope ration code .
ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 5-1 Chapter 5 Thumb In struction Refere nce Thi s ch apt er de scri b es the Thu mb in s tru ctio ns th a t are pr ovid ed by t he A RM as sem b ler and the inline ass emblers in the ARM C and C++ compil ers.
Th umb Ins tru ctio n Ref ere nc e 5-2 C op yri ght © 2 000, 20 01 A RM Lim it ed. A ll rig hts r es erv ed. AR M D UI 0068 B T able 5-1 Location of Thumb ins t r uctions and pseu do-instruct ions In.
Thum b Instr uc tio n Ref ere nc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 5-3 ROR Ro ta te r ight pag e 5 -24 4T SBC S ubtra ct wi th c arry pag e 5- 21 .
Th umb Ins tru ctio n Ref ere nc e 5-4 C op yri ght © 2 000, 20 01 A RM Lim it ed. A ll rig hts r es erv ed. AR M D UI 0068 B 5. 1 Thum b memory access in struct ions This section contain s th e follo wing subsect ions: • LDR and STR, imme diate of fset on pa ge 5-5 Load Re gis ter an d Sto re Re gist er .
Thum b Instr uc tio n Ref ere nc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 5-5 5.1.1 LDR and STR, im mediate offset Load Reg iste r and Stor e Re gist er . Addre ss i n memory s peci fied as an i mmedia te of fset from a va lue in a re gister .
Th umb Ins tru ctio n Ref ere nc e 5-6 C op yri ght © 2 000, 20 01 A RM Lim it ed. A ll rig hts r es erv ed. AR M D UI 0068 B Address alig nment f o r word and halfword transfers The address must be divi s ible by 4 for wor d transf ers, and by 2 for ha lfword tra nsfers.
Thum b Instr uc tio n Ref ere nc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 5-7 5.1.2 LDR and STR, re gister offset Load Re gis ter and S tor e Regi ster . Addre ss in memory spec if i ed as a re gis ter -base d offs et f ro m a va lue i n a regi ster.
Th umb Ins tru ctio n Ref ere nc e 5-8 C op yri ght © 2 000, 20 01 A RM Lim it ed. A ll rig hts r es erv ed. AR M D UI 0068 B Address alig nment f o r word and halfword transfers The address must be divi s ible by 4 for wor d transf ers, and by 2 for ha lfword tra nsfers.
Thum b Instr uc tio n Ref ere nc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 5-9 5.1.3 LDR and STR, p c or sp relative Load Reg iste r and Stor e Re gist er . Addre ss i n memory s peci fied as an i mmedia te of fset fr om a val ue in the p c or th e sp .
Th umb Ins tru ctio n Ref ere nc e 5-1 0 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B If your system does no t hav e a s ystem coproces sor (cp15), or alig nment c heckin g is disa bled: • A non-ali gned load corrupt s Rd .
Thum b Instr uc tio n Ref ere nc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 5-1 1 5.1.4 P USH and POP Push lo w regis ters, and opt ionall y the lr , ont o t he stack. Pop lo w regi sters, and optional l y the pc, of f the stack .
Th umb Ins tru ctio n Ref ere nc e 5-1 2 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B POP { reg list , pc} This i nstructi on cause s a branc h to t he address popped o ff the s tac k into the pc.
Thum b Instr uc tio n Ref ere nc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 5-1 3 5.1.5 LDM IA and STMIA Load and store m ultipl e regi ster s. Syn tax op Rn !, { reglist } where: op is ei ther: LDMIA L oad m ult ipl e, i nc rem ent aft er STMIA Store mul tiple , increme nt after .
Th umb Ins tru ctio n Ref ere nc e 5-1 4 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B Examp les LDMIA r3!, {r0,r4} LDMIA r5!, {r0-r7} STMIA r0!, {r6,r7} STMI.
Thum b Instr uc tio n Ref ere nc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 5-1 5 5 .2 Thum b arithm etic instr uction s This sect ion cont ains the f ollo wing sub sect ions: • ADD and SUB, low r e gist ers on pa ge 5-16 Add and subtra ct.
Th umb Ins tru ctio n Ref ere nc e 5-1 6 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 5.2.1 ADD and SUB, low registers Add and subtra c t. Ther e are three forms of these instr uctions that ope rate on lo w registers.
Thum b Instr uc tio n Ref ere nc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 5-1 7 Not e An ADD ins tructi on wit h a n egati ve v alue for expr3 or expr 8 assemb les to the corre spondin g SUB instr uction wi th a pos iti v e cons tant .
Th umb Ins tru ctio n Ref ere nc e 5-1 8 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 5.2.2 ADD, high or l ow registers Add va lues in re gisters, re turning the resul t to the firs t operand re gister . Syn tax ADD Rd , Rm where: Rd is the desti nation reg ister .
Thum b Instr uc tio n Ref ere nc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 5-1 9 5.2.3 ADD and SUB, s p In crem ent or de crem en t sp by an im me diat e co ns tan t.
Th umb Ins tru ctio n Ref ere nc e 5-2 0 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 5. 2.4 ADD, pc or sp relati ve Add an imm ediat e cons tant to the val ue from sp or pc, an d p lace the r esul t into a lo w regi ster .
Thum b Instr uc tio n Ref ere nc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 5-2 1 5.2.5 ADC, SBC, a nd MUL Add with ca rry , Subtr a c t with carry , and Multip ly . Syn tax op Rd , Rm where: op is one of ADC , SBC , or MUL .
Th umb Ins tru ctio n Ref ere nc e 5-2 2 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 5.3 Thumb g eneral d ata pr ocessing in struc tions This section contain s th e follo wing subsect ions: • AND , OR R, EOR , and BIC on page 5-23 Bitwis e l ogical oper ations.
Thum b Instr uc tio n Ref ere nc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 5-2 3 5.3.1 AND, ORR, EOR, and BI C Bitwi s e l ogical operat ions. Syn tax op Rd , Rm where: op is one of AND , ORR , EOR , or BIC .
Th umb Ins tru ctio n Ref ere nc e 5-2 4 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 5.3 .2 A SR, LSL , LS R, and ROR Shif t and rotat e operation s . Thes e inst ruction s can use a va lue cont ained in a re gist er , or an im me diat e shi ft va lu e.
Thum b Instr uc tio n Ref ere nc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 5-2 5 Reg ister- control led shi ft Thes e i nstr u ction s ta ke th e v alue fr om Rd , apply the shi ft to it, and plac e the resul t back int o Rd .
Th umb Ins tru ctio n Ref ere nc e 5-2 6 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 5.3.3 CM P an d CMN Comp ar e an d Comp are N eg ati v e. Syn tax CMP Rn , # expr CMP Rn , Rm CMN Rn , Rm where: Rn is the re gister cont ainin g the fir s t o perand.
Thum b Instr uc tio n Ref ere nc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 5-2 7 Examples CMP r2,#255 CMP r7,r12 ; high register IS a llowed with CMP Rn,R.
Th umb Ins tru ctio n Ref ere nc e 5-2 8 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 5.3.4 M O V , MVN , an d NEG M ove, Move NOT , an d N ega te . Syn tax MOV Rd , # expr MOV Rd , Rm MVN Rd , Rm NEG Rd , Rm where: Rd is the de stinat ion re gis ter .
Thum b Instr uc tio n Ref ere nc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 5-2 9 Condition fl ags MOV Rd ,# expr and MVN inst ru ctio ns up dat e the N and Z fl ags . Th ey have no effe ct on t h e C or V flag s.
Th umb Ins tru ctio n Ref ere nc e 5-3 0 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 5.3.5 TST Te s t b i t s . Syn tax TST Rn , Rm where: Rn is the re gister cont ainin g the fir s t o perand. Rm is the re gister cont ainin g t he second opera nd.
Thum b Instr uc tio n Ref ere nc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 5-3 1 5 .4 Thum b branc h instru ctio ns This sect ion cont ains the f ollo wing sub sect ions: • B on pa ge 5-32 Br anch . • BL on page 5-34 Br anch wit h Link .
Th umb Ins tru ctio n Ref ere nc e 5-3 2 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 5.4.1 B Bra nch. T hi s i s the o nly ins tr uction in th e Thumb inst ruct ion s et t hat c an be condit ional. Syn tax B{ cond } label where: cond is an opt ional condit ion code (see T a bl e 5-2 on page 5-33).
Thum b Instr uc tio n Ref ere nc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 5-3 3 T a bl e 5-2 Condition codes for Thumb B instru ction Suffi x Flags Meani.
Th umb Ins tru ctio n Ref ere nc e 5-3 4 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 5.4.2 BL Long bra nch with Link. Syn tax BL label where: label is a p ro gr am-r ela tive expre ss io n. S ee Re gister -re lativ e and pr ogr am-r ela tive ex pre ssions on page 3-23 for more informati on.
Thum b Instr uc tio n Ref ere nc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 5-3 5 5.4.3 BX Br anch , an d opt ion all y ex chan ge in str uct ion s et. Syn tax BX Rm where: Rm is an ARM regi s t er containi ng the a ddress t o b ranch to.
Th umb Ins tru ctio n Ref ere nc e 5-3 6 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 5.4.4 BLX Branc h with Link, and opt ionally e xchange i nstruct ion set. Syn tax BLX Rm BLX label where: Rm is an ARM regis ter co ntaini ng the addre ss to branch to.
Thum b Instr uc tio n Ref ere nc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 5-3 7 5 .5 Thumb software in terrupt and b reakpo int ins tructi ons This sect ion cont ains the f ollo wing sub sect ions: • SWI • BKP T on page 5-38.
Th umb Ins tru ctio n Ref ere nc e 5-3 8 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 5.5.2 BKPT Break poin t. Syn tax BKPT immed_8 where: immed_8 is an expre ssion e val uating to a n inte ger in the range 0-255.
Thum b Instr uc tio n Ref ere nc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 5-3 9 5 .6 Thum b pseudo -in struc tions The ARM assemble r s upport s a numbe r of Thum b pseudo-in s t ructio ns that are tr anslated into the a ppropria te T humb i nstru ctions a t asse mbly ti m e.
Th umb Ins tru ctio n Ref ere nc e 5-4 0 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 5.6.1 ADR Thumb pseudo-instruction The ADR pseudo- instr uction lo ads a program-rel ati v e addres s into a regi ster . Syn tax ADR register , expr where: register is the re gister to load.
Thum b Instr uc tio n Ref ere nc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 5-4 1 5.6.2 LDR T humb pse udo -ins truct ion The LDR pseudo -inst ruction l oads a lo w regi ster with ei ther: • a 32 -bit cons tant value • an ad dr ess .
Th umb Ins tru ctio n Ref ere nc e 5-4 2 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B • T o loa d a prog ram-rela tiv e or e xternal address into a r egis ter . The a ddress remains va lid rega rdles s of whe r e the link er places the ELF secti on contai ning the LDR .
Thum b Instr uc tio n Ref ere nc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 5-4 3 5. 6.3 NO P T hum b ps eu do-i ns tr uct i on NOP genera tes the pre ferred Thumb no- operation ins truct ion.
Th umb Ins tru ctio n Ref ere nc e 5-4 4 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B.
ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 6-1 Chapter 6 V ector Floating- point Pr ogramming This c ha pter provid e s r e fe rence i nformation about pro gra mming the V ect or Flo ating-p oint c oprocessor in As sembly lang ua ge.
Ve ctor Flo ating- poi nt Pr ogr ammi ng 6-2 C op yri ght © 2 000, 20 01 A RM Lim it ed. A ll rig hts r es erv ed. AR M D UI 0068 B T able 6- 1 Location of d escription s of VFP inst ructi ons Mnemon.
V ecto r Fl oa tin g-poi nt Pro gra mmi ng ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 6-3 FNE G Ne gat e page 6- 16 V ect or All FNM AC Ne gat e - multi pl y.
Ve ctor Flo ating- poi nt Pr ogr ammi ng 6-4 C op yri ght © 2 000, 20 01 A RM Lim it ed. A ll rig hts r es erv ed. AR M D UI 0068 B 6 .1 T h e vecto r f loati ng-p oint co pr ocesso r The V ec tor Fl.
V ecto r Fl oa tin g-poi nt Pro gra mmi ng ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 6-5 6. 2 Float ing-p oint regis ters The V ecto r Floati ng-point c oproce ssor has 32 singl e-precis ion re gist ers, s0 to s31 .
Ve ctor Flo ating- poi nt Pr ogr ammi ng 6-6 C op yri ght © 2 000, 20 01 A RM Lim it ed. A ll rig hts r es erv ed. AR M D UI 0068 B 6.2.2 V ectors A vect or can use up to eight s ingle- precisi on regis ters, or four double -preci sion regi ste rs, from the same b ank.
V ecto r Fl oa tin g-poi nt Pro gra mmi ng ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 6-7 6 .3 V ector an d scalar op erations Y ou can use VFP arithm etic ins tructi ons to operat e: • on sc alars • on vec tors • on scala rs and v ectors toge th er .
Ve ctor Flo ating- poi nt Pr ogr ammi ng 6-8 C op yri ght © 2 000, 20 01 A RM Lim it ed. A ll rig hts r es erv ed. AR M D UI 0068 B 6 .4 VFP an d condi tio n code s Y ou can use a c onditi on code to co ntrol t he ex ecut ion of any VF P ins tructi on.
V ecto r Fl oa tin g-poi nt Pro gra mmi ng ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 6-9 Not e The type of the ins tructi on that la st update d the flags in th e CPSR dete rmines the meaning of c onditio n codes.
Ve ctor Flo ating- poi nt Pr ogr ammi ng 6-1 0 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 6 .5 VFP sys tem re gister s Thr ee VF P s yste m r egi ster s ar.
V ecto r Fl oa tin g-poi nt Pro gra mmi ng ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 6-1 1 bits[1 8:16] LEN is the number o f regis ters u s ed by each v ect or (s ee Ve c t o r s on page 6-6). It is 1 + t he va lue of bits[1 8:16]: 0b000 LEN = 1 .
Ve ctor Flo ating- poi nt Pr ogr ammi ng 6-1 2 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 6. 5.2 FPEXC, th e flo ating -point e xceptio n r egist e r Y ou c an on ly ac ces s th e FPEXC in priv ileged modes .
V ecto r Fl oa tin g-poi nt Pro gra mmi ng ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 6-1 3 6 .6 Flush-to -zer o mod e Some i mplementat ions of VFP use supp ort code t o handle denormali zed numbe rs.
Ve ctor Flo ating- poi nt Pr ogr ammi ng 6-1 4 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 6.6.3 Operations not affected b y flush-to-zero mode The fol lowi.
V ecto r Fl oa tin g-poi nt Pro gra mmi ng ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 6-1 5 6.7 VFP in struct ions This sect ion cont ains the f ollo wing sub sect ions: • F ABS , F CPY , an d FN EG on pa ge 6-16 Flo ating-p oint absolu te v alue , c opy , and negat e.
Ve ctor Flo ating- poi nt Pr ogr ammi ng 6-1 6 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 6. 7.1 F ABS, F CPY , and FN EG Floati ng-point cop y , absol ute v alue, a nd neg ate. Th e se i ns tr uc ti on s c an be s ca la r, vec tor, or mi xe d ( se e V ector and s calar o pe r ations on page 6-7) .
V ecto r Fl oa tin g-poi nt Pro gra mmi ng ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 6-1 7 Examples FABSD d3, d5 FNEGSMI s15, s15.
Ve ctor Flo ating- poi nt Pr ogr ammi ng 6-1 8 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 6.7.2 F ADD an d FSUB Floati ng-point a dd and s ubtrac t. FADD and FSUB can be scala r, vector , or m i xed (see V e c tor and scal ar oper ations on page 6-7) .
V ecto r Fl oa tin g-poi nt Pro gra mmi ng ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 6-1 9 6.7.3 FCMP Fl oa ti ng -po i nt c om pa r e. FCMP is al ways scal ar . Syn tax FCMP{E}< precision >{ cond } Fd , Fm FCMP{E}Z< precision >{ cond } Fd where: E is an optiona l parameter .
Ve ctor Flo ating- poi nt Pr ogr ammi ng 6-2 0 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 6.7.4 FCVTD S Con ve rt singl e-prec isio n fl oatin g-point to double -precision.
V ecto r Fl oa tin g-poi nt Pro gra mmi ng ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 6-2 1 6.7.5 FCVTSD Con ve rt double- pre cis ion f loati ng-point to single -precision.
Ve ctor Flo ating- poi nt Pr ogr ammi ng 6-2 2 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 6.7.6 FDIV Floati ng-point di vi de. FDIV can be sc alar, ve cto r , o r mi xed (see V ector and sca lar oper atio ns on page 6-7) .
V ecto r Fl oa tin g-poi nt Pro gra mmi ng ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 6-2 3 6.7.7 FLD and FST Flo ating-p oint l oa d and store .
Ve ctor Flo ating- poi nt Pr ogr ammi ng 6-2 4 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B FLDSNE s3, [r2, #72+count] FSTS s2, [r5] FLDD d2, [r15, #addr-{PC.
V ecto r Fl oa tin g-poi nt Pro gra mmi ng ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 6-2 5 6.7.8 FLDM and FSTM Flo ating- point load multipl e and s t ore m ult iple.
Ve ctor Flo ating- poi nt Pr ogr ammi ng 6-2 6 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B Usage The FLDM instru ction lo ads sev eral consec uti ve floa ting-poi nt regis ters from memory . The FSTM instr uction s av es t he contents of se ver a l cons ecuti ve flo ating-p oint regis ters to memo ry .
V ecto r Fl oa tin g-poi nt Pro gra mmi ng ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 6-2 7 6.7.9 FM A C, FNMA C, FM S C , and FNM SC Flo ating-p oint mul tiply-a ccumula t e , neg ate-mult iply-a c cumu late, multiply- s ub tract and negate -multiply -subtract .
Ve ctor Flo ating- poi nt Pr ogr ammi ng 6-2 8 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B FNMSCSLE s6, s0, s26.
V ecto r Fl oa tin g-poi nt Pro gra mmi ng ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 6-2 9 6.7.10 FMDRR and FMRRD T rans fer conte nts be tween two ARM re giste rs and a doubl e-pr ecisio n floatin g-point reg ister .
Ve ctor Flo ating- poi nt Pr ogr ammi ng 6-3 0 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 6.7.11 FMDHR, FMDLR, FM RDH, and FMRDL T rans fer conte nts bet ween an ARM regis ter an d a hal f of a double -preci sion float ing-poin t regist er .
V ecto r Fl oa tin g-poi nt Pro gra mmi ng ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 6-3 1 6.7.12 FMRS and FMSR T rans fer conte nts be tween a singl e-prec isio n fl oatin g-point regi ster a nd an ARM reg ister .
Ve ctor Flo ating- poi nt Pr ogr ammi ng 6-3 2 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 6.7.13 FMRRS and FMSRR T rans fer conte nts betw een two sin gle-pre cision floa ting-point re giste rs and two ARM registers.
V ecto r Fl oa tin g-poi nt Pro gra mmi ng ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 6-3 3 6.7.14 FMRX , FMXR , and FMST A T T rans fer conte nts be tween an ARM regi ster and a VFP system re gister .
Ve ctor Flo ating- poi nt Pr ogr ammi ng 6-3 4 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 6.7.15 FMUL and FNMUL Floa ting-po int mult iply and neg ate-mul tiply . FMUL and FNMUL can be scala r , ve ctor , or mi xe d (s ee V ector and scal ar oper ations on pa g e 6- 7) .
V ecto r Fl oa tin g-poi nt Pro gra mmi ng ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 6-3 5 6.7.16 FSI T O and FUIT O Con ve rt s igned inte ge r to f loatin g-point a n d uns igned inte ge r to fl oating-poi nt.
Ve ctor Flo ating- poi nt Pr ogr ammi ng 6-3 6 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 6.7.17 FSQRT Floati ng-point squa re root instr uc t ion. This i nstructi on c an be sca lar , v ect or , or mix e d (see V ector and scal ar oper ations on p a ge 6- 7).
V ecto r Fl oa tin g-poi nt Pro gra mmi ng ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 6-3 7 6.7.18 FTOSI and FT O UI Con ve rt flo ating-point to signed i nteger a n d floa ting-point to unsi gned inte g er .
Ve ctor Flo ating- poi nt Pr ogr ammi ng 6-3 8 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 6 .8 VFP ps eudo- inst ructio n There i s one VFP pseu do-ins truction.
V ecto r Fl oa tin g-poi nt Pro gra mmi ng ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 6-3 9 Examples FLDD d1,=3.
Ve ctor Flo ating- poi nt Pr ogr ammi ng 6-4 0 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 6 .9 VFP dir ectives and vector notation This sectio n applies only to armasm . The inl ine as semble rs in th e C and C++ compil ers do not accep t the se direct iv es or vect or notati on.
V ecto r Fl oa tin g-poi nt Pro gra mmi ng ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 6-4 1 6.9.1 VFP ASSERT SCALAR The VFPASSERT SCALAR dir ecti ve infor m s the ass embler that foll owin g VFP inst ruction s are in sc alar mo de.
Ve ctor Flo ating- poi nt Pr ogr ammi ng 6-4 2 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 6.9.2 VFP ASSERT V ECTO R The VFPASSERT VECTOR dir ecti ve i nfor ms the a ssem bler t hat f ollo wing VFP ins tr uction s are in v ector mode .
V ecto r Fl oa tin g-poi nt Pro gra mmi ng ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 6-4 3 Example FMRX r10,FPSCR BIC r10,r10,#0x00370000 ORR r10,r10,#0x000.
Ve ctor Flo ating- poi nt Pr ogr ammi ng 6-4 4 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B.
ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 7-1 Chapter 7 Direct ives Refe rence Thi s ch apt er de scri bes th e dir ect ives tha t are p rov ided by the AR M ass emb l er, armasm .
Directives Refe rence 7-2 C op yri ght © 2 000, 20 01 A RM Lim it ed. A ll rig hts r es erv ed. AR M D UI 0068 B 7.1 Alphab etical list o f directives T able 7-1 Loca t ion of descr ipti ons of direc.
Dire ct iv es Ref er enc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 7-3 7 .2 Symbol definit ion dir ectives This sect ion des cribes the f ollo wing direc ti ves : • GBLA, GBLL, and GBLS on page 7-4 Declar e a global ari thmetic , lo gical , or string v a ri able.
Directives Refe rence 7-4 C op yri ght © 2 000, 20 01 A RM Lim it ed. A ll rig hts r es erv ed. AR M D UI 0068 B 7.2.1 GB LA, G BLL, and G BLS The GBLA dire cti ve de clar es a gl obal ari thmetic v a ri able, and in itial izes its v alue to 0 .
Dire ct iv es Ref er enc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 7-5 Examples Exam ple 7-1 decl ar es a v a ria ble objec tsize , sets the val ue of objectsize to 0xFF , an d the n us es it la ter in a SP AC E d ir ec tive.
Directives Refe rence 7-6 C op yri ght © 2 000, 20 01 A RM Lim it ed. A ll rig hts r es erv ed. AR M D UI 0068 B 7. 2.2 LCL A, LC L L, an d LCLS The LCLA dire ct iv e decl ares a loca l ar ith meti c var iab le, and init ializ es its v alue to 0.
Dire ct iv es Ref er enc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 7-7 7. 2.3 SET A, SET L, a nd SETS The SETA dire cti ve s ets th e va lue of a lo cal or glo bal a rit hmet ic va ria ble. The SETL dire cti v e set s the v alue of a l oca l or glo bal lo gica l vari able.
Directives Refe rence 7-8 C op yri ght © 2 000, 20 01 A RM Lim it ed. A ll rig hts r es erv ed. AR M D UI 0068 B 7.2.4 RLIST The RLIST (regis ter li st) direct iv e gi ves a name to a set of genera l-purpose regi sters. Syn tax name RLIST { list-of-registers } where: name is the name to be giv en to the set of reg isters .
Dire ct iv es Ref er enc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 7-9 7.2.5 CN The CN direct iv e def ines a name for a coproc essor regis ter . Syn tax name CN expr where: name is t he name to be defi ne d for the coproc essor re gister .
Directives Refe rence 7-1 0 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 7.2.6 CP The CP directi ve def i nes a nam e for a specifi e d coproc e ssor . The coprocessor num ber must be wit hin the ran ge 0 to 15.
Dire ct iv es Ref er enc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 7-1 1 7.2.7 DN and SN The DN direct iv e def ines a na me for a specif ied doub le-precis ion VFP regi s ter . The names d0-d15 a n d D0-D 15 are prede fine d.
Directives Refe rence 7-1 2 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 7.2.8 FN The FN direct iv e def ines a name for a specif ied FP A float ing-point regis ter . The names f0-f 7 and F 0-F7 are predef ined.
Dire ct iv es Ref er enc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 7-1 3 7 .3 Data de finition direc tives This sect ion des cribes the f ollo wing direc ti ves : • LTO R G o n page 7-14 Set a n orig in for a li teral pool.
Directives Refe rence 7-1 4 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 7.3.1 L T ORG The LTORG d irect iv e in struc ts the asse mble r t o as semb le t he cu rren t li teral pool imm edi atel y .
Dire ct iv es Ref er enc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 7-1 5 7.3.2 MAP The MAP di re ctive se ts th e o rig in o f a st ora ge ma p to a spec ifie d a dd re ss. T he stor age-m ap location count er , {VAR} , is set to the sam e address.
Directives Refe rence 7-1 6 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 7.3.3 FIELD The FIELD dir ectiv e des cribes spa c e wit hin a s torage map that has been d efin ed us ing the MAP di rec tive. # is a syno nym for FIELD .
Dire ct iv es Ref er enc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 7-1 7 7.3.4 SP ACE The SPACE direct iv e reserv es a zeroed bloc k of memo r y .
Directives Refe rence 7-1 8 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 7.3.5 DCB The DCB dire c t iv e al loca tes one or more byt e s o f memory , and defi nes th e ini tial runtime conte nts of the me mory .
Dire ct iv es Ref er enc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 7-1 9 7.3.6 DCD and DCDU The DCD direc ti ve a lloc ates on e o r more wo rds of memo ry , al igned o n 4- byte boundari es, and def ines the init ial runt ime con tents of the memor y .
Directives Refe rence 7-2 0 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 7.3.7 DCDO The DCDO di rec tive all oc at e s on e or m or e wo rd s of me mo r y , .
Dire ct iv es Ref er enc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 7-2 1 7.3.8 DCFD an d DCFDU The DCFD direct iv e allo cates memory for word -aligne d double-p recisio n floa tin g-point numbe rs, an d defin e s t he init ial runtime conten ts o f the memory .
Directives Refe rence 7-2 2 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 7.3.9 DCF S and DCF SU The DCFS direct iv e allo cates memory for word -a l igned singl e-prec ision fl oating -point numbe rs, and def ines t he in itial runti me cont ents of the memory .
Dire ct iv es Ref er enc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 7-2 3 7.3.10 DCI In A RM cod e, the DCI dire c t iv e a lloca tes one o r more w ords of m emory , ali gned on 4-byt e boundaries, and defi nes th e initi al runtime c ontents of the memory .
Directives Refe rence 7-2 4 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 7.3.11 DCQ and DCQU The DCQ direct iv e allo cates one o r more 8-by te block s of m emory , align e d on 4-b yte boundar ie s, and def ines the ini tial run time conte nts of the memory .
Dire ct iv es Ref er enc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 7-2 5 7.3.12 DCW an d DCWU The DCW direct iv e allo cates one or more half words of m e mory , a l igned on 2-b yte boundar ies, and def ines the ini tial runtime cont ents of th e m emo ry .
Directives Refe rence 7-2 6 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 7. 4 Asse m b ly co ntro l di rectives This se ction descri bes the f ollo wing di recti ves : • MA CR O and MEND on page 7-27 • MEXI T on page 7-29 • IF , ELSE , and ENDIF on page 7-30 • WHILE a nd WEND on pa ge 7-32 .
Dire ct iv es Ref er enc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 7-2 7 7.4.2 M A CRO an d M END The MACRO direct iv e mark s the start o f the def initi on of a macro. Macro expa nsion te rmi nat es a t the MEND dir ect i ve.
Directives Refe rence 7-2 8 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B Use | as the arg ument to use the de fault v alue of a parameter .
Dire ct iv es Ref er enc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 7-2 9 Using a m acro to produce assemb ly-tim e di agn ostics : MACRO ; M acro definiti.
Directives Refe rence 7-3 0 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 7. 4.4 IF , EL SE, a nd E NDIF The IF dire c t iv e introd uces a c ondition t hat is use d to de cid e whether to a ssemble a seq uence of inst ructio ns and/o r di recti ves.
Dire ct iv es Ref er enc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 7-3 1 Examples Exa mple 7- 3 asse mbles the fi rs t set o f inst ructio ns if NEWVERSION is def ined, or the alt ern ative s et ot her wis e.
Directives Refe rence 7-3 2 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 7.4.5 WHILE and W END The WHILE direct iv e sta rts a seque nce of instr uc t ions or dir ecti ve s that are to be as sem ble d rep eat ed ly .
Dire ct iv es Ref er enc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 7-3 3 7. 5 F rame descr iption dir ectives This sect ion des cribes the f ollo wing dir.
Directives Refe rence 7-3 4 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 7.5.1 FRAME ADDRESS The FRAME ADDRESS dire cti ve describes h ow t o calc ulate t he canoni cal frame a ddress for follo wing inst ruction s .
Dire ct iv es Ref er enc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 7-3 5 7.5.2 FRA ME POP Use th e FRAME POP dire cti v e to in form t he as se mbler whe n the c al lee r elo ads re gis ter s. Y ou can only use it withi n functio ns with FUNCTION and ENDFUNC or PROC an d ENDP direc ti ves.
Directives Refe rence 7-3 6 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 7.5 .3 F R AME PU SH Use the FRAME PUSH d irectiv e t o i nform the a ssemble r when the callee sa ves registers, nor mally at func tion ent ry .
Dire ct iv es Ref er enc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 7-3 7 Example p PROC ; Canonical frame address is sp + 0 EXPORT p STMFD sp!,{r4-r6,lr} .
Directives Refe rence 7-3 8 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 7.5.5 FR AME RESTORE Use the FRAME RESTORE dire cti ve to inf orm th e ass embl er th at t he con te nts of sp eci fie d regi sters ha ve been r e stor e d to the val ues they ha d on ent ry t o the fu nction.
Dire ct iv es Ref er enc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 7-3 9 7.5.6 FRA ME SA VE The FRAME SAVE dir ectiv e describ es the lo catio n of sav ed regi ster cont ents relat ive t o th e canon ical fra me addre ss .
Directives Refe rence 7-4 0 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 7.5 .7 FR A ME ST A T E REM EMB ER The FRAME STATE REMEMBER dir ec tive saves the c urre n t inf or mat ion on h o w to ca lcu la te the ca nonica l frame ad dress and loc a t ions of sa ve d regi s ter v a lu es.
Dire ct iv es Ref er enc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 7-4 1 7. 5.8 FRAME S T A TE REST ORE The FRAME STATE RESTORE dire c t iv e re stores informat ion a bout ho w to cal culate the canon ical frame address and loc ation s of sav e d regi ster v alues.
Directives Refe rence 7-4 2 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 7.5.9 FUNCTION or PR OC The FUNCTION direct iv e marks the start of an A TPCS- conforming fun c ti on. PROC is a synon ym for FUNCTION .
Dire ct iv es Ref er enc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 7-4 3 7.5.10 ENDFUNC o r ENDP The ENDFUNC direct iv e mark s the end of an A T PCS-c onforming functi on (see FUNCT ION or PR OC on page 7-42) .
Directives Refe rence 7-4 4 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 7.6 R ep or t ing di re ct iv es This se ction descri bes the f ollo wing di recti ves : • ASSERT gener ates an erro r mess age if an asserti on is false duri ng assembl y .
Dire ct iv es Ref er enc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 7-4 5 7.6.2 INFO The INFO direct iv e suppo rts diagnosti c genera tion on ei ther pass of the asse mbly . ! is ve ry sim ilar to INFO , but ha s le s s deta il ed r ep or tin g.
Directives Refe rence 7-4 6 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 7.6.3 OPT The OPT dire cti v e set s l isting options f rom withi n the sourc e code. Syn tax OPT n where: n is the OPT direc ti ve se tting.
Dire ct iv es Ref er enc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 7-4 7 By defa ult the -list opt ion prod uces a norma l li stin g that inc ludes v aria ble decl arati ons, m acro expa nsions, cal l-condi tioned direc ti ves, a nd MEND di rec ti ves .
Directives Refe rence 7-4 8 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 7.6.4 TT L and S UBT The TTL dire cti ve in s e rts a ti tle at t he sta rt of each pa ge of a li stin g fi le. Th e title is printe d on e ach pa ge until a ne w TTL dir ect ive is iss ue d.
Dire ct iv es Ref er enc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 7-4 9 7. 7 Mi scellaneo u s directi ves This sect ion des cribes the f ollo wing direc .
Directives Refe rence 7-5 0 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 7.7.1 ALIGN The ALIGN dire c t iv e al igns the c urrent locatio n to a specif ied bounda ry b y paddi ng with zer oes.
Dire ct iv es Ref er enc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 7-5 1 Examples AREA cacheable, CODE, ALIGN=3 rout1 ; code ; aligned on 8-byte boundary .
Directives Refe rence 7-5 2 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 7.7.2 AREA The AREA dir ective ins tru cts th e as sem ble r to as se mbl e a new co de or data sect i on. Secti ons a re i nde p endent , na med, in divis ible chunks of c ode or da ta that are mani pulated b y the li nk er .
Dire ct iv es Ref er enc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 7-5 3 Ide ntica l E LF secti ons with th e same nam e are o verl aid i n t he same sectio n o f me mory by the li nker . I f an y are d if fer ent, the linke r ge nera te s a wa rning and does no t ove rlay the secti ons.
Directives Refe rence 7-5 4 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 7.7.3 C ODE16 an d CODE 32 The CODE16 dire cti ve instruc ts t he asse mbler t o inte rpret subsequent ins tructions as 16- bit Thumb ins truc tions .
Dire ct iv es Ref er enc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 7-5 5 7.7.4 END The END direct iv e in forms the assembl e r that it has rea ched the end of a sourc e file . Syn tax END Usage Eve ry assembl y lan guage source file must e nd w i th END on a line b y i tse lf.
Directives Refe rence 7-5 6 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 7.7.5 ENTR Y The ENTRY d ire ct iv e de clare s a n ent ry p oint t o a progr am. Syn tax ENTRY Usage Y ou must spe cify a t least on e ENTRY point for a program.
Dire ct iv es Ref er enc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 7-5 7 7.7.6 EQU The EQU d ire cti ve g iv es a s y mbo lic na m e to a n umeri c cons t ant, a regi s t er -r elati ve v alu e or a program-re lati ve v alue.
Directives Refe rence 7-5 8 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 7.7.7 E XPO RT or GLOBAL The EXPORT dir ecti ve declar es a symbol t hat can be use d by the link er to resol ve symbol referenc e s in sepa rate objec t and library f iles.
Dire ct iv es Ref er enc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 7-5 9 7.7.8 EXPORT AS The EXPORTAS dire c t iv e a llo ws you t o export a symbol to t he objec t f ile, c orrespondi ng t o a d iffe rent s y mbol in the s ource f ile .
Directives Refe rence 7-6 0 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 7. 7.9 EXT ERN The EXTERN direct iv e pro vides the a ss embler with a name that is not def ined in the current assembly .
Dire ct iv es Ref er enc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 7-6 1 7.7.10 GET or INCL UDE The GET direct iv e includes a f ile within th e f ile bei ng assemble d. The i nclude d f ile is as sem ble d at t he loca t ion o f t he GET dir ect i ve.
Directives Refe rence 7-6 2 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 7.7.11 GLOBAL See EXPORT or GL OB A L on pa ge 7-58. 7.7.12 IMPORT The IMPORT direct iv e pro vides the a ss embler with a name that is not def ined in the current assembly .
Dire ct iv es Ref er enc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 7-6 3 7.7.13 INCBI N The INCBI N direct iv e inc l ud es a f ile wit hin the f ile b eing a ssembl ed. T he f ile is i ncluded as it i s, wit hout be ing a ssemble d.
Directives Refe rence 7-6 4 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 7.7.15 KEEP The KEEP dir ecti v e ins truc ts th e assemb ler to re tain l ocal sym bol s in th e sym bol tab le in th e objec t fi le.
Dire ct iv es Ref er enc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 7-6 5 7.7.16 NOFP The NOFP direc ti ve dis allo ws floati ng-point instruc tions in an a ss embly l anguag e sou rce fi le .
Directives Refe rence 7-6 6 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 7.7.18 REQUI RE8 and PRESERVE 8 The REQUIRE8 di re ctive sp ec ifie s t hat t he c ur ren t file req uir e s 8- byt e alig n me nt of th e stac k.
Dire ct iv es Ref er enc e ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. 7-6 7 7.7.19 RN The RN direct iv e def ines a re gister name for a spe cif ied reg ister . Syn tax name RN expr where: name is the name to be ass ign ed to the r egis ter .
Directives Refe rence 7-6 8 C opyri gh t © 200 0, 2001 AR M L imit ed . A ll right s re s erved . ARM DU I 00 68 B 7.7.20 R OUT The ROUT direct iv e marks the bounda ries of the scope of loc al labels (s ee Local la bels on page 3-16 ). Syn tax { name } ROUT where: name is the na me to be assi gned to t he sco pe.
ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. Glossa ry-1 Glos sar y ADS See ARM Dev eloper Suite. ANSI Ameri c a n Na tiona l S tan dards Ins titu te. An org a ni zati on that spec if ies stand ards for , among ot her thin gs, computer software.
Glos sary Glossary-2 C op yri ght © 2 00 0, 20 01 ARM Lim it ed. All rig hts re serv ed . ARM D UI 0068 B A T PCS ARM and T humb Pro c edure Call St a nd ard de f ines ho w regi sters a nd the stack wi ll be use d for subr outine c alls. AXD See ARM eXtended Deb ugger .
Glossa ry ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. Glossa ry-3 Int errupt A chang e in the normal proc essing sequence of an app lica tion ca used by , for e xamp le, an ext erna l sign al. Int erwork i ng Produ c i ng an applic a t ion t ha t uses bo th ARM a nd Thumb c ode.
Glos sary Glossary-4 C op yri ght © 2 00 0, 20 01 ARM Lim it ed. All rig hts re serv ed . ARM D UI 0068 B Scope T he ac cessibi lity of a functio n or v aria ble at a part icula r p oint i n the a pplica tion c od e. Symbols which ha ve glo bal scope ar e always a ccessibl e.
ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. Inde x-1 Inde x The i tems in thi s inde x are list e d in a lphabetic a l o rder , with symbols and numeric s appea ring at th e end. The r eferences gi ven are to page numb ers.
In dex In dex-2 Cop yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. AR M D UI 0068 B nu meric ex press ions 3-20 num er ic li te rals 3 -21 nu meric va riables 3-13 oper ator prece den.
In de x ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. Inde x-3 GBLA 3-6, 3 -13, 7-4, 7-4 6 GBLL 3-6, 3-13, 7-4, 7-46 GBLS 3-6, 3-13, 7 -4, 7-46 GET 3-5, 7-61 GL.
In dex In dex-4 Cop yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. AR M D UI 0068 B LDM in struc t i on 2 -39, 2- 54, 3- 3, 7-8 Thum b 2- 46 LDR pseud o-instr ucti on 2-25, 2-27, 2- 3.
In de x ARM DU I 00 68 B C op yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. Inde x-5 S tatus fl ags 2-20 S TM instru ction 2-39, 2-54 , 3-3, 7-8 Thum b 2- 46 :ST R: o pe rato r 3 -26.
In dex In dex-6 Cop yri ght © 2 000, 20 01 ARM Lim it ed. A ll rig hts res erv ed. AR M D UI 0068 B.
デバイスARM VERSION 1.2の購入後に（又は購入する前であっても）重要なポイントは、説明書をよく読むことです。その単純な理由はいくつかあります：
ARM VERSION 1.2をまだ購入していないなら、この製品の基本情報を理解する良い機会です。まずは上にある説明書の最初のページをご覧ください。そこにはARM VERSION 1.2の技術情報の概要が記載されているはずです。デバイスがあなたのニーズを満たすかどうかは、ここで確認しましょう。ARM VERSION 1.2の取扱説明書の次のページをよく読むことにより、製品の全機能やその取り扱いに関する情報を知ることができます。ARM VERSION 1.2で得られた情報は、きっとあなたの購入の決断を手助けしてくれることでしょう。
ARM VERSION 1.2を既にお持ちだが、まだ読んでいない場合は、上記の理由によりそれを行うべきです。そうすることにより機能を適切に使用しているか、又はARM VERSION 1.2の不適切な取り扱いによりその寿命を短くする危険を犯していないかどうかを知ることができます。
ですが、ユーザガイドが果たす重要な役割の一つは、ARM VERSION 1.2に関する問題の解決を支援することです。そこにはほとんどの場合、トラブルシューティング、すなわちARM VERSION 1.2デバイスで最もよく起こりうる故障・不良とそれらの対処法についてのアドバイスを見つけることができるはずです。たとえ問題を解決できなかった場合でも、説明書にはカスタマー・サービスセンター又は最寄りのサービスセンターへの問い合わせ先等、次の対処法についての指示があるはずです。
