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© Copyright 1985, 1997 National Instruments Corporation. All Rights Reserved. GPIB-1014 User Manual March 1997 Edition Part Number 320030-01.
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Limited Warranty The GPIB-1014 is warranted against defects in materials and workmanship for a period of two years from the date of shipment, as evidenced by receipts or other documentation. National Instruments will, at its option, repair or replace equipment that proves to be defective during the warranty period.
Warning Regarding Medical and Clinical Use of National Instruments Products National Instruments products are not designed with components and testing intended to ensure a level of reliability suitable for use in treatment and diagnosis of humans.
FCC/DOC Radio Frequency Interference Compliance This equipment generates and uses radio frequency energy and, if not installed and used in strict accordance with the instructions in this manual, may cause interference to radio and television reception.
© National Instruments Corporation vii GPIB-1014 User Manual Contents About This Manual ............................................................................................................ xiii Organization of This Manual ....................
Contents GPIB-1014 User Manual viii © National Instruments Corporation Register Description .......................................................................................... 4-2 Register Description Format ...................................
Contents © National Instruments Corporation ix GPIB-1014 User Manual Going from Standby to Active Controller ......................................................... 5-4 Going from Active to Idle Controller ..........................................
Contents GPIB-1014 User Manual x © National Instruments Corporation 68450 DMAC ................................................................................................................ 6-14 DMAC Channel Operation ..............................
Contents © National Instruments Corporation xi GPIB-1014 User Manual Data Lines .......................................................................................................... E-2 Handshake Lines ...........................................
Contents GPIB-1014 User Manual xii © National Instruments Corporation Figure 6-3. Array Format for Linked Chaining Modes ...................................................... 6-21 Figure E-1. The GPIB Connector and Signal Assignments ...............
© National Instruments Corporation xiii GPIB-1014 User Manual About This Manual The GPIB-1014 User Manual describes the mechanical and electrical aspects of the GPIB-1014, the data transfer features, and contains information concerning its operation and programming.
About This Manual GPIB-1014 User Manual xiv © National Instruments Corporation • Appendix F, Mnemonics Key , contains a mnemonics key that defines the mnemonics (abbreviations) used throughout this.
About This Manual © National Instruments Corporation xv GPIB-1014 User Manual • Motorola Semiconductor Technical Data MC68450 Advance Information Direct Memory Access Controller (DMAC) • Hitachi .
© National Instruments Corporation 1-1 GPIB-1014 User Manual Chapter 1 Introduction This chapter describes the GPIB-1014, lists the contents and oiptional equipment for your GPIB-1014 kit, and explains how to unpack the GPIB-1014 kit. The GPIB-1014 is a high-performance IEEE 488 interface for the VMEbus.
Introduction Chapter 1 GPIB-1014 User Manual 1-2 © National Instruments Corporation Figure 1-1 shows the GPIB-1014 interface board. Figure 1-1. GPIB-1014 Interface Board Art not available in PDF version of document.
Chapter 1 Introduction © National Instruments Corporation 1-3 GPIB-1014 User Manual The GPIB-1014 interface kit includes hardware and programming examples to implement the GPIB functions. Optional cables are supplied for interconnection with other devices on the GPIB.
Introduction Chapter 1 GPIB-1014 User Manual 1-4 © National Instruments Corporation Unpacking Follow these steps when unpacking your GPIB-1014. 1. Verify that the pieces contained in the package you received match the kit parts list given earlier in this chapter.
© National Instruments Corporation 2-1 GPIB-1014 User Manual Chapter 2 General Description This chapter contains the electrical specifications for the GPIB-1014, the data transfer features, and describes the characteristics of key interface board components.
General Description Chapter 2 GPIB-1014 User Manual 2-2 © National Instruments Corporation Table 2-1. GPIB-1014 Signals (continued) Driver Device Receiver Device Bus Signals Part Number Part Number B.
Chapter 2 General Description © National Instruments Corporation 2-3 GPIB-1014 User Manual to generate its board select signal. It then decodes the lowest eight lines, A8 through A1, to address the f.
General Description Chapter 2 GPIB-1014 User Manual 2-4 © National Instruments Corporation Table 2-3. 68450 Internal DMA Registers Ad dress (Base + Hex Offset) Mode Register Channel Size 0A R/W Memor.
Chapter 2 General Description © National Instruments Corporation 2-5 GPIB-1014 User Manual Table 2-3. 68450 Internal DMA Registers (continued) Address (Base + Hex Offset) Mode Register Channel Size 8.
General Description Chapter 2 GPIB-1014 User Manual 2-6 © National Instruments Corporation Memory addresses generated by the GPIB-1014 are 24 bits wide and the VMEbus Address Modifier Lines (AM5 through AM0) are fully programmable using function code registers located in the 68450 and three hardware jumpers (W3, W4, and W5).
Chapter 2 General Description © National Instruments Corporation 2-7 GPIB-1014 User Manual Data Transfer Bus (DTB) Requester The GPIB-1014 arbitrates for the DTB before each DMA transfer. The board is designed for you to select, through software, one of four VMEbus request lines (BR0* through BR3*) using two bits in Configuration Register 1.
General Description Chapter 2 GPIB-1014 User Manual 2-8 © National Instruments Corporation • GPIB Listener response time (DAV* low to NDAC* high) • GPIB Talker response time (NRFD* high to DAV* l.
Chapter 2 General Description © National Instruments Corporation 2-9 GPIB-1014 User Manual 3 Lines Digital Voltmeter Able to Talk and Listen Device C Printer Able to Listen Device B Device A VMEbus C.
General Description Chapter 2 GPIB-1014 User Manual 2-10 © National Instruments Corporation Computer Center Up to 300 Meters (RS-422) R&D Lab Microprocessor W ork Station Production & T estin.
Chapter 2 General Description © National Instruments Corporation 2-11 GPIB-1014 User Manual Figure 2-3 is a block diagram of the GPIB-1014. GPIB µ PD7210 TLC 68450 DMAC Data T ransfer Bus Priority I.
General Description Chapter 2 GPIB-1014 User Manual 2-12 © National Instruments Corporation The interface consists of these major components, which are discussed in greater detail in Chapter 6.
Chapter 2 General Description © National Instruments Corporation 2-13 GPIB-1014 User Manual Table 2-5 lists the capabilities of the GPIB-1014 in terms of the IEEE 488 standard codes.
General Description Chapter 2 GPIB-1014 User Manual 2-14 © National Instruments Corporation Table 2-5. GPIB-1014 IEEE 488 Interface Capabilities (continued) Capability Code Description DC1 Complete D.
Chapter 2 General Description © National Instruments Corporation 2-15 GPIB-1014 User Manual • Receive control • Pass control • Conduct a Parallel Poll • Take control synchronously or asynchronously Table 2-6 contains the GPIB-1014 IEEE 1014 compliance levels.
© National Instruments Corporation 3- 1 GPIB-1014 User Manual Chapter 3 Configuration and Installation This chapter describes the steps needed to configure and install the GPIB-1014 hardware.
Configuration and Installation Chapter 3 GPIB-1014 User Manual 3- 2 © National Instruments Corporation Figure 3-1 shows the locations of the GPIB-1014 configuration jumpers and switches. Figure 3-1. Parts Locator Diagram Art not available in PDF version of document.
Chapter 3 Configuration and Installation © National Instruments Corporation 3- 3 GPIB-1014 User Manual Access Mode The GPIB-1014 can be configured to respond to Supervisor (privileged) or User (non-privileged) access. Hardware jumper W2 is used to select the access mode that is automatically in effect upon a power-up or a system reset.
Configuration and Installation Chapter 3 GPIB-1014 User Manual 3- 4 © National Instruments Corporation Set Base Address Using Jumper Block W1 Move the jumper to the side labeled 1 to select a logical one for the corresponding address bit, or to the side labeled 0 to select a logical zero.
Chapter 3 Configuration and Installation © National Instruments Corporation 3- 5 GPIB-1014 User Manual DMA Address Modifier Code Output During a DMA cycle, the GPIB-1014 sends out a 6-bit Address Modifier (AM) code to the VMEbus lines AM5 through AM0.
Configuration and Installation Chapter 3 GPIB-1014 User Manual 3- 6 © National Instruments Corporation Table 3-1. Programming Values for Default Settings of W3, W4, and W5 FCR Bits AM Codes M2 throug.
Chapter 3 Configuration and Installation © National Instruments Corporation 3- 7 GPIB-1014 User Manual For example, to produce an AM code of 17 hex (a binary value of 010111), complete the following steps: 1. Set jumper W3 to 0. 2. Set jumper W4 to 0.
Configuration and Installation Chapter 3 GPIB-1014 User Manual 3- 8 © National Instruments Corporation Table 3-3. GPIB-1014 Pin Assignment on VMEbus Connector P1 Pin No.
Chapter 3 Configuration and Installation © National Instruments Corporation 3- 9 GPIB-1014 User Manual Table 3-4. GPIB-1014 Pin Assignment on VMEbus Connector P2 Signal Signal Signal Signal Pin No.
Configuration and Installation Chapter 3 GPIB-1014 User Manual 3- 10 © National Instruments Corporation Cabling Two options are available for GPIB I/O from the GPIB-1014: • A Front Panel Plug-In Connector • A VMEbus P2 Connector The Model GPIB-1014-1 interface board has a standard 24-pin IEEE 488 connector on the front panel of the board.
© National Instruments Corporation 4-1 GPIB-1014 User Manual Chapter 4 Register Bit Descriptions This chapter contains a description of the register map, a list of interface registers, and a description of the DMA registers. Register Map The register map for the GPIB-1014 is shown in Table 4-1.
Register Bit Descriptions Chapter 4 GPIB-1014 User Manual 4-2 © National Instruments Corporation Table 4-1. GPIB-1014 Register Map (continued) Register Name Address (Hex) Type Size DMA Register Group.
Chapter 4 Register Bit Descriptions © National Instruments Corporation 4-3 GPIB-1014 User Manual Register Description Format The remainder of this chapter discusses each of the GPIB-1014 registers in the order shown in Table 4-1. Each register group is introduced, followed by a detailed bit description of each register.
Register Bit Descriptions Chapter 4 GPIB-1014 User Manual 4-4 © National Instruments Corporation Interface Registers Twenty-one GPIB Interface registers, eight of which are readable and 13 of which are writable, are located within the NEC µ PD7210 Talker/Listener/Controller (TLC) integrated circuit.
Chapter 4 Register Bit Descriptions © National Instruments Corporation 4-5 GPIB-1014 User Manual DIR CDOR (Contents of Read Register) (Contents of Write Register) Legend Bit 7 Bit 6 Bit 5 Bit 4 Bit 3.
Register Bit Descriptions Chapter 4 GPIB-1014 User Manual 4-6 © National Instruments Corporation Control Code Command Code When CNT2-CNT0 is: ICR is loaded with: PPR is loaded with: AUXRA is loaded w.
Chapter 4 Register Bit Descriptions © National Instruments Corporation 4-7 GPIB-1014 User Manual Data In Register (DIR) VMEbus Address: Base Address + 111 (hex) Attributes: Read Only, Internal to TLC.
Register Bit Descriptions Chapter 4 GPIB-1014 User Manual 4-8 © National Instruments Corporation Command/Data Out Register (CDOR) VMEbus Address: Base Address + 111 (hex) Attributes: Write Only, Inte.
Chapter 4 Register Bit Descriptions © National Instruments Corporation 4-9 GPIB-1014 User Manual Interrupt Status Register 1 (ISR1) VMEbus Address: Base Address + 113 (hex) Attributes: Read Only, Int.
Register Bit Descriptions Chapter 4 GPIB-1014 User Manual 4-10 © National Instruments Corporation Bit Mnemonic Description undefined: GPIB command not automatically recognized and executed by TLC ACD.
Chapter 4 Register Bit Descriptions © National Instruments Corporation 4-11 GPIB-1014 User Manual Bit Mnemonic Description SCG: GPIB Secondary Command Group ACDS: GPIB Accept Data State pon: Power On.
Register Bit Descriptions Chapter 4 GPIB-1014 User Manual 4-12 © National Instruments Corporation Bit Mnemonic Description EOS: GPIB END Of String message REOS: Reception of GPIB EOS allowed, AUXRA[2.
Chapter 4 Register Bit Descriptions © National Instruments Corporation 4-13 GPIB-1014 User Manual Bit Mnemonic Description write CDOR: Bit is set immediately after writing to the Command/Data Out Reg.
Register Bit Descriptions Chapter 4 GPIB-1014 User Manual 4-14 © National Instruments Corporation Bit Mnemonic Description Notes LACS: GPIB Listener Active State ACDS: GPIB Accept Data State continuo.
Register Bit Descriptions Chapter 4 GPIB-1014 User Manual 4-14 © National Instruments Corporation Interrupt Status Register 2 (ISR2) VMEbus Address: Base Address + 115 (hex) Attributes: Read Only, In.
Bit Mnemonic Description ERR IE: Enable Interrupt on Error Bit END RX: End Received Bit END IE: Enable Interrupt on End Received Bit DEC: Device Clear Bit DEC IE: Enable Interrupt on Device Clear Bit .
Register Bit Descriptions Chapter 4 GPIB-1014 User Manual 4-16 © National Instruments Corporation Bit Mnemonic Description 5r LOK Lockout Bit LOK is used, along with the REM bit, to indicate the status of the TLC GPIB Remote/Local (RL) function.
Bit Mnemonic Description 2r LOKC Lockout Change Bit 2w LOKC IE Lockout Change Interrupt Enable Bit LOKC is set by: any change in LOK LOKC is cleared by: pon + (read ISR2) Notes LOK: ISR2[5]r pon: Power On Reset read ISR2: Bit is cleared immediately after it is read LOKC is set when there is a change in the LOK bit, ISR2[5]r, (REMS +RELS).
Register Bit Descriptions Chapter 4 GPIB-1014 User Manual 4-18 © National Instruments Corporation Bit Mnemonic Description Notes TA: Talker Active bit, ADSR[1]r LA: Listener Active bit, ADSR[2]r CIC:.
Serial Poll Status Register (SPSR) VMEbus Address: Base Address + 117 (hex) Attributes: Read Only, Internal to TLC Serial Poll Mode Register (SPMR) VMEbus Address: Base Address + 117 (hex) Attributes:.
Register Bit Descriptions Chapter 4 GPIB-1014 User Manual 4-20 © National Instruments Corporation Address Status Register (ADSR) VMEbus Address: Base Address + 119 (hex) Attributes: Read Only, Intern.
Bit Mnemonic Description 3r TPAS Talker Primary Addressed State Bit TPAS is used when the TLC is configured for extended GPIB addressing, and, when set, indicates that the TLC has received its primary GPIB talk address.
Register Bit Descriptions Chapter 4 GPIB-1014 User Manual 4-22 © National Instruments Corporation Address Mode Register (ADMR) VMEbus Address: Base Address + 119 (hex) Attributes: Write Only, Interna.
Bit Mnemonic Description 1-0w ADM[1-0] Address Mode Bits 1 through 0 These bits state the addressing mode currently in effect–that is, the manner in which the information in ADR0 and ADR1 is interpreted (see Address Register 0 and Address Register 1 later in this chapter).
Register Bit Descriptions Chapter 4 GPIB-1014 User Manual 4-24 © National Instruments Corporation Bit Mnemonic Description ADM0 and ADM1 must be cleared when either of the two programmable bits ton or lon is set.
Command Pass Through Register (CPTR) VMEbus Address: Base Address + 11B (hex) Attributes: Read Only, Internal to TLC R 7 6 54 32 1 0 CPT7 CPT6 CPT5 CPT4 CPT3 CPT2 CPT1 CPT0 Bit Mnemonic Description 7-.
Register Bit Descriptions Chapter 4 GPIB-1014 User Manual 4-26 © National Instruments Corporation Table 4-3. Multiline GPIB Commands Recognized by the µ PD7210 (continued) Hex Number Message Descrip.
Auxiliary Mode Register (AUXMR) VMEbus Address: Base Address + 11B (hex) Attributes: Write Only, Internal to TLC Permits Access to Hidden Registers W 7 6 54 32 1 0 CNT1 CNT0 CNT2 COM4 COM3 COM2 COM1 COM0 The Auxiliary Mode Register (AUXMR) is used to issue auxiliary commands.
Register Bit Descriptions Chapter 4 GPIB-1014 User Manual 4-28 © National Instruments Corporation Table 4-4. Auxiliary Command Summary Function Code* (COM4-COM0) Hex 4 3 2 1 0 Code** Auxiliary Comman.
Table 4-5 shows the functions that are executed when the AUXMR Control Code (CNT2 through CNT0) is loaded with 000 (binary) and the Command Code (COM4 through COM0) is loaded.
Register Bit Descriptions Chapter 4 GPIB-1014 User Manual 4-30 © National Instruments Corporation Table 4-5. Auxiliary Commands: Detail Description (continued) Command Code (COM4-COM0) 4 3 2 1 0 Description 0 0 0 1 1 Finish Handshake (FH) The Finish Handshake command finishes a GPIB Handshake that was stopped because of a Holdoff on RFD or DAC.
Table 4-5. Auxiliary Commands: Detail Description (continued) Command Code (COM4-COM0) 4 3 2 1 0 Description 0 0 0 0 1 Clear Parallel Poll Flag 0 1 0 0 1 Set Parallel Poll Flag These commands set the Parallel Poll Flag to the value of COM3.
Register Bit Descriptions Chapter 4 GPIB-1014 User Manual 4-32 © National Instruments Corporation Table 4-5. Auxiliary Commands: Detail Description (continued) Command Code (COM4-COM0) 4 3 2 1 0 Desc.
Chapter 4 Register Descriptions © National Instruments Corporation 4-33 GPIB-1014 User Manual Hidden Registers The hidden registers are loaded through the Auxiliary Mode Register (AUXMR). AUXMR[7-5] is loaded with the hidden register number, and AUXMR[4-0] is loaded with the data to be transferred to the hidden register.
Register Descriptions Chapter 4 GPIB-1014 User Manual 4-34 © National Instruments Corporation Internal Counter Register (ICR) VMEbus Address: Base Address + 11B (hex) AUXMR Control Code: 001 (Binary,.
Chapter 4 Register Descriptions © National Instruments Corporation 4-35 GPIB-1014 User Manual Parallel Poll Register (PPR) VMEbus Address: Base Address + 11B (hex) AUXMR Control Code: 011 (Binary, Bi.
Register Descriptions Chapter 4 GPIB-1014 User Manual 4-36 © National Instruments Corporation Bit Mnemonic Description 3w S Status Bit Polarity (Sense) Bit The S bit is used to indicate the polarity (or sense) of the TLC local ist message.
Chapter 4 Register Descriptions © National Instruments Corporation 4-37 GPIB-1014 User Manual Auxiliary Register A (AUXRA) VMEbus Address: Base Address + 11B (hex) AUXMR Control Code: 100 (Binary, Bi.
Register Descriptions Chapter 4 GPIB-1014 User Manual 4-38 © National Instruments Corporation Bit Mnemonic Description 1-0w HLDE Holdoff on End Bit HLDA Holdoff on All Bit HLDE and HLDA together determine the GPIB data receiving mode.
Chapter 4 Register Descriptions © National Instruments Corporation 4-39 GPIB-1014 User Manual Auxiliary Register B (AUXRB) VMEbus Address: Base Address + 11B (hex) AUXMR Control Code: 101 (Binary, Bi.
Register Descriptions Chapter 4 GPIB-1014 User Manual 4-40 © National Instruments Corporation Bit Mnemonic Description 2w TRI Three-State Timing Bit The TRI bit determines the TLC GPIB Source Handshake Timing, T1. TRI can be set to enable high-speed data transfers (T1 ≥ 500 nsec) when tri-state GPIB drivers are used.
Chapter 4 Register Descriptions © National Instruments Corporation 4-41 GPIB-1014 User Manual Auxiliary Register E (AUXRE) VMEbus Address: Base Address + 11B (hex) AUXMR Control Code: 110 (Binary, Bi.
Register Descriptions Chapter 4 GPIB-1014 User Manual 4-42 © National Instruments Corporation Address Register 0 (ADR0) VMEbus Address: Base Address + 11D (hex) Attributes: Read Only, Internal to TLC.
Chapter 4 Register Descriptions © National Instruments Corporation 4-43 GPIB-1014 User Manual Address Register (ADR) VMEbus Address: Base Address + 11D (hex) Attributes: Write Only, Internal to TLC 76543210 ARS DT DL AD5 AD4 AD3 AD2 AD1 W The Address Register (ADR) is used to load the internal registers ADR0 and ADR1.
Register Descriptions Chapter 4 GPIB-1014 User Manual 4-44 © National Instruments Corporation Address Register 1 (ADR1) VMEbus Address: Base Address + 11F (hex) Attributes: Read Only, Internal to TLC.
Chapter 4 Register Descriptions © National Instruments Corporation 4-45 GPIB-1014 User Manual End of String Register (EOSR) VMEbus Address: Base Address + 11F hex Attributes: Write Only, Internal to .
Register Descriptions Chapter 4 GPIB-1014 User Manual 4-46 © National Instruments Corporation DMA Registers The onboard DMA Controller is a 68450 DMAC. This chip is extremely flexible and uses four independent DMA channels. The DMAC can support single address (flyby) transfers or dual address (flowthrough) transfers.
Chapter 4 Register Descriptions © National Instruments Corporation 4-47 GPIB-1014 User Manual Register Offset 00 02 04 06 08 0A 0C 0E 10 12 14 16 18 1A 1C 1E 20 22 24 26 28 2A 2C 2E 30 32 34 36 38 3A.
Register Descriptions Chapter 4 GPIB-1014 User Manual 4-48 © National Instruments Corporation The following paragraphs describe the channel configuration and status registers.
Chapter 4 Register Descriptions © National Instruments Corporation 4-49 GPIB-1014 User Manual Transfer Count Registers The Memory Transfer Counter Register (MTCR) and the Base Transfer Counter Register (BTCR) are 16-bit registers. The MTCR is used to specify how many operands will be transferred.
Register Descriptions Chapter 4 GPIB-1014 User Manual 4-50 © National Instruments Corporation Function Code Registers VMEbus Address: Base Address + 29 (hex) for Memory Function Code Base Address + 3.
Chapter 4 Register Descriptions © National Instruments Corporation 4-51 GPIB-1014 User Manual Device Control Register VMEbus Address: Base Address + 04 (hex) Attributes: Read/Write, Internal to DMAC 7 6 54 32 1 0 XRM DTYP DPS 0 PCL R/W The Device Control Register (DCR) is a device-soriented control register.
Register Descriptions Chapter 4 GPIB-1014 User Manual 4-52 © National Instruments Corporation Bit Mnemonic Description 2r/w 0 Reserved Bit Write a zero to this bit. 1-0r/w PCL Peripheral Control Line Bits 1 through 0 Each of the four DMAC channels has a Peripheral Control Line (called PCL0* through PCL3*).
Chapter 4 Register Descriptions © National Instruments Corporation 4-53 GPIB-1014 User Manual Operation Control Register VMEbus Address: Base Address + 05 (hex) Attributes: Read/Write, Internal to DMAC 7 6 54 32 1 0 DIR 0 SIZE CHN REQG R/W The Operation Control Register (OCR) is an operation-oriented register.
Register Descriptions Chapter 4 GPIB-1014 User Manual 4-54 © National Instruments Corporation 10 = Array Chaining 11 = Linked Chaining Bit Mnemonic Description In most GPIB applications, either no chaining or array chaining is used. See Chapter 5 for details.
Chapter 4 Register Descriptions © National Instruments Corporation 4-55 GPIB-1014 User Manual Sequence Control Register VMEbus Address: Base Address + 06 (hex) Attributes: Read/Write, Internal to DMAC 7 6 54 32 1 0 0 0 0 0 MAC DAC R/W The Sequence Control Register (SCR) is used to define the sequencing of memory and device addresses.
Register Descriptions Chapter 4 GPIB-1014 User Manual 4-56 © National Instruments Corporation Channel Control Register VMEbus Address: Base Address + 07 (hex) Attributes: Read/Write, Internal to DMAC 7 6 54 32 1 0 STR CNT HLT SAB EINT 0 0 0 R/W This register is used to control the operation of the channel.
Chapter 4 Register Descriptions © National Instruments Corporation 4-57 GPIB-1014 User Manual 0 = Channel operation not aborted 1 = Abort channel operation Bit Mnemonic Description 3r/w EINT Interrupt Enable Bit The Interrupt Enable bit in used to enable or disable interrupts from the channel.
Register Descriptions Chapter 4 GPIB-1014 User Manual 4-58 © National Instruments Corporation Channel Status Register VMEbus Address: Base Address + 00 (hex) Attributes: Read/Write, Internal to DMAC 7 6 54 32 1 0 COC BTC NDT ERR ACT 0 PCT PCS R/W The Channel Status Register (CSR) bits are set automatically by DMAC.
Chapter 4 Register Descriptions © National Instruments Corporation 4-59 GPIB-1014 User Manual Bit Mnemonic Description 4r/w ERR Error Bit The Error bit is used to report the occurrence of error conditions. It is set if any errors have been signaled. If bit ERR is set, the CER logs the exact cause of the error.
Register Descriptions Chapter 4 GPIB-1014 User Manual 4-60 © National Instruments Corporation Channel Error Register VMEbus Address: Base Address + 01 (hex) Attributes: Read Only, Internal to DMAC 7 6 54 32 10 ERROR CODE 0 0 0 R The Channel Error Register (CER) is an error condition register.
Chapter 4 Register Descriptions © National Instruments Corporation 4-61 GPIB-1014 User Manual Channel Priority Register VMEbus Address: Base Address + 2D (hex) Attributes: Read/Write, Internal to DMAC 7 6 54 32 0 CP 0 0 0 0 0 0 R/W The Channel Priority Register (CPR) is used to define the priority level for each channel.
Register Descriptions Chapter 4 GPIB-1014 User Manual 4-62 © National Instruments Corporation Interrupt Vector Registers Each channel has a Normal Interrupt Vector Register (NIVR) and an Error Interrupt Vector Register (EIVR), each consisting of eight bits.
Chapter 4 Register Descriptions © National Instruments Corporation 4-63 GPIB-1014 User Manual General Control Register VMEbus Address: Base Address + FF (hex) Attributes: Read/Write, Internal to DMAC.
Register Descriptions Chapter 4 GPIB-1014 User Manual 4-64 © National Instruments Corporation Configuration Registers The GPIB-1014 contains two 8-bit write-only registers that are used to configure some of the board operating parameters.
Chapter 4 Register Descriptions © National Instruments Corporation 4-65 GPIB-1014 User Manual Bit Mnemonic Description 4-3w BRG Bus Request/Grant Bits The Bus Request/Grant bits are used to select which pair of the VMEbus request/grant lines are used by the GPIB-1014 to request and obtain control of the system bus.
Register Descriptions Chapter 4 GPIB-1014 User Manual 4-66 © National Instruments Corporation Configuration Register 2 (CFG2) VMEbus Address: Base Address + 105 (hex) Attributes: Write Only, Internal.
Chapter 4 Register Descriptions © National Instruments Corporation 4-67 GPIB-1014 User Manual Bit Mnemonic Description 1w LMR Local Master Reset Bit The Local Master Reset bit is used to reset the GPIB-1014 to a known state. Setting this bit to a 1 drives the local reset line active while clearing this bit releases the local reset line.
© National Instruments Corporation 5-1 GPIB-1014 User Manual Chapter 5 Programming Considerations This chapter explains the initialization process, sending/receiving messages, and the serial/parallel poll process.
Programming Considerations Chapter 5 GPIB-1014 User Manual 5-2 © National Instruments Corporation • The Transit Receive Mode 0 (TRM0) and Transit Receive Mode 1 (TRM1) bits in the Address Mode Register (ADMR) are cleared. All other TLC register contents should be considered as undefined while the LMR bit is set and after LMR has been cleared.
Chapter 5 Programming Considerations © National Instruments Corporation 5-3 GPIB-1014 User Manual 9. Load the Parallel Poll response in the Parallel Poll Register (PPR) if local configuration is used. If using remote configuration, clear the PPR. 10.
Programming Considerations Chapter 5 GPIB-1014 User Manual 5-4 © National Instruments Corporation Sending Remote Multiline Messages (Commands) The GPIB-1014 sends commands as Active Controller simply by writing to the Command/Data Out Register (CDOR) in response to the CO status bit in ISR2.
Chapter 5 Programming Considerations © National Instruments Corporation 5-5 GPIB-1014 User Manual Case 2: The TLC, as a Listener, takes control upon receipt of the Take Control Synchronously auxiliary command.
Programming Considerations Chapter 5 GPIB-1014 User Manual 5-6 © National Instruments Corporation The GPIB-1014 as GPIB Talker and Listener The TLC may be either GPIB Talker or Listener, but not both simultaneously. Either function is deactivated automatically if the other is activated.
Chapter 5 Programming Considerations © National Instruments Corporation 5-7 GPIB-1014 User Manual Address Mode 2 Address Mode 2 is used when Talker Extended (TE) or Listener Extended (LE) functions are to be used. TE and LE functions require receipt of two addresses (primary and secondary) before setting TA or LA.
Programming Considerations Chapter 5 GPIB-1014 User Manual 5-8 © National Instruments Corporation 6. When the Valid auxiliary command is issued, the TLC assumes that the My Secondary Address (MSA) me.
Chapter 5 Programming Considerations © National Instruments Corporation 5-9 GPIB-1014 User Manual In cycle steal without hold mode, upon receiving a DMA request from the TLC, the DMAC requests use of the VMEbus. Once the VMEbus is granted to the GPIB-1014, the DMAC performs the DMA transfer.
Programming Considerations Chapter 5 GPIB-1014 User Manual 5-10 © National Instruments Corporation DMA Transfers without the Carry Cycle Data Block A Total = N bytes NO CHAINING OR Total = N bytes Data Block A Data Block B Data Block C CHAINING DMAC VMEbus interrupt TLC interrupt Bus Error GPIB Sync.
Chapter 5 Programming Considerations © National Instruments Corporation 5-11 GPIB-1014 User Manual b. A 0xFF (hex) must be written to the CSR of Channel 0 to clear any leftover error or status bits. c. The DCR of Channel 0 is loaded with the proper value to select the DMA transfer mode (cycle steal without hold or cycle steal with hold).
Programming Considerations Chapter 5 GPIB-1014 User Manual 5-12 © National Instruments Corporation 4. For array or linked chaining, load the MFCR of Channel 0 with the proper data to generate the required Address Modifier Code to access the data blocks.
Chapter 5 Programming Considerations © National Instruments Corporation 5-13 GPIB-1014 User Manual DMA Transfers with the Carry Cycle Channel 0 Data Block A Total=N-1 bytes NO CHAINING OR Total=N-1 b.
Programming Considerations Chapter 5 GPIB-1014 User Manual 5-14 © National Instruments Corporation 2. Channel 0 must be configured to provide a flyby transfer for the n-1 data bytes between the GPIB and the VME system memory. The sequence is as follows: a.
Chapter 5 Programming Considerations © National Instruments Corporation 5-15 GPIB-1014 User Manual • For array or linked chaining, load the MFCR of Channel 0 with the proper data to generate the required Address Modifier Code to access the data blocks.
Programming Considerations Chapter 5 GPIB-1014 User Manual 5-16 © National Instruments Corporation i. For array or linked chaining, load the MFCR of Channel 1 with the proper value to generate the desired address modifier code, which then accesses the data blocks.
Chapter 5 Programming Considerations © National Instruments Corporation 5-17 GPIB-1014 User Manual 4. Once channels 0 and 1 have been configured properly, start the DMA channels. Start Channel 1 before starting Channel 0. The channels are started by writing to the CCRs with the STR bits set.
Programming Considerations Chapter 5 GPIB-1014 User Manual 5-18 © National Instruments Corporation • An interrupt from the TLC • A bus or DMAC error that occurred during a DMA transfer • GPIB handshake synchronization To determine which condition caused the interrupt, you must first examine the CSR of Channel 1.
Chapter 5 Programming Considerations © National Instruments Corporation 5-19 GPIB-1014 User Manual accepted by all Listeners on the GPIB (indicating a GPIB synchronization). For this reason, Channel 1 is programmed to transfer two bytes to avoid a premature COC interrupt.
Programming Considerations Chapter 5 GPIB-1014 User Manual 5-20 © National Instruments Corporation Whether terminating on the END message or the EOS message (or whenever the DMA transfer does not complete properly), the DMAC must be stopped by issuing a software abort to Channels 0 and 1 by writing to the CCR with the SAB bit set.
Chapter 5 Programming Considerations © National Instruments Corporation 5-21 GPIB-1014 User Manual Interrupts If the GPIB-1014 is enabled for interrupts, there are three events that can cause an interrupt on the VMEbus. The first event is an interrupt from the TLC.
Programming Considerations Chapter 5 GPIB-1014 User Manual 5-22 © National Instruments Corporation The TLC contains its own internal registers, which are used to control and enable interrupts. The interrupt output from the TLC, however, is sensed by the PCL of DMA Channel 1.
Chapter 5 Programming Considerations © National Instruments Corporation 5-23 GPIB-1014 User Manual Serial Polls Conducting a Serial Poll The TLC, as CIC, can serial poll other devices as described in the IEEE 488 specification.
Programming Considerations Chapter 5 GPIB-1014 User Manual 5-24 © National Instruments Corporation Although the Controller can obtain a Parallel Poll response quickly and at any time, there can be considerable front-end overhead during initialization to configure the devices to respond appropriately.
Chapter 5 Programming Considerations © National Instruments Corporation 5-25 GPIB-1014 User Manual 2. Send the GPIB UNL message to unaddress all GPIB Listeners. 3. Send the listen address of the first device to be configured. 4. Send the GPIB PPC message to all devices followed by the PPE message for that device.
© National Instruments Corporation 6-1 GPIB-1014 User Manual Chapter 6 Theory of Operation This chapter contains a functional overview of the GPIB-1014 board and explains the operation of each functional block making up the GPIB-1014.
Theory of Operation Chapter 6 GPIB-1014 User Manual 6-2 © National Instruments Corporation accomplished using an F245 8-bit data transceiver, which gates the upper data byte to the TLC. This data transceiver is automatically controlled by the DMAC signal HIBYTE*.
Chapter 6 Theory of Operation © National Instruments Corporation 6-3 GPIB-1014 User Manual Control Equations of Transceivers Table 6-1 lists the control equations for the address and data.
Theory of Operation Chapter 6 GPIB-1014 User Manual 6-4 © National Instruments Corporation address. If DS* from the master is also asserted, local signal BRDEN* is asserted. Further decoding is necessary to determine which register is being addressed.
Chapter 6 Theory of Operation © National Instruments Corporation 6-5 GPIB-1014 User Manual control the timing of local signal DTACK* when the board is a slave and signal to control RD* and WR* to the TLC (see Timing State Machine later in this chapter).
Theory of Operation Chapter 6 GPIB-1014 User Manual 6-6 © National Instruments Corporation • Enabling the Release On Request feature. Writing a 0 to this bit (ROR*) enables the Release On Request feature while writing a 1 disables the Release On Request feature.
Chapter 6 Theory of Operation © National Instruments Corporation 6-7 GPIB-1014 User Manual Configuration Register 2 Four discrete 74LS74A D-type flip-flops are used to implement Configuration Register 2 (CFG2). Data is written into each bit of this register on the rising edge of the WR* signal generated by the Timing State Machine circuitry.
Theory of Operation Chapter 6 GPIB-1014 User Manual 6-8 © National Instruments Corporation corresponds to the read access time of the TLC. Local signal SACK is asserted to drive VMEbus signal DTACK* active to indicate that the data is valid on the VMEbus data lines D07 through D00.
Chapter 6 Theory of Operation © National Instruments Corporation 6-9 GPIB-1014 User Manual DMA Gating and Control The DMA Gating and Control circuitry is designed to control the DMA request/acknowledge interface between the DMAC and the TLC.
Theory of Operation Chapter 6 GPIB-1014 User Manual 6-10 © National Instruments Corporation If the carry cycle feature is not used in a DMA transfer, the CC bit in CFG1 is 0, and DMA Gating and Control circuitry directs all DMA requests from the TLC to DMAC Channel 0.
Chapter 6 Theory of Operation © National Instruments Corporation 6-11 GPIB-1014 User Manual are some external requests for the bus. While the board is holding the bus and the DMAC requests the bus, the DMAC is immediately granted the bus, thus avoiding bus arbitration time.
Theory of Operation Chapter 6 GPIB-1014 User Manual 6-12 © National Instruments Corporation received. OWN* is asserted by the DMAC to indicate that it now has ownership of the bus. BUS_REL* is asserted by the DTB Requester and Controller circuitry to indicate that it is going to release the VMEbus.
Chapter 6 Theory of Operation © National Instruments Corporation 6-13 GPIB-1014 User Manual 4. The outputs of the 74S139 are connected to four 74LS02 gates, along with the LBROUT* signal, to assert one of the four VMEbus bus request lines (BR3* through BR0*).
Theory of Operation Chapter 6 GPIB-1014 User Manual 6-14 © National Instruments Corporation This PCL is used to detect interrupts from the GPIB-1014 that are not internal to the DMAC. A negative transition on the PCL sets the PCT bit in the CSR of DMAC Channel 1.
Chapter 6 Theory of Operation © National Instruments Corporation 6-15 GPIB-1014 User Manual accepted the byte and the Talker may have already released DAV*. For this reason, the synchronization circuitry looks at the level of the DAV* line rather than for a transition.
Theory of Operation Chapter 6 GPIB-1014 User Manual 6-16 © National Instruments Corporation 4. Clear IMR2. 5. Write a value to CFG1 to release PCL1 line (perhaps use the same value as the last write to CFG1). 6. Write a software abort to Channel 0. 7.
Chapter 6 Theory of Operation © National Instruments Corporation 6-17 GPIB-1014 User Manual Device (TLC)/DMAC Communication. Communication between the TLC and the DMAC is accomplished mainly by two signals. Each of the four DMA channels has a DMA request input (REQ0* through REQ*3) and a DMA acknowledge output (ACK0* through ACK3*).
Theory of Operation Chapter 6 GPIB-1014 User Manual 6-18 © National Instruments Corporation DMA Requests. Internal or external requests activate the DMAC to transfer an operand. The REQG bits of the OCR determine the manner in which requests are generated.
Chapter 6 Theory of Operation © National Instruments Corporation 6-19 GPIB-1014 User Manual Operands and Addressing. Three factors affect how the actual data is handled: device (destination) port size, operand (from source) size, and address sequencing.
Theory of Operation Chapter 6 GPIB-1014 User Manual 6-20 © National Instruments Corporation address the device (VMEbus memory) in dual-address transfers. It is initiated before starting the channel operation. The BAR is used only in chaining or continue operations.
Chapter 6 Theory of Operation © National Instruments Corporation 6-21 GPIB-1014 User Manual to service the request for the halted channel. When this bit is reset, the channel resumes operation and services any request that may have been received while the channel was halted.
Theory of Operation Chapter 6 GPIB-1014 User Manual 6-22 © National Instruments Corporation If the interrupt bit in the CCR is set when the BTC bit is set, an interrupt is generated.
Chapter 6 Theory of Operation © National Instruments Corporation 6-23 GPIB-1014 User Manual Start of array # of entries = 3 BAR BTC DMAC Memory Address A Transfer Count A Memory Address B Transfer Count B Memory Address C Transfer Count C Data Block A Data Block B Data Block C Address and Transfer Count Array Data Blocks Figure 6-2.
Theory of Operation Chapter 6 GPIB-1014 User Manual 6-24 © National Instruments Corporation Start of array BAR BTC DMAC Data Block A Data Block B Data Block C Address and Transfer Count Array Data Bl.
Chapter 6 Theory of Operation © National Instruments Corporation 6-25 GPIB-1014 User Manual Sources of errors are as follows: • Configuration Error This occurs when any undefined or reserved bit pattern, or illegal device/operand size combination is programmed into a channel and an attempt is made to set the STR bit.
Theory of Operation Chapter 6 GPIB-1014 User Manual 6-26 © National Instruments Corporation transfer, the Memory Address and Device Address Registers point to the location of the next operand and the Memory Transfer Counter contains the number of operands yet to be transferred.
Chapter 6 Theory of Operation © National Instruments Corporation 6-27 GPIB-1014 User Manual request is enabled for the condition. An important fact to remember is that ISR1 and ISR2 are always cleared when read, even if the condition that caused the bit to be initially set remains true.
Theory of Operation Chapter 6 GPIB-1014 User Manual 6-28 © National Instruments Corporation limited assurance that the TLC and its associated circuitry are working and that the output signals can be manipulated properly. NDAC* is the GPIB Not Data Accepted signal.
© National Instruments Corporation 7-1 GPIB-1014 User Manual Chapter 7 Diagnostic and Troubleshooting Test Procedures This chapter contains test procedures for determining if the GPIB-1014 is installed and operating correctly. The tests are similar to those used by National Instruments to verify correct hardware functioning.
Diagnostic and Troubleshooting Test Procedures Chapter 7 GPIB-1014 User Manual 7-2 © National Instruments Corporation 2. Examine any read and write routines being used in connection with the checkout procedure for errors. 3. Recheck the jumper settings described in Chapter 3.
Chapter 7 Diagnostic and Troubleshooting Test Procedures © National Instruments Corporation 7-3 GPIB-1014 User Manual 105 CFG2 = 08 Clear LMR 065 NIV1 = 55 065 NIV1 = 55? 067 EIV1 = 55 067 EIV1 = 55? 105 CFG2 = 0A Set LMR and turn LED green 105 CFG2 = 08 Clear LMR 065 NIV1 = 0F? 067 EIV1 = 0F? 5.
Diagnostic and Troubleshooting Test Procedures Chapter 7 GPIB-1014 User Manual 7-4 © National Instruments Corporation 11B AUXMR = 1E set IFC 11B AUXMR = 16 clear IFC 119 ADSR = 80? CIC 115 ISR2 = 9? CO + ADSC 11B AUXMR = 10 go to standby 119 ADSR = C0? CIC + ATN* 8.
Chapter 7 Diagnostic and Troubleshooting Test Procedures © National Instruments Corporation 7-5 GPIB-1014 User Manual daddr=FF Set data values at source locations daddr+1=FE .
Diagnostic and Troubleshooting Test Procedures Chapter 7 GPIB-1014 User Manual 7-6 © National Instruments Corporation 00A MTC0 = 0001 one byte 004 DCR0 = A0 005 OCR0 = 82 006 SCR0 = 0 000 CSR0 = FF 0.
Chapter 7 Diagnostic and Troubleshooting Test Procedures © National Instruments Corporation 7-7 GPIB-1014 User Manual 005 OCR0 = 02 045 OCR1 = 0A 006 SCR0 = 04 046 SCR1 = 04 029 MFC0 = 06 00C MAR0 = .
Diagnostic and Troubleshooting Test Procedures Chapter 7 GPIB-1014 User Manual 7-8 © National Instruments Corporation 3000 data = 0000 clear two memory locations, these will be written over by data f.
Chapter 7 Diagnostic and Troubleshooting Test Procedures © National Instruments Corporation 7-9 GPIB-1014 User Manual 113 ISR1 = 2? after transferred the first two bytes on Channel 0 and the carry cy.
© National Instruments Corporation A-1 GPIB-1014 User Manual Appendix A Hardware Specifications This appendix specifies the electrical, environmental, and physical characteristics of the GPIB-1014 board and the conditions under which it should be operated.
Hardware Specifications Appendix A GPIB-1014 User Manual A-2 © National Instruments Corporation Table A-3. Physical Characteristics Characteristic Specification Dimensions 6.
© National Instruments Corporation B-1 GPIB-1014 User Manual Appendix B Parts List and Schematic Diagrams This appendix contains the parts list and schematic diagrams for the GPIB-1014.
© National Instruments Corporation C-1 GPIB-1014 User Manual Appendix C Sample Programs This appendix contains listings of routines in 68000 assembly language code that implement the essential elements of these major utility functions: • Initialize the GPIB-1014 interface (INIT).
Sample Programs Appendix C GPIB-1014 User Manual C-2 © National Instruments Corporation ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |; | GPIB-1014 Sample Functions for Dri.
Appendix C Sample Programs © National Instruments Corporation C-3 GPIB-1014 User Manual | ISR1 Bits DI = 001 (octal) | Data in DO = 002 | Data out ERR = 004 | Error ENDRX = 020 | END received | ISR2 .
Sample Programs Appendix C GPIB-1014 User Manual C-4 © National Instruments Corporation | CSR Bits CLRS = 0377 | Clear all status bits COC = 0200 | Channel operation complete CERR = 020 | Error in ch.
Appendix C Sample Programs © National Instruments Corporation C-5 GPIB-1014 User Manual | | * * * * * * * * * * * * * * * * | * INITIALIZE - INIT * | * * * * * * * * * * * * * * * * | | Summary: | - .
Sample Programs Appendix C GPIB-1014 User Manual C-6 © National Instruments Corporation | 68000 Code | Comments | -------------------------------------------------------------------------------------.
Appendix C Sample Programs © National Instruments Corporation C-7 GPIB-1014 User Manual | | * * * * * * * * * * * * * * * * * * * * * * | * INTERFACE CLEAR - IFC * | * * * * * * * * * * * * * * * * *.
Sample Programs Appendix C GPIB-1014 User Manual C-8 © National Instruments Corporation | | * * * * * * * * * * * * * * * * * * * * | * REMOTE ENABLE - REN * | * * * * * * * * * * * * * * * * * * * *.
Appendix C Sample Programs © National Instruments Corporation C-9 GPIB-1014 User Manual | | * * * * * * * * * * * * * * * | * RECEIVE - RCV * | * * * * * * * * * * * * * * * | | Summary: | - Called b.
Sample Programs Appendix C GPIB-1014 User Manual C-10 © National Instruments Corporation | 68000 Code | Comments --------------------------------------------------------------------------------------.
Appendix C Sample Programs © National Instruments Corporation C-11 GPIB-1014 User Manual | RCV4: btst #COC,CSR0 | Calculate number of bytes transferred bne RCV5 | movw MTC0,d1 | subw d1,d0 | btst #EC.
Sample Programs Appendix C GPIB-1014 User Manual C-12 © National Instruments Corporation | | * * * * * * * | * READ * | * * * * * * * | Summary: | - Called to read device-dependent (data) messages | .
Appendix C Sample Programs © National Instruments Corporation C-13 GPIB-1014 User Manual | 68000 Code | Comments --------------------------------------------------------------------------------------.
Sample Programs Appendix C GPIB-1014 User Manual C-14 © National Instruments Corporation | | * * * * * * * * * * * * * * * * * * | * DATA SEND - DSEND * | * * * * * * * * * * * * * * * * * * | | Summ.
Appendix C Sample Programs © National Instruments Corporation C-15 GPIB-1014 User Manual | 68000 Code | Comments --------------------------------------------------------------------------------------.
Sample Programs Appendix C GPIB-1014 User Manual C-16 © National Instruments Corporation DSEND4: btst #COC,CSR0 | Calculate number of bytes transferred bne DSEND5 | movw MTC0,d1 | subw d1,d0 | btst #.
Appendix C Sample Programs © National Instruments Corporation C-17 GPIB-1014 User Manual | | * * * * * * * * * | * WRITE * | * * * * * * * * * | | Summary: | - Called to send device-dependent (data) .
Sample Programs Appendix C GPIB-1014 User Manual C-18 © National Instruments Corporation | 68000 Code | Comments --------------------------------------------------------------------------------------.
Appendix C Sample Programs © National Instruments Corporation C-19 GPIB-1014 User Manual | | * * * * * * * * * * * * * * * * * * * * * * | * COMMAND SEND - CSEND * | * * * * * * * * * * * * * * * * *.
Sample Programs Appendix C GPIB-1014 User Manual C-20 © National Instruments Corporation | | * * * * * * * * * * * * * * * | * COMMAND - CMD * | * * * * * * * * * * * * * * * | | Summary: | - Send GP.
Appendix C Sample Programs © National Instruments Corporation C-21 GPIB-1014 User Manual | | * * * * * * * * * * * * * * * * * * * * * * | * PASS CONTROL - PASSC * | * * * * * * * * * * * * * * * * *.
© National Instruments Corporation D- 1 GPIB-1014 User Manual Appendix D Multiline Interface Messages This appendix lists the multiline interface messages and describes the mnemonics and messages that correspond to the interface functions.
Multiline Interface Messages Appendix D GPIB-1014 User Manual D- 2 © National Instruments Corporation Multiline Interface Messages Hex Oct Dec ASCII Msg Hex Oct Dec ASCII Msg 00 000 0 NUL 20 040 32 S.
Appendix D Multiline Interface Messages © National Instruments Corporation D- 3 GPIB-1014 User Manual Multiline Interface Messages Hex Oct Dec ASCII Msg Hex Oct Dec ASCII Msg 40 100 64 @ MTA0 60 140 .
© National Instruments Corporation E-1 GPIB-1014 User Manual Appendix E Operation of the GPIB This chapter describes the operation of the GPIB. Communication among interconnected GPIB devices is achieved by passing messages through the interface system.
Operation of the GPIB Appendix E GPIB-1014 User Manual E-2 © National Instruments Corporation Some bus configurations do not require a Controller. For example, one device may always be a Talker (called a Talk-only device) and there may be one or more Listen-only devices.
Appendix E Operation of the GPIB © National Instruments Corporation E-3 GPIB-1014 User Manual NRFD (not ready for data) NRFD indicates when a device is ready or not ready to receive a message byte. The line is driven by all devices when receiving commands and by Listeners when receiving data messages.
Operation of the GPIB Appendix E GPIB-1014 User Manual E-4 © National Instruments Corporation Physical and Electrical Characteristics Devices are usually connected with a cable assembly consisting of a shielded 24 conductor cable with both a plug and receptacle connector at each end.
Appendix E Operation of the GPIB © National Instruments Corporation E-5 GPIB-1014 User Manual Figure E-2. Linear Configuration.
Operation of the GPIB Appendix E GPIB-1014 User Manual E-6 © National Instruments Corporation Figure E-3. Star Configuration Configuration Requirements To achieve the high data transfer rate that the GPIB was designed for, the physical distance between devices and the number of devices on the bus are limited.
Appendix E Operation of the GPIB © National Instruments Corporation E-7 GPIB-1014 User Manual Bus extenders are available from National Instruments and other manufacturers for use when these limits must be exceeded.
© National Instruments Corporation F-1 GPIB-1014 User Manual Appendix F Mnemonics Key This appendix contains a mnemonics key that defines the mnemonics (abbreviations) used throughout this manual for functions, remote messages, local messages, states, bits, registers, integrated circuits, system functions, and VMEbus operations and signals.
Mnemonics Key Appendix F GPIB-1014 User Manual F-2 © National Instruments Corporation Mnemonic Type Definition A A[01-31] VBS Address Lines 1 through 31 ACDS ST Acceptor Data State (AH function) ACFA.
Appendix F Mnemonics Key © National Instruments Corporation F-3 GPIB-1014 User Manual BG[0-3]OUT* VBS Bus Grant Out Lines BIN B Binary Bit BLT VBO Block Transfer BR[0-3]* VBS Bus Request Lines.
Mnemonics Key Appendix F GPIB-1014 User Manual F-4 © National Instruments Corporation C C F Controller CACS ST Controller Active State (C function) CADS ST Controller Addressed State CAWS ST Controll.
Appendix F Mnemonics Key © National Instruments Corporation F-5 GPIB-1014 User Manual DEN* LS Data Enable DET B Device Execute Trigger Bit DET IE B Enable Interrupt on Device Execute Trigger Bit DHDC.
Mnemonics Key Appendix F GPIB-1014 User Manual F-6 © National Instruments Corporation F FH LM Finish Handshake FIN LS GPIB DMA Transfer Finished G GET RM Group Execute Trigger GND VBS Ground GTL RM G.
Appendix F Mnemonics Key © National Instruments Corporation F-7 GPIB-1014 User Manual L L F Listener LA B Listener Active Bit LACS ST Listener Active State (L function) LADS ST Listener Addressed Sta.
Mnemonics Key Appendix F GPIB-1014 User Manual F-8 © National Instruments Corporation O OSA RM Other Secondary Address OTA RM Other Talk Address P P[3-1] B Parallel Poll Response Bits 3 through 1 PAC.
Appendix F Mnemonics Key © National Instruments Corporation F-9 GPIB-1014 User Manual rsv LM Request Service rtl LM Return To Local RWD B Release When Done Bit RWLS ST Remote With Lockout State S S B.
Mnemonics Key Appendix F GPIB-1014 User Manual F-10 © National Instruments Corporation SYSCLK* VBS System Clock SYSFAIL* VBS System Fail SYSRESET* VBS System Reset T T F Talker TA B Talker Active Bit.
Appendix F Mnemonics Key © National Instruments Corporation F-11 GPIB-1014 User Manual U U B Unconfigure Bit UAT VBO Unaligned Transfer UCG RM Universal Command Group UDPCF LM Undefined Primary Comma.
© National Instruments Corporation G- 1 GPIB-1014 User Manual Appendix G Customer Communication For your convenience, this appendix contains forms to help you gather the information necessary to help us solve technical problems you might have as well as a form you can use to comment on the product documentation.
Technical Support Form ____________________________________________________ Photocopy this form and update it each time you make changes to your software or hardware, and use the completed copy of this form as a reference for your current configuration.
GPIB-1014 Hardware and Software Configuration Form Record the settings and revisions of your hardware and software on the line to the right of each item. Update this form each time you revise your software or hardware configuration, and use this form as a reference for your current configuration.
• Type of other boards installed and their respective hardware settings: Board Type Base I/O Address Interrupt Level DMA Channel.
Documentation Comment Form National Instruments encourages you to comment on the documentation supplied with our products. This information helps us provide quality products to meet your needs. Title: GPIB-1014 User Manual Edition Date: March 1997 Part Number: 320030-01 Please comment on the completeness, clarity, and organization of the manual.
© National Instruments Corporation Glossary-1 GPIB-1014 User Manual Glossary ___________________________________________________ Prefix Meaning Value n- µ - m- k- M- nano- micro- milli- kilo- mega- .
GPIB-1014 User Manual Index- 1 © National Instruments Corporation Index Numbers 0 (Reserved Bit) Channel Error Register, 4-60 Channel Priority Register, 4-61 Channel Status Register, 4-59 Configurati.
Index © National Instruments Corporation Index- 2 GPIB-1014 User Manual Memory Address Register (MAR), 4-48 theory of operation, 6-17 Address Status Register (ADSR), 4-20 to 4-21 addressed implementation of Talker and Listener, 5-6 to 5-8 ADM[1-0] (Address Mode Bits 1 through 0), 4-23 to 4-24 ADMR.
Index GPIB-1014 User Manual Index- 3 © National Instruments Corporation C cabling, 3-10 capability codes for GPIB-1014, 2-13 to 2-15 CC (Carry Cycle Bit), 4-65 CCR. See Channel Control Register (CCR). CDO[7-0] (Command/Data Out Bits 7 through 0), 4-7 CDOR.
Index © National Instruments Corporation Index- 4 GPIB-1014 User Manual commands or command messages, E-1 multiline GPIB commands (table), 4-25 to 4-26, D-2 to D-3 compare address lines location of, .
Index GPIB-1014 User Manual Index- 5 © National Instruments Corporation VMEbus, 6-3 data or data messages, E-1 DATA SEND-DSEND sample program, C-14 to C-16 data transfer bus (DTB) requester description of, 2-7 VMEbus modules not provided, 2-7 data transfer features.
Index © National Instruments Corporation Index- 6 GPIB-1014 User Manual DMA gating and control circuitry, 6-7 to 6-8 DMA registers 68450 internal DMA registers (chart), 2-5 Address Registers, 4-48 Ba.
Index GPIB-1014 User Manual Index- 7 © National Instruments Corporation continue mode of operation, 6-18 halt, 6-18 initiating the operation, 6-18 interrupt enable, 6-19 software abort, 6-18 overview.
Index © National Instruments Corporation Index- 8 GPIB-1014 User Manual E EINT (Interrupt Enable Bit), 4-57, 4-62, 6-19 electrical characteristics. See physical and electrical characteristics.
Index GPIB-1014 User Manual Index- 9 © National Instruments Corporation parts list and schematic diagrams, B-1 to B-9 theory of operation 68450 DMAC, 6-14 to 6-23 address decoding, 6-3 to 6-4 clock a.
Index © National Instruments Corporation Index- 10 GPIB-1014 User Manual GPIB-1014 compatibility, 1-1 GPIB-1014 compliance levels, 2-15 IFC (interface clear) line, E-3 Immediate Execute Pon command codes for, 4-28 description, 4-29 IMR1. See Interrupt Mask Register 1 (IMR1).
Index GPIB-1014 User Manual Index- 11 © National Instruments Corporation register map, 4-1 Serial Poll Mode Register (SPMR), 4-19 Serial Poll Status Register (SPSR), 4-19 writing to hidden registers, 4-4 Internal Counter Register (ICR), 4-34 interrupt control.
Index © National Instruments Corporation Index- 12 GPIB-1014 User Manual LMR (Local Master Reset Bit), 4-67 Local Unlisten command codes for, 4-28 description, 4-32 LOK (Lockout Bit), 4-16 LOKC (Lock.
Index GPIB-1014 User Manual Index- 13 © National Instruments Corporation OCR. See Operation Control Register. operands and addressing, DMAC channel operation, 6-17 operating environment, A-1 Operatio.
Index © National Instruments Corporation Index- 14 GPIB-1014 User Manual COMMAND SEND-CSEND, C-19 DATA SEND-DSEND, C-14 to C-16 GPIB-1014 Sample Functions for Driver, C-2 to C-4 INITIALIZE-INIT, C-5 .
Index GPIB-1014 User Manual Index- 15 © National Instruments Corporation overview, 5-6 programmed implementation, 5-6 R READ sample program, C-12 to C-13 RECEIVE-RCV sample program, C-11 receiving messages.
Index © National Instruments Corporation Index- 16 GPIB-1014 User Manual Interrupt Status Register 1 (ISR1), 4-8 to 4-13 Interrupt Status Register 2 (ISR2), 4-14 to 4-18 µ PD7210 internal GPIB inter.
Index GPIB-1014 User Manual Index- 17 © National Instruments Corporation SCR. See Sequence Control Register. SDC (Selected Device Clear) command, 4-25 Send EOI (SEOI) command codes for, 4-28 descript.
Index © National Instruments Corporation Index- 18 GPIB-1014 User Manual REN (remote enable), E-3 SRQ (service request), E-3 VMEbus signals chart of, 2-1 to 2-2 control signals, 6-2 operation, 6-1 to.
Index GPIB-1014 User Manual Index- 19 © National Instruments Corporation codes for, 4-28 description, 4-31 Talker/Listener/Controller (TLC). See also Controller function; DMAC channel operation.
Index © National Instruments Corporation Index- 20 GPIB-1014 User Manual definition of, 2-12 theory of operation DMA cycles, 6-7 overview, 6-6 slave cycles, 6-6 to 6-7 TLC.
Index GPIB-1014 User Manual Index- 21 © National Instruments Corporation troubleshooting test procedures DMA stand alone testing, 6-24 GPIB interface testing, 6-24 hardware installation tests, 7-2 to.
Index GPIB-1014 User Manual Index- 23 © National Instruments Corporation X X (Don't Care Bit), 4-42, 4-50 XEOS (Transmit END with EOS Bit), 4-37 XRM (External Request Mode Bits 7 through 6), 4-5.
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