NECメーカーuPD75P3116の使用説明書/サービス説明書
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1994 DATA SHEET The µ PD75P3116 replaces the µ PD753108’s internal mask ROM with a one-time PROM, and features expanded ROM capacity. Because the µ PD75P3116 supports programming by users, it is suitable for use in evaluation of systems in the development stage using the µ PD753104, 753106, or 753108, and for use in small-scale production.
µ PD75P31 16 2 Data Sheet U11369EJ3V0DS FUNCTION OUTLINE Item Function Instruction execution time • 0.95, 1.91, 3.81, or 15.3 µ s (main system clock: @ 4.19 MHz) • 0.67, 1.33, 2.67, or 10.7 µ s (main system clock: @ 6.0 MHz) • 122 µ s (subsystem clock: @ 32.
µ PD75P31 16 3 Data Sheet U11369EJ3V0DS CONTENTS 1. PIN CONFIGURATION (TOP VIEW) ................................................................................................. 4 2. BLOCK DIAGRAM ....................................................
µ PD75P31 16 4 Data Sheet U11369EJ3V0DS 1. PIN CONFIGURATION (TOP VIEW) • 64-pin plastic QFP (14 × 14): µ PD75P3116GC-AB8 • 64-pin plastic LQFP (12 × 12): µ PD75P3116GK-8A8 • 64-pin plastic LQFP (14 × 14): µ PD75P3116GC-8BS Note Always connect the V PP pin directly to V DD during normal operation.
µ PD75P31 16 5 Data Sheet U11369EJ3V0DS PIN IDENTIFICATIONS P00 to P03: Port 0 COM0 to COM3: Common output 0 to 3 P10 to P13: Port 1 V LC0 to V LC2 : LCD power supply 0 to 2 P20 to P23: Port 2 BIAS: .
µ PD75P31 16 6 Data Sheet U11369EJ3V0DS 2. BLOCK DIAGRAM P20 to P23 P00 to P03 S0 to S15 16 4 4 4 4 4 4 4 4 COM0 to COM3 4 BIAS f LCD V PP V DD RESET Vss CPU clock Φ Standby control X2 X1 XT2 XT1 Sy.
µ PD75P31 16 7 Data Sheet U11369EJ3V0DS 3. PIN FUNCTIONS 3.1 Port Pins (1/2) Pin Name I/O Alternate Function 8-Bit Status I/O Circuit Function I/O After Reset Type Note 1 P00 Input INT4 4-bit input port (Port 0) — Input <B> Connection of an internal pull-up resistor can be P01 SCK specified by a software setting in 3-bit units.
µ PD75P3116 8 Data Sheet U11369EJ3V0DS 3.1 Port Pins (2/2) Pin Name I/O Alternate Function 8-Bit Status I/O Circuit Function I/O After Reset Type Note 1 P60 I/O KR0/D0 Programmable 4-bit I/O port (Port 6) — Input <F>-A Input and output can be specified in 1-bit units.
µ PD75P31 16 9 Data Sheet U11369EJ3V0DS 3.2 Non-Port Pins (1/2) Pin Name I/O Alternate Function Status I/O Circuit Function After Reset Type Note 1 TI0 Input P13 External event pulse input to timer/e.
µ PD75P31 16 10 Data Sheet U11369EJ3V0DS 3.2 Non-Port Pins (2/2) Pin Name I/O Alternate Function Status I/O Circuit Function After Reset Type S0 to S15 Output — Segment signal output Note 1 G-A S16.
µ PD75P3116 11 Data Sheet U11369EJ3V0DS 3.3 Pin I/O Circuits The I/O circuits for the µ PD75P3116’s pins are shown in abbreviated form below. IN V DD P-ch N-ch V DD P-ch N-ch OUT Data Output disable IN V DD P-ch IN/OUT P.U.R. enable Data P.U.R. Type D Output disable P.
µ PD75P31 16 12 Data Sheet U11369EJ3V0DS (Continued) Type F-B Type H Type M-C Type G-A Type G-B Type M-E Output disable V DD P-ch N-ch IN/OUT Data V DD P-ch P.U.R. enable P.U.R. Output disable (N) Output disable (P) P.U.R. : Pull-Up Resistor IN/OUT Type G-A Type E-B SEG data Output disable Data V DD P-ch IN/OUT P.
µ PD75P3116 13 Data Sheet U11369EJ3V0DS 3.4 Recommended Connection of Unused Pins Table 3-1. List of Unused Pin Connections Pin Recommended Connection P00/INT4 Connect to Vss or V DD . P01/SCK Input: Independently connect to Vss or V DD via a resistor.
µ PD75P3116 14 Data Sheet U11369EJ3V0DS 4. Mk I AND Mk II MODE SELECTION FUNCTION Setting the stack bank selection (SBS) register for the µ PD75P3116 enables the program memory to be switched between the Mk I mode and Mk II mode. This function is applicable when using the µ PD75P3116 to evaluate the µ PD753104, 753106, or 753108.
µ PD75P3116 15 Data Sheet U11369EJ3V0DS 4.2 Setting of Stack Bank Selection (SBS) Register Use the stack bank selection register to switch between the Mk I mode and Mk II mode. Figure 4-1 shows the format of the stack bank selection register. The stack bank selection register is set using a 4-bit memory manipulation instruction.
µ PD75P3116 16 Data Sheet U11369EJ3V0DS 5. DIFFERENCES BETWEEN µ PD75P3116 AND µ PD753104, 753106, 753108 The µ PD75P3116 replaces the internal mask ROM in the µ PD753104, 753106, and 753108 with a one-time PROM and features expanded ROM capacity.
µ PD75P31 16 17 Data Sheet U11369EJ3V0DS 6. MEMORY CONFIGURATION Figure 6-1. Program Memory Map Note Can only be used in the Mk II mode. Remark For instructions other than those noted above, the BR PCDE and BR PCXA instructions can be used to branch to addresses with changes in the PC’s lower 8 bits only.
µ PD75P31 16 18 Data Sheet U11369EJ3V0DS Figure 6-2. Data Memory Map Note Memory bank 0 or 1 can be selected as the stack area. (32 × 4) 256 × 4 (224 × 4) 128 × 4 0 1 15 000H 01FH 020H 0FFH 100H .
µ PD75P3116 19 Data Sheet U11369EJ3V0DS 7. INSTRUCTION SET (1) Representation and coding formats for operands In the instruction’s operand area, use the following coding format to describe operands.
µ PD75P31 16 20 Data Sheet U11369EJ3V0DS (2) Operation conventions A: A register; 4-bit accumulator B: B register C: C register D: D register E: E register H: H register L: L register X: X register X.
µ PD75P3116 21 Data Sheet U11369EJ3V0DS (3) Description of symbols used in addressing area Remarks 1. MB indicates access-enabled memory banks. 2. In area *2, MB = 0 for both MBE and MBS. 3. In areas *4 and *5, MB = 15 for both MBE and MBS. 4. Areas *6 to *11 indicate corresponding address-enabled areas.
µ PD75P3116 22 Data Sheet U11369EJ3V0DS Instruction Mnemonic Operand No. of Machine Operation Addressing Skip Group Bytes Cycle Area Condition Transfer MOV A, #n4 1 1 A ← n4 String-effect A reg1, #.
µ PD75P3116 23 Data Sheet U11369EJ3V0DS Instruction Mnemonic Operand No. of Machine Operation Addressing Skip Group Bytes Cycle Area Condition Bit transfer MOV1 CY, fmem.bit 2 2 CY ← (fmem.bit) *4 CY, pmem.@L 2 2 CY ← (pmem 7-2 +L 3-2 .bit(L 1-0 )) *5 CY, @H+mem.
µ PD75P3116 24 Data Sheet U11369EJ3V0DS Instruction Mnemonic Operand No. of Machine Operation Addressing Skip Group Bytes Cycle Area Condition Comparison SKE reg, #n4 2 2+S Skip if reg=n4 reg = n4 @H.
µ PD75P31 16 25 Data Sheet U11369EJ3V0DS Instruction Mnemonic Operand No. of Machine Operation Addressing Skip Group Bytes Cycle Area Condition Branch BR Note 1 addr —— PC 13-0 ← addr *6 Use the assembler to select the most appropriate instruction among the following.
µ PD75P31 16 26 Data Sheet U11369EJ3V0DS Instruction Mnemonic Operand No. of Machine Operation Addressing Skip Group Bytes Cycle Area Condition Subroutine CALLA Note !addr1 3 3 (SP–6)(SP–3)(SP–.
µ PD75P31 16 27 Data Sheet U11369EJ3V0DS Instruction Mnemonic Operand No. of Machine Operation Addressing Skip Group Bytes Cycle Area Condition Subroutine PUSH rp 1 1 (SP–1)(SP–2) ← rp, SP ← .
µ PD75P3116 28 Data Sheet U11369EJ3V0DS 8. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY The program memory contained in the µ PD75P3116 is a 16384 × 8-bit one-time PROM that can be electrically written one time only. The pins listed in the table below are used for this PROM’s write/verify operations.
µ PD75P3116 29 Data Sheet U11369EJ3V0DS 8.2 Program Memory Write Procedure Program memory can be written at high speed using the following procedure. (1) Pull down unused pins to Vss via resistors. Set the X1 pin to low. (2) Supply 5 V to the V DD and V PP pins.
µ PD75P31 16 30 Data Sheet U11369EJ3V0DS V PP V DD V DD + 1 V DD V PP V DD X1 Data output Data output MD0/P30 MD2/P32 MD3/P33 MD1/P31 “ L ” D0/P60 to D3/P63 D4/P50 to D7/P53 8.3 Program Memory Read Procedure The µ PD75P3116 can read program memory contents using the following procedure.
µ PD75P3116 31 Data Sheet U11369EJ3V0DS 8.4 One-Time PROM Screening Due to its structure, the one-time PROM cannot be fully tested before shipment by NEC. Therefore, NEC recommends that after the required data is written and the PROM is stored under the temperature and time conditions shown below, the PROM should be verified via screening.
µ µ µ µ µ PD75P31 16 32 Data Sheet U11369EJ3V0DS 9. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (T A = 25˚C) Parameter Symbol Test Conditions Rating Unit Power supply voltage V DD –0.3 to +7.0 V PROM power supply V PP –0.3 to +13.5 V voltage Input voltage V I1 Except port 5 –0.
µ µ µ µ µ PD75P31 16 33 Data Sheet U11369EJ3V0DS Main System Clock Oscillator Characteristics (T A = –40 to +85 ° C, V DD = 1.8 to 5.5 V) Resonator Recommended Constant Parameter Test Conditions MIN.
µ PD75P31 16 34 Data Sheet U11369EJ3V0DS Subsystem Clock Oscillator Characteristics (T A = –40 to +85˚C, V DD = 1.8 to 5.5 V) Resonator Recommended Constant Parameter Test Conditions MIN. TYP. MAX. Unit Crystal Oscillation 32 32.768 35 kHz resonator frequency (f XT ) Note 1 Oscillation V DD = 4.
µ µ µ µ µ PD75P31 16 35 Data Sheet U11369EJ3V0DS DC Characteristics (T A = –40 to +85˚C, V DD = 1.8 to 5.5 V) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit Output current, low I OL Per pin 15 mA Total of all pins 150 mA Input voltage, high V IH1 Ports 2, 3, 8, and 9 2.
µ µ µ µ µ PD75P31 16 36 Data Sheet U11369EJ3V0DS DC Characteristics (T A = –40 to +85˚C, V DD = 1.8 to 5.5 V) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit LCD drive voltage V LCD VAC0 = 0 T A = – 40 to +85 ° C 2.7 V DD V T A = – 10 to +85 ° C 2.
µ PD75P3116 37 Data Sheet U11369EJ3V0DS AC Characteristics (T A = –40 to +85˚C, V DD = 1.8 to 5.5 V) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit CPU clock cycle t CY Operating on V DD = 2.7 to 5.5 V 0.67 64 µ s time Note 1 main system clock V DD = 1.
µ µ µ µ µ PD75P31 16 38 Data Sheet U11369EJ3V0DS Serial Transfer Operation 2-wire and 3-wire serial I/O mode (SCK...Internal clock output): (T A = –40 to +85˚C, V DD = 1.8 to 5.5 V) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit SCK cycle time t KCY1 V DD = 2.
µ µ µ µ µ PD75P31 16 39 Data Sheet U11369EJ3V0DS SBI mode (SCK...Internal clock output (master)): (T A = –40 to +85˚C, V DD = 1.8 to 5.5 V) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit SCK cycle time t KCY3 V DD = 2.7 to 5.5 V 1300 ns V DD = 1.
µ PD75P31 16 40 Data Sheet U11369EJ3V0DS AC Timing Test Points (Excluding X1, XT1 Input) Clock Timing TI0, TI1, TI2 Timing TI0, TI1, TI2 1/f TI t TIL t TIH X1 input 1/f X t XL t XH 0.1 V V DD – 0.1 V XT1 input 1/f XT t XTL t XTH 0.1 V V DD – 0.1 V V IH (MIN.
µ PD75P31 16 41 Data Sheet U11369EJ3V0DS Serial Transfer Timing 3-wire serial I/O mode 2-wire serial I/O mode t KCY1, 2 t KL1, 2 t KH1, 2 SCK SI SO t SIK1, 2 t KSI1, 2 t KSO1, 2 Input data Output dat.
µ PD75P31 16 42 Data Sheet U11369EJ3V0DS t KCY3, 4 t KH3, 4 t KSI3, 4 t SIK3, 4 t KSO3, 4 SCK SB0, 1 t KL3, 4 t SBK t KSB t KCY3, 4 t KH3, 4 t KSI3, 4 t SIK3, 4 t KSO3, 4 SCK SB0, 1 t KL3, 4 t SBK t .
µ PD75P31 16 43 Data Sheet U11369EJ3V0DS Data Memory Stop Mode Low Supply Voltage Data Retention Characteristics (T A = –40 to +85˚C) Parameter Symbol Test Conditions MIN.
µ PD75P31 16 44 Data Sheet U11369EJ3V0DS Data Retention Timing (STOP Mode Release by RESET) Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal) V DD RESET STOP instr.
µ µ µ µ µ PD75P31 16 45 Data Sheet U11369EJ3V0DS DC Programming Characteristics (T A = 25 ± 5˚C, V DD = 6.0 ± 0.25 V, V PP = 12.5 ± 0.3 V, V SS = 0 V) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit Input voltage, high V IH1 Except X1 and X2 pins 0.
µ PD75P31 16 46 Data Sheet U11369EJ3V0DS Program Memory Write Timing Program Memory Read Timing t VPS t VDS t XH t XL t I t DS t DH t DV t DF t DS t DH t AH t AS t PW t M1R t M0S t OPW t M1S t M1H t .
µ µ µ µ µ PD75P31 16 47 Data Sheet U11369EJ3V0DS 10. CHARACTERISTIC CURVES (REFERENCE VALUES) 10 5.0 1.0 0.5 0.1 0.05 0.01 0.005 0.001 012345678 (T A = 25 ° C) Supply voltage V DD (V) Supply current I DD (mA) PCC = 0010 PCC = 0001 PCC = 0000 Main system clock HALT mode + 32 kHz oscillation XT1 XT2 X1 X2 Crystal resonator 6.
µ µ µ µ µ PD75P31 16 48 Data Sheet U11369EJ3V0DS 10 5.0 1.0 0.5 0.1 0.05 0.01 0.005 0.001 012345678 XT1 XT2 X1 X2 Crystal resonator 4.19 MHz Crystal resonator 32.
µ PD75P31 16 49 Data Sheet U11369EJ3V0DS 48 49 32 64 1 17 16 33 64-PIN PLASTIC QFP (14x14) NOTE Each lead centerline is located within 0.15 mm of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS A B D G 17.6 ± 0.4 14.0 ± 0.2 0.
µ PD75P31 16 50 Data Sheet U11369EJ3V0DS 64-PIN PLASTIC LQFP (12x12) NOTE Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS A B D G 14.8 ± 0.4 12.0 ± 0.2 0.13 1.125 I 14.8 ± 0.
µ PD75P31 16 51 Data Sheet U11369EJ3V0DS 64-PIN PLASTIC LQFP (14x14) NOTE Each lead centerline is located within 0.20 mm of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS A B D G 17.2 ± 0.2 14.0 ± 0.2 0.8 (T.P.) 1.0 J 17.2 ± 0.
µ PD75P31 16 52 Data Sheet U11369EJ3V0DS 12. RECOMMENDED SOLDERING CONDITIONS The µ PD75P3116 should be soldered and mounted under the conditions recommended in the table below. For details of recommended soldering conditions, refer to the information document Semiconductor Device Mounting Technology Manual (C10535E).
µ PD75P31 16 53 Data Sheet U11369EJ3V0DS Table 12-1. Surface Mounting Type Soldering Conditions (2/2) (3) µ PD75P3116GC-8BS: 64-pin plastic LQFP (14 × 14) Soldering Soldering Conditions Recommended Method Condition Symbol Infrared reflow Package peak temperature: 235 ° C, Time: 30 seconds max.
µ PD75P31 16 54 Data Sheet U11369EJ3V0DS APPENDIX A. LIST OF µ PD75308B, 753108, AND 75P3116 FUNCTIONS Parameter µ PD75308B µ PD753108 µ PD75P3116 Program memory Mask ROM Mask ROM One-time PROM 0.
µ PD75P31 16 55 Data Sheet U11369EJ3V0DS Parameter µ PD75308B µ PD753108 µ PD75P3116 Clock output (PCL) Φ , 524, 262, 65.5 kHz • Φ , 524, 262, 65.5 kHz (Main system clock: (Main system clock: during 4.19 MHz operation) during 4.19 MHz operation) • Φ , 750, 375, 93.
µ PD75P3116 56 Data Sheet U11369EJ3V0DS APPENDIX B. DEVELOPMENT TOOLS The following development tools have been provided for system development using the µ PD75P3116. In the 75XL Series, a common relocatable assembler is used in combination with a device file dedicated to each model.
µ PD75P31 16 57 Data Sheet U11369EJ3V0DS PROM Write Tools Hardware PG-1500 This is a PROM writer that can program a single-chip microcontroller with PROM in stand-alone mode or under the control of a host machine when connected with the supplied accessory board and optional programmer adapter.
µ PD75P3116 58 Data Sheet U11369EJ3V0DS Debugging Tools An in-circuit emulator (IE-75001-R) is provided as a program debugging tool for the µ PD75P3116.
µ PD75P3116 59 Data Sheet U11369EJ3V0DS OS for IBM PCs The following operating systems for IBM PCs are supported. OS Version PC DOS TM Ver.3.1 to 6.3 J6.1/V Note to J6.3/V Note MS-DOS Ver.5.0 to 6.2 5.0/V Note to 6.2/V Note IBM DOS TM J5.02/V Note Note Only English mode is supported.
µ PD75P31 16 60 Data Sheet U11369EJ3V0DS Package Drawing and Recommended Footprint of Conversion Socket (EV-9200GC-64) Figure B-1. EV-9200GC-64 Package Drawing (For Reference Only) A F 1 E EV-9200GC-64 B D C M N L K R Q I H P O S T J G No.1 pin index EV-9200GC-64-G0E ITEM MILLIMETERS INCHES A B C D E F G H I J K L M N O P Q R S T 18.
µ PD75P31 16 61 Data Sheet U11369EJ3V0DS Figure B-2. EV-9200GC-64 Recommended Footprint (For Reference Only) F E D G H I J K L C B A 0.031 × 0.591=0.472 0.031 × 0.591=0.472 EV-9200GC-64-P1E ITEM MILLIMETERS INCHES A B C D E F G H I J K L 19.5 14.8 14.
µ PD75P31 16 62 Data Sheet U11369EJ3V0DS Package Drawing of Conversion Adapter (TGK-064SBW) Figure B-3. TGK-064SBW Package Drawing (For Reference Only) ITEM MILLIMETERS INCHES b 1.85 0.073 c 3.5 0.138 a 0.3 0.012 d 2.0 0.079 h 5.9 0.232 i 0.8 0.031 j 2.
µ PD75P31 16 63 Data Sheet U11369EJ3V0DS Notes on Target System Design The following shows a diagram of the connection conditions between the emulation probe, conversion connector and conversion socket or conversion adapter. Design your system making allowances for conditions such as the form of parts mounted on the target system, as shown below.
µ PD75P31 16 64 Data Sheet U11369EJ3V0DS Figure B-6. Connection Conditions of Target System (1) Figure B-7. Connection Conditions of Target System (2) In-circuit emulator IE-75001-R External sense clips Target system Conversion socket EV-9200GC-64 64-pin GC EP-753108GC-R Ground clip 35 mm 35 mm 18.
µ PD75P31 16 65 Data Sheet U11369EJ3V0DS APPENDIX C. RELATED DOCUMENTS The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices Document Name Document No.
µ PD75P31 16 66 Data Sheet U11369EJ3V0DS Other Related Documents Document Name Document No. SEMICONDUCTOR SELECTION GUIDE – Products & Packages – X13769E Semiconductor Device Mounting Technol.
µ PD75P31 16 67 Data Sheet U11369EJ3V0DS [MEMO].
µ PD75P3116 68 Data Sheet U11369EJ3V0DS NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation.
µ PD75P3116 69 Data Sheet U11369EJ3V0DS Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors.
µ PD75P3116 QTOP is a trademark of NEC Corporation. MS-DOS is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. IBM DOS, PC/AT, and PC DOS are trademarks of International Business Machines Corporation.
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NEC uPD75P3116を既にお持ちだが、まだ読んでいない場合は、上記の理由によりそれを行うべきです。そうすることにより機能を適切に使用しているか、又はNEC uPD75P3116の不適切な取り扱いによりその寿命を短くする危険を犯していないかどうかを知ることができます。
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