Omega EngineeringメーカーOME-A8111の使用説明書/サービス説明書
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OME-A-8111 Hardware User’s Manual OME-A-8111 Hardware Manual (ver.1.1, Jul/2003) 1.
Table of Contents 1. Introduction _________________________________________________________ 4 1.1 General D escriptio n ___________________________________________________ 4 1.2 Features _____________________________________________________________ 4 1.
2.7.2 A/D Conversion Trigger M odes _______________________________________________ 22 2.7.3 A/D Transfer Modes ________________________________________________________ 23 2.7.4 Using software trigge r and pol ling transfer ______________________________________ 23 2.
1. Introduction 1.1 General Description The OME-A-8111 is a high performance, multif unction (analog and digital I/O) board for the PC AT compatible computer with the ISA bus. The OME-A-8111 provides programmable gain (1, 2, 4, 8 and 16). The OM E-A-8111 contains a 12-bit ADC with up to 8 single-ended analog inputs.
1.3 Specifications 1.3.1 Power Consumption z +5V @ 300 mA maxim um z +12V @ 60 mA maxim um z -12V @ 30 mA maxim um z Operating temperature: 0 ° C ~ 50 ° C 1.3.2 Analog Inputs z Channels: 8 single-ended z Input range: (software programmable) Bipolar: ± 5 V, ± 2.
1.3.4 DA Converter z Channels : 1 independent z Type : 12-bit multiplying , Analog device AD-7948 z Linearity : ± 1/2 bit z Output Range : 0~5 V or 0~10 V jumper selected , may be used with other AC or DC reference input. Maximum output lim it ± 10V z Output Drive : ± 5 mA z Settling Time : 0.
1.3.7 Programmable Timer/Counter z Type : 82C54 -8 programmable tim er/counter z Counters: The counter1 and counter2 are cascaded as a 32-bit pacer timer. z Pacer output : 0.00047 Hz to 0.5 MHz z Input Gate : TTL compatible z Internal Clock : 2 MHz 1.
2. Hardware Configuration 2.1 Board Layout BB ADS- 7 74 ON 123456 JP1 JP2 8111 SW1 987654 () A BASS ADDRESS A1 P1 A31 12 19 20 CN3 D/ C OUT CN2 D/ C I N 20 2 1 19 ANA I/0 CN1 VR1 VR2 VR3 VR4 VR5 OME-A-8111 Hardware Manual (ver.
2.2 I/O Base Address Setting The OME-A-8111 occupies 16 consecutive locations in I/O address space. The base address is set by DIP switch SW1. The default address is 0x220 as shown below: A 9 A 8 A 7 .
The PC I/O port mapping is given below. ADDRESS DEVICE ADDRESS DEVICE 000-1FF PC reserved 320-32F XT Hard Disk 200-20F Game/control 378-37F Parallel Printer 210-21F XT Expansion Unit 380-38F SDLC 238-23F Bus Mouse/Alt.
2.4 I/O Register Address The OME-A-8111 occupies 16 consecutive PC I/O addresses. The following table lists the registers and their locations. Address Read Write Base+0 8254 Counter 0 8254 Counter 0 B.
2.4.1 The 8254 Counter The 8254 Programmable tim er/counter has 4 registers from Base+0 through Base+3. For detailed programming inform ation about the 8254, please refer to Intel‘s “Microsystem Components Handbook”.
2.4.3 D/A Output Latch Register (WRITE) Base+4: Channel 1 D/A Low Byte Data Format Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 D7 D6 D5 D4 D3 D2 D1 D0 (WRITE) Base+5: Channel 1 D/A High Byte Data .
2.4.5 Clear Interrupt Request (WRITE) Base+8: Clear Interrupt Request Format Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 X X X X X X X X X = don‘t care, XXXXXXXX = any 8 bit data is valid If OME-A-8111 is working in the interrupt transfer mode, an on-board hardware status bit will be set after each A/D conversion.
2.4.7 A/D Multiplex Control Register (WRITE) Base+A : A/D Multiplexer Control Register Format Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 X X X X X D2 D1 D0 A/D input channel selection data =3 bits: D2.
2.4.8 A/D Mode Control Register (WRITE) Base+B : A/D Mode Control Register Format Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 X SI2 SI1 SI0 X D2 D1 D0 X=don‘t care Mode Select Trigger Type Trans.
The pacer trigger can control the sampling rate very precisely. So the converted data can be used to reconstruct the waveform of the analog input signal . In pacer trigger mode, the pacer timer will periodically generate trigger signals to the A/D converter.
2.4.10 D/O Output Latch Register (WRITE) Base+D: D/O Output Latch Low Byte Data Format Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 D7 D6 D5 D4 D3 D2 D1 D0 (WRITE) Base+E: D/O Output Latch High Byte Data Format Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 D15 D14 D13 D12 D11 D10 D9 D8 D/O 16 bits output data: D15.
2.5 Digital I/O The OME-A-8111 provides 16 digital input channels and 16 digital output channels. All levels are TTL compatible . The connections diagram and block diagram are given below: Read Read D0...D7 Base+D Base+E D0...D7 D8...D15 1...8 9...16 Output Latch Register Output Latch Register CN3 17.
2.6 8254 Timer/Counter The 8254 Programmable tim er/counter has 4 registers from Base+0 through Base+3. For detailed programming inform ation about 8254, please refer to Intel‘s “Microsystem Components Handbook”.
2.7 A/D Conversion This section explains how to perfor m A/D conversions. The A/D conversion can be performed by software trigger by pacer trigger. At the end of the A/D conversion, it is possible to .
2.7.1 A/D conversion flow Then the user must decide which A/D convers ion m ode will be used. The software driver supports three different modes. The user can control the A/D conversion by polling mode very easily (sec. 2.4.9) . It is recommended to use the softwa re driver if using interrupt or DMA mode.
2.7.3 A/D Transfer Modes OME-A-8111 supports two transfer m odes. 1 : polling transfer : This mode can be used with all trigger mode s. Detailed information is given in section 2.4.8.The software scans A/D high byt e data register, BASE+5, until READY_BIT=0.
2.8 D/A Conversion The OME-A-8111 provides two 12-bit D/ A converters. Before using the D/A conversion function, user should notice the following issues: z D/A output register, BASE+4/BASE+5/BASE+6/BASE+7 (sec. 2.4.3) . z JP1/JP2 selects internal/external reference voltage (sec.
2.9 Analog Input Signal Connection FIG 1: Connecting analog input configuration A/D CHn OME-A-8111 AGND A/D CH0 Es Signal Shielding z Signal shielding connections are shown in Fig1. z Use single-point connection to frame ground (not AGND or DGND) Frame Ground OME-A-8111 AGND DGND Vin OME-A-8111 Hardware Manual (ver.
2.10 Pin Assignment The OME-A-8111 provides three connect ors. Connect 1, CN1 functions for analog input & analog output input. Connector 2, CN2, f unctions as 16 digital outputs. Connector 3, CN3, function as a digital output. CN1/CN2/CN3 Pin Assignment CN1: Analog input/Analog output /Connect Pin Assignment.
CN2: Analog input/Analog output /Connect Pin Assignment. Pin Number Description Pin Number Description 1 Digital Input 0/TTL 2 Digital Input 1/TTL 3 Digital Input 2/TTL 4 Digital Input 3/TTL 5 Digital.
2.11 Daughter Board The OME-A-8111 can be connected with many different daughter boards. The function of these daughter boards is described as follows. 2.11.1 OME-CA-4002 The OME-CA-4002 is a 37-pin D-Sub male connect or. It can directly connect to a 37-pin D-sub connector.
3. Calibration The OME-A-8111 is calibrated to its best stat e of operation. For environments with large vibration, recalibration is recommended. Befo re calibrating the OME-A-8111, users should have the following items: z One 6-digit multi-meter. z One stable voltage source (4.
3.2 D/A Calibration Steps 1. Run A8111CAL.EXE 2. Connect D/A channel0,, pin 30 of CN1 to DVM 3. Adjust VR1 until DVM=5.0000V 4. Press “Enter" key 5. Adjust VR2 until DVM=0.0000V 3.3 A/D Calibration Steps 1. Press “Enter" key 2. Connot A/D Channel 0 to analog ground, CN1-Pin1 to CN1-Pin20.
W ARRANTY / DISCLAIMER OMEGA ENGINEERING, INC. warrants this unit to be free of defects in materials and workmanship for a period of 13 months from date of purchase. O MEGA ’ s W ARRANTY adds an additional one (1) month grace period to the normal one (1) year product warranty to cover handling and shipping time.
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