AtmelメーカーATmega324PAの使用説明書/サービス説明書
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Features • High-perf ormance, Low-po wer A VR ® 8-bit Micr ocontroller • Adv anced RISC Architecture – 131 P owerful Instruction s – Mo st Single-c lock Cyc le Executio n – 32 x 8 General P.
2 8152AS–AVR–11/08 ATmega324PA 1. Pin Configurations 1.1 Pinout - PDIP/TQ FP/VQFN/QFN/MLF Figure 1-1. Pinout Note: The large center pad under neath the VQFN/QFN/MLF package should be soldered to ground on the board to ensure good mechani cal stability .
3 8152AS–AVR–11/08 ATmega324PA 1.2 Pinout - DRQFN Figure 1-2. DRQFN - Pinout T able 1-1. DR QFN - Pinout A1 PB5 A7 PD3 A13 PC4 A19 PA 3 B1 PB6 B6 PD4 B11 PC5 B16 PA 2 A2 PB7 A8 PD5 A14 PC6 A20 PA .
4 8152AS–AVR–11/08 ATmega324PA 1.3 Pinout - VFBGA Figure 1-3. VFBGA - Pinout T able 1-2. BGA - Pinout 1234567 A GND PB4 PB2 GND VCC P A2 GND B PB6 PB5 PB3 PB0 P A0 P A3 P A5 C VCC RESET PB7 PB1 P .
5 8152AS–AVR–11/08 ATmega324PA 2. Overview The ATmega324PA is a low-power CMOS 8- bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instru ctions in a single c.
6 8152AS–AVR–11/08 ATmega324PA The ATmega324PA provides the following featur es: 32K bytes of In-System Programmable Flash with Read-While-Write c apabilities, 1K bytes EEPROM, 2K bytes SRAM, 32 g.
7 8152AS–AVR–11/08 ATmega324PA 2.2 Pin Descriptions 2.2.1 VCC Digital supply voltage. 2.2.2 GND Ground. 2.2.3 P ort A (P A7:P A0) Port A serves as analog inputs to the Analog-to-digital Co nver ter. Port A also serves as an 8-bit bi-direction al I/O port with inte rnal pull-up resistors (sele cted for each bit).
8 8152AS–AVR–11/08 ATmega324PA 2.2.7 RESET Reset input. A low level on this pin for longer than the minimum pulse length will gen erate a reset, even if the clock is not runni ng. The minimum pulse length is given in ”System an d Reset Characteristics” on page 329 .
9 8152AS–AVR–11/08 ATmega324PA 5. Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pa ge (0xFF) Reserved - - - - - - - (0xFE) Reserved - - - - - - - - (0xFD) Reserved .
10 8152AS–AVR–11/08 ATmega324PA (0xC0) UCSR0A RXC0 TXC0 UDRE0 FE0 DOR0 UPE0 U2X0 MPCM0 190/205 (0xBF) Reserved - - - - - - - - (0xBE) Reserved - - - - - - - - (0xBD) TWAMR TWAM6 TWAM5 TWAM4 TWAM3 .
11 8152AS–AVR–11/08 ATmega324PA (0x7E) DIDR0 ADC7D ADC6D ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D 260 (0x7D) Reserved - - - - - - - - (0x7C) ADMUX REFS1 REFS0 ADLAR MU X4 MUX3 MUX2 MUX1 MUX0 256 (0x7B).
12 8152AS–AVR–11/08 ATmega324PA Notes: 1. F or compatibili ty with future devices, reserved bits s hould be written to zero if accessed. Reser ved I/O memory addre ss es should nev er be written. 2. I/O registers within the address range $00 - $1F are directly bit-accessible using th e SBI and CBI instr uctions.
13 8152AS–AVR–11/08 ATmega324PA 6. Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,.
14 8152AS–AVR–11/08 ATmega324PA BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1/2 BRIE k Branch if Interrupt En abled if ( I = 1) then PC ← PC + k + 1 None 1/2.
15 8152AS–AVR–11/08 ATmega324PA SPM Store Program Memory (Z) ← R1:R0 None - IN Rd, P In Port Rd ← PN o n e 1 OUT P, Rr Out Port P ← Rr None 1 PUSH Rr Push Register on Stack STACK ← Rr None 2 POP Rd Pop Register from Stack Rd ← STACK None 2 MCU CONTROL INSTRUCTIONS NOP No Operation None 1 SLEEP Sleep (see specifi c descr.
16 8152AS–AVR–11/08 ATmega324PA 7. Or dering Information 7.1 A Tmega324P A Notes: 1. This device can also be supplied in wafe r f orm. Please contac t your local Atmel sales office for detailed ordering info r mation and minimum quantities.
17 8152AS–AVR–11/08 ATmega324PA 8. P ac kaging Inf ormation 8.1 44A 2325 Orchard P arkwa y San Jose, CA 95131 TITLE DRA WING NO. R REV . 44A, 44-lead, 10 x 10 mm Body Size, 1.
18 8152AS–AVR–11/08 ATmega324PA 8.2 40P6 2325 Orchard P arkwa y San Jose, CA 95131 TITLE DRA WING NO. R REV . 40P6 , 40-lead (0.600"/15.24 mm Wide) Plastic Dual Inline Package (PDIP) B 40P6 09/28/01 PIN 1 E1 A1 B REF E B1 C L SEA TING PLANE A 0º ~ 15º D e eB COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A – – 4.
19 8152AS–AVR–11/08 ATmega324PA 8.3 44M1 TITLE DRA WING NO. GPC REV . Pa ck a g e Drawin g Contact: p a ck a gedr a wing s @ a tmel.com 44M1 ZW S H 44M1, 44-pad, 7 x 7 x 1.
20 8152AS–AVR–11/08 ATmega324PA 8.4 44MC TITLE DRA WING NO . REV . Pa ck a g e Drawin g Contact: p a ck a gedr a wing s @ a tmel.com 44MC A 9/1 3 /07 D2 E2 L L B15 A1 8 B11 A1 3 B10 A12 B6 A7 A6 B5 B1 B20 A1 A24 eT L b R0.20 0.40 eR A19 B16 eT/2 S IDE VIEW A1 A y C D E Pin 1 ID T OP VIEW BO TT OM VIEW Note: 1.
21 8152AS–AVR–11/08 ATmega324PA 8.5 49C2 TITLE DRA WING NO. GPC REV . Pa ck a g e Drawin g Contact: p a ck a gedr a wing s @ a tmel.com 49C2 CBD A 49C2, 49- ba ll (7 x 7 Arr a y), 0.
22 8152AS–AVR–11/08 ATmega324PA 9. Errata 9.1 A Tmega324P A Rev . F No known Errata..
23 8152AS–AVR–11/08 ATmega324PA 10. Datasheet Re vision History Please note that the referring page numbers in this se ction are referred to this documen t. The referring re visio n in th is section are referring to the document revision. 10.1 Re v .
8152AS–AVR–11/0 8 Headquar ters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, .
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Atmel ATmega324PAを既にお持ちだが、まだ読んでいない場合は、上記の理由によりそれを行うべきです。そうすることにより機能を適切に使用しているか、又はAtmel ATmega324PAの不適切な取り扱いによりその寿命を短くする危険を犯していないかどうかを知ることができます。
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