Texas InstrumentsメーカーTMS320C6454の使用説明書/サービス説明書
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www.ti.com PRODUCT PREVIEW 1 TMS320C6454 Fixed-Point Digital Signal Processor 1.1 Features TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 • 32-Bit DDR2 Memory Controller (DDR2-533 • High-Performance Fixed-Point DSP (C6454) SDRAM) – 1.
www.ti.com PRODUCT PREVIEW 1.1.1 ZTZ/GTZ BGA Package (Bottom View) ZTZ/GTZ 697-PIN BALL GRID ARRA Y (BGA) P ACKAGE ( BOTT OM VIEW ) A 2 B 1 3 4 5 6 7 8 9 10 1 1 12 13 14 15 16 17 18 19 20 21 22 23 24 .
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The C64x+ DSP core employs eight functional units, two register files, and two data paths. Like the earlier C6000 devices, two of these eight functional units are multipliers or .
www.ti.com PRODUCT PREVIEW 1.3 Functional Block Diagram L2 Memory Controller (Memory Protect/ Bandwidth Mgmt) DDR2 Mem Ctlr System (B) C64x+ DSP Core Data Path B B Register File B31−B16 B15−B0 Instruction Fetch Data Path A A Register File A31−A16 A15−A0 Device Configuration Logic .
www.ti.com PRODUCT PREVIEW Contents TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 1 TMS320C6454 Fixed-Point Digital Signal 5.5 Megamodule Resets ................................ 81 Processor .......
www.ti.com PRODUCT PREVIEW 2 Device Overview 2.1 Device Characteristics TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-1 , provides an overview of the C6454 DSP.
www.ti.com PRODUCT PREVIEW 2.2 CPU (DSP Core) Description TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-1.
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Other new features include: • SPLOOP - A small instruction buffer in the CPU that aids in creation of software pipelining loops where multiple iterations of a loop are executed in parallel.
www.ti.com PRODUCT PREVIEW src2 src2 .D1 .M1 .S1 .L1 long src odd dst src2 src1 src1 src1 src1 even dst even dst odd dst dst1 dst src2 src2 src2 long src DA1 ST1b LD1b LD1a ST1a Data path A Odd register file A (A1, A3, A5...A31) Odd register file B (B1, B3, B5.
www.ti.com PRODUCT PREVIEW 2.3 Memory Map Summary TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-2 shows the memory map address ranges of the C6454 device.
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-2. C6454 Memory Map Summary (continued) MEMORY BLOCK DESCRIPTION B.
www.ti.com PRODUCT PREVIEW 2.4 Boot Sequence 2.4.1 Boot Modes Supported TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The boot sequence is a proces.
www.ti.com PRODUCT PREVIEW 2.4.2 2nd-Level Bootloaders TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 such as Code Composer Studio. For the PCI host boot, the CPU is out of reset, but it executes an IDLE instruction until a DSP interrupt is generated by the host.
www.ti.com PRODUCT PREVIEW 2.5 Pin Assignments 2.5.1 Pin Map AG AF AE AD AC AB AA Y W V U T R 13 12 1 1 10 9 8 7 6 5 4 3 2 1 13 12 1 1 10 9 8 7 6 5 4 3 2 1 CLKR1/ GP[0] HD15/ AD15 HD2/ AD2 PGNT/ GP[12.
www.ti.com PRODUCT PREVIEW AG AF AE AD AC AB AA Y W V U T R 17 18 19 20 21 22 23 24 25 26 27 28 29 17 18 19 20 21 22 23 24 25 26 27 28 29 SDA AED27 V SS ASADS/ ASRE AED17 AHOLD PLL V1 AEA13/ LENDIAN A.
www.ti.com PRODUCT PREVIEW C D E F G H J K L M N P 17 18 19 20 21 22 23 24 25 26 27 28 29 17 18 19 20 21 22 23 24 25 26 27 28 29 RSV09 AED52 DV DD 33 V SS V SS V SS AECLKIN AEA9/ MACSEL0 CLKIN1 DV DD .
www.ti.com PRODUCT PREVIEW A D E F G H J K L M N P 13 12 1 1 10 9 8 7 6 5 4 3 2 1 13 12 1 1 10 9 8 7 6 5 4 3 2 1 RGRXD2 RGTXD3 DV DD 33 MTXD2 V SS MTXD0/ RMTXD0 CV DD MON MTXD6 V SS PREQ/ GP[15] PINT .
www.ti.com PRODUCT PREVIEW 2.6 Signal Groups Description TRST IEEE Standard 1 149.1 (JT AG) Emulation Reserved Reset and Interrupts Control/Status TDI TDO TMS TCK NMI RESET RSV03 RSV04 Clock/PLL1 and .
www.ti.com PRODUCT PREVIEW A. This pin functions as GP[1] by default. For more details, see the Device Configuration section of this document. B. These McBSP1 peripheral pins are muxed with the GPIO peripheral pins and by default these signals function as GPIO peripheral pins.
www.ti.com PRODUCT PREVIEW ACE4 (A ) AECLKOUT AED[63:0] ACE3 (A ) ACE2 (A ) AEA[19:0] AARDY Data Memory Map Space Select Address Byte Enables 64 20 External Memory I/F Control EMIF A (64-bit Data Bus).
www.ti.com PRODUCT PREVIEW McBSPs (Multichannel Buffered Serial Ports) (B) CLKX0 FSX0 DX0 CLKR0 FSR0 DR0 T ransmit McBSP0 Receive Clock CLKX1/GP[3] FSX1/GP[1 1] DX1/GP[9] CLKR1/GP[0] FSR1/GP[10] DR1/G.
www.ti.com PRODUCT PREVIEW RGTXCTL, RGRXCTL MRXER/RMRXER, MRXDV , MCRS/RMCRSDV , MCOL, MTXEN/RMTXEN Ethernet MAC (EMAC) and MDIO MDIO MDCLK MDIO Clock Clocks Error Detect and Control Input/Output Receive RGMDIO RGMDCLK RGTXD[3:0] A. RGMII signals are mutually exclusive to all other EMAC signals.
www.ti.com PRODUCT PREVIEW HD[15:0]/AD[15:0] HR/W/PCBE2 HDS2/PCBE1 PCBE0 /GP[2] HHWIL/PCLK HINT/PFRAME PINT A/GP[14] Data/Address Arbitration 32 Clock Control PCI Interface (A) HAS/PP AR PRST/GP[13] H.
www.ti.com PRODUCT PREVIEW 2.7 Terminal Functions TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The terminal functions table ( Table 2-3 ) identifi.
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO.
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO. PTRDY P4 I/O/Z PCI target ready ( PRTDY) ( I/O/Z ).
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO.
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO.
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO.
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO.
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO.
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO.
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO.
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO.
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO. This pin is the EMAC collision sense (MCDL) ( I ) for MII [default] or GMII.
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO. Reserved. This pin must be connected to the 1.
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO.
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO. Reserved. This pin must be connected to the 1.
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO. (DV DD15 /2)-V reference for HSTL buffer (EMAC RGMII).
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO. A29 E26 E28 G2 H23 H28 J6 J24 K1 K7 K23 L24 M7 M23 M28 N24 P6 P28 R1 R6 R23 DV DD33 T7 S 3.
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO. AD5 AD7 AD14 AD18 AD22 AD24 AE6 AE8 AE15 AF1 AF16 DV DD33 AF24 S 3.
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO. R18 T11 T13 T15 T17 T19 U12 CV DD S 1.
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO.
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO.
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO.
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO.
www.ti.com PRODUCT PREVIEW 2.8 Development 2.8.1 Development Support 2.8.2 Device Support TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 In case the.
www.ti.com PRODUCT PREVIEW C64x+ t DSP: C6454 PREFIX TMX 320 C6454 ZTZ TMX = Experimental device TMS = Qualified device DEVICE F AMIL Y 320 = TMS320 t DSP family P ACKAGE TYPE (A) ZTZ = 697-pin plastic BGA, with Pb-Free solder balls GTZ = 697-pin plastic BGA, with Pb-ed solder balls DEVICE A.
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 objective of this document is to indicate differences between the two cores. Functionality in the devices that is identical is not included.
www.ti.com PRODUCT PREVIEW 3 Device Configuration 3.1 Device Configuration at Device Reset TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 On the C6454 device, certain device configurations like boot mode, pin multiplexing, and endianess, are selected at device reset.
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 3-1. C6454 Device Configuration Pins (AEA[19:0], ABA[1:0], and PCI_EN) (continued) CONFIGURATION IPD/ NO. FUNCTIONAL DESCRIPTION PIN IPU (1) HPI peripheral bus width select (HPI_WIDTH).
www.ti.com PRODUCT PREVIEW 3.2 Peripheral Configuration at Device Reset TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 3-1. C6454 Device Configuration Pins (AEA[19:0], ABA[1:0], and PCI_EN) (continued) CONFIGURATION IPD/ NO.
www.ti.com PRODUCT PREVIEW 3.3 Peripheral Selection After Device Reset TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 3-2.
www.ti.com PRODUCT PREVIEW Reset Static Powerdown Disabled Enable In Progress Enabled Unlock the PERCFG0 register by using the PERLOCK register . W rite to the PERCFG0 register within 16 SYSCLK3 clock cycles to change the state of the peripherals. Poll the PERST A T registers to verify state change.
www.ti.com PRODUCT PREVIEW 3.4 Device State Control Registers TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The C6454 device has a set of registers that are used to control the status of its peripherals.
www.ti.com PRODUCT PREVIEW 3.4.1 Peripheral Lock Register Description TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 When written with correct 32-bit key (0x0F0A0B00), the Peripheral Lock Register (PERLOCK) allows one write to the PERCFG0 register within 16 SYSCLK3 cycles.
www.ti.com PRODUCT PREVIEW 3.4.2 Peripheral Configuration Register 0 Description TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The Peripheral Configuration Register (PERCFG0) is used to change the state of the peripherals.
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 3-7. Peripheral Configuration Register 0 (PERCFG0) Field Descriptions (continued) Bit Field Value Description 12 I2CCTL Mode control for I2C 0 Set I2C to disabled mode 1 Set I2C to enabled mode 11 Reserved Reserved.
www.ti.com PRODUCT PREVIEW 3.4.3 Peripheral Configuration Register 1 Description TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The Peripheral Configuration Register (PERCFG1) is used to enable the EMIFA and DDR2 Memory Controller.
www.ti.com PRODUCT PREVIEW 3.4.4 Peripheral Status Registers Description TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The Peripheral Status Registers (PERSTAT0 and PERSTAT1) show the status of the C6454 peripherals.
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 3-9. Peripheral Status Register 0 (PERSTAT0) Field Descriptions (con.
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 31 16 Reserved R-0 15 3 2 0 Reserved PCISTAT R-0 R-0 LEGEND: R = Read only; - n = value after reset Figure 3-7. Peripheral Status Register 1 (PERSTAT1) - 0x02AC 0018 Table 3-10.
www.ti.com PRODUCT PREVIEW 3.4.5 EMAC Configuration Register (EMACCFG) Description TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The EMAC Configuration Register (EMACCFG) is used to assert and deassert the reset of the Reduced Media Independent Interface (RMII) logic of the EMAC.
www.ti.com PRODUCT PREVIEW 3.4.6 Emulator Buffer Powerdown Register (EMUBUFPD) Description TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The Emulator Buffer Powerdown Register (EMUBUFPD) is used to control the state of the pin buffers of emulator pins EMU[18:2].
www.ti.com PRODUCT PREVIEW 3.5 Device Status Register Description TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The device status register depicts the device configuration selected upon device reset.
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 3-13. Device Status Register (DEVSTAT) Field Descriptions (continued.
www.ti.com PRODUCT PREVIEW 3.6 JTAG ID (JTAGID) Register Description 3.7 Pullup/Pulldown Resistors TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 3-13.
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 • Other Input Pins : If the IPU/IPD does not match the desired value/state, use an external pullup/pulldown resistor to pull the signal to the opposite rail.
www.ti.com PRODUCT PREVIEW 3.8 Configuration Examples Shading denotes a peripheral module not available for this configuration. McBSP0 TIMER0 EMIF A GPIO PLL2 and PLL2 Controller TIMER1 PLL1 and PLL1 .
www.ti.com PRODUCT PREVIEW Shading denotes a peripheral module not available for this configuration. McBSP0 TIMER0 EMIF A GPIO TIMER1 PLL1 and PLL1 Controller DDR2 EMIF AED[63:0] 64 AECLKIN, AARDY , A.
www.ti.com PRODUCT PREVIEW 4 System Interconnect 4.1 Internal Buses, Bridges, and Switch Fabrics TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 On the C6454 device, the C64x+ Megamodule, the EDMA3 transfer controllers, and the system peripherals are interconnected through two switch fabrics.
www.ti.com PRODUCT PREVIEW 4.2 Data Switch Fabric Connections TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Figure 4-1 shows the connection between slaves and masters through the data switched central resource (SCR).
www.ti.com PRODUCT PREVIEW EMAC HPI M M 128-bit (SYSCLK2) M3 M0 S M M M McBSPs S DDR2 Memory Controller S EMIF A S PCI S MASTER S M Bridge CFG SCR S Bridge PCI M EDMA3 Channel Controller EDMA3 Transfe.
www.ti.com PRODUCT PREVIEW 4.3 Configuration Switch Fabric TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 4-1.
www.ti.com PRODUCT PREVIEW Megamodule M CFG SCR S M McBSPs S T imers S HPI S PCI S S Bridge 7 GPIO S EMAC/MDIO M Data SCR S S I2C S S PLL Controllers (A) S S Device Configuration Registers (A) EDMA3 T.
www.ti.com PRODUCT PREVIEW 4.4 Priority Allocation TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 On the C6454 device, each of the masters (excluding the C64x+ Megamodule) are assigned a priority via the Priority Allocation Register (PRI_ALLOC), see Figure 4-3 .
www.ti.com PRODUCT PREVIEW 5 C64x+ Megamodule A register file Data path 1 Data path 2 B register file D2 S2 xx xx M2 L2 Instruction decode M1 xx xx L1 S1 D1 16/32−bit instruction dispatch Instructio.
www.ti.com PRODUCT PREVIEW 4K bytes 8K bytes 16K bytes L1P memory 00E0 0000h 00E0 4000h 00E0 6000h 00E0 7000h 00E0 8000h direct mapped SRAM 1/2 dm 3/4 SRAM SRAM 7/8 All SRAM 000 001 010 01 1 100 Block.
www.ti.com PRODUCT PREVIEW 32K bytes 32K bytes 64K bytes 128K bytes 792K bytes L2 memory 0080 0000h 008C 0000h 008E 0000h 008F 0000h 008F 8000h 0090 0000h 3/4 SRAM 4-way cache 4-way cache SRAM 7/8 4-w.
www.ti.com PRODUCT PREVIEW 5.2 Memory Protection 5.3 Bandwidth Management TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Memory protection allows an operating system to define who or what is authorized to access L1D, L1P, and L2 memory.
www.ti.com PRODUCT PREVIEW 5.4 Power-Down Control 5.5 Megamodule Resets TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The C64x+ Megamodule supports the ability to power-down various parts of the C64x+ Megamodule.
www.ti.com PRODUCT PREVIEW 5.6 Megamodule Revision TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The version and revision of the C64x+ Megamodule can be read from the Megamodule Revision ID Register (MM_REVID) located at address 0181 2000h.
www.ti.com PRODUCT PREVIEW 5.7 C64x+ Megamodule Register Description(s) TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 5-4.
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 5-4. Megamodule Interrupt Registers (continued) HEX ADDRESS RANGE AC.
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 5-8. Megamodule Cache Configuration Registers HEX ADDRESS RANGE ACRO.
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 5-8. Megamodule Cache Configuration Registers (continued) HEX ADDRES.
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 5-8. Megamodule Cache Configuration Registers (continued) HEX ADDRES.
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 5-9. Megamodule L1/L2 Memory Protection Registers (continued) HEX AD.
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 5-9. Megamodule L1/L2 Memory Protection Registers (continued) HEX AD.
www.ti.com PRODUCT PREVIEW 6 Device Operating Conditions 6.1 Absolute Maximum Ratings Over Operating Case Temperature Range (Unless Otherwise 6.2 Recommended Operating Conditions TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Noted) (1) Supply voltage range: CV DD (2) -0.
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Recommended Operating Conditions (continued) MIN NOM MAX UNIT 3.3 V pins (except PCI-capable and 0.8 V I2C pins) PCI-capable pins -0.
www.ti.com PRODUCT PREVIEW 6.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Case Temperature (Unless Otherwise Noted) PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT 3.
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Electrical Characteristics Over Recommended Ranges of Supply Voltage and O.
www.ti.com PRODUCT PREVIEW 7 C64x+ Peripheral Information and Electrical Specifications 7.1 Parameter Information T ransmission Line 4.0 pF 1.85 pF Z0 = 50 Ω (see Note) T ester Pin Electronics Data Sheet T iming Reference Point Output Under T est NOTE: The data sheet provides timing at the device pin.
www.ti.com PRODUCT PREVIEW 7.1.3 Timing Parameters and Board Routing Analysis 1 2 3 4 5 6 7 8 10 1 1 AECLKOUT (Output from DSP) AECLKOUT (Input to External Device) Control Signals (A) (Output from DSP.
www.ti.com PRODUCT PREVIEW 7.2 Recommended Clock and Control Signal Transition Behavior 7.3 Power Supplies 7.3.1 Power-Supply Sequencing DV DD33 CV DD12 All other power supplies 1 2 7.
www.ti.com PRODUCT PREVIEW 7.3.4 Preserving Boundary-Scan Functionality on RGMII and DDR2 Memory Pins TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Peripherals used for booting, like I2C and HPI, are automatically enabled after device reset.
www.ti.com PRODUCT PREVIEW 7.4 Enhanced Direct Memory Access (EDMA3) Controller 7.4.1 EDMA3 Device-Specific Information TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REV.
www.ti.com PRODUCT PREVIEW 7.4.2 EDMA3 Channel Synchronization Events TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The EDMA3 supports up to 64 DMA channels that can be used to service system peripherals and to move data between system memories.
www.ti.com PRODUCT PREVIEW 7.4.3 EDMA3 Peripheral Register Description(s) TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-3.
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-4. EDMA3 Channel Controller Registers (continued) HEX ADDRESS RANG.
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-4. EDMA3 Channel Controller Registers (continued) HEX ADDRESS RANG.
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-4. EDMA3 Channel Controller Registers (continued) HEX ADDRESS RANG.
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-4. EDMA3 Channel Controller Registers (continued) HEX ADDRESS RANG.
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-4. EDMA3 Channel Controller Registers (continued) HEX ADDRESS RANG.
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-5. EDMA3 Parameter RAM (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME ... ... 02A0 47E0 - 02A0 47FF - Parameter Set 63 02A0 4800 - 02A0 481F - Parameter Set 64 02A0 4820 - 02A0 483F - Parameter Set 65 .
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-6. EDMA3 Transfer Controller 0 Registers (continued) HEX ADDRESS R.
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-7. EDMA3 Transfer Controller 1 Registers (continued) HEX ADDRESS R.
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-8. EDMA3 Transfer Controller 2 Registers (continued) HEX ADDRESS R.
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-9. EDMA3 Transfer Controller 3 Registers HEX ADDRESS RANGE ACRONYM.
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-9. EDMA3 Transfer Controller 3 Registers (continued) HEX ADDRESS R.
www.ti.com PRODUCT PREVIEW 7.5 Interrupts 7.5.1 Interrupt Sources and Interrupt Controller TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The CPU interrupts on the C6454 device are configured through the C64x+ Megamodule Interrupt Controller.
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-10. C6454 DSP Interrupts (continued) EVENT NUMBER INTERRUPT EVENT .
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-10. C6454 DSP Interrupts (continued) EVENT NUMBER INTERRUPT EVENT .
www.ti.com PRODUCT PREVIEW 7.5.2 External Interrupts Electrical Data/Timing 2 1 NMI TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-11. Timing Requirements for External Interrupts (1) (see Figure 7-6 ) -720 -850 NO.
www.ti.com PRODUCT PREVIEW 7.6 Reset Controller 7.6.1 Power-on Reset ( POR Pin) TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The reset controller detects the different type of resets supported on the C6454 device and manages the distribution of those resets throughout the device.
www.ti.com PRODUCT PREVIEW 7.6.2 Warm Reset ( RESET Pin) TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 all the system clocks are invalid at this point. • The RESETSTAT pin stays asserted (low), indicating the device is in reset.
www.ti.com PRODUCT PREVIEW 7.6.3 System Reset 7.6.4 CPU Reset TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 4. The device is now out of reset, device execution begins as dictated by the selected boot mode (see Section 2.
www.ti.com PRODUCT PREVIEW 7.6.5 Reset Priority 7.6.6 Reset Controller Register TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 If any of the above reset sources occur simultaneously, the PLLCTRL only processes the highest priority reset request.
www.ti.com PRODUCT PREVIEW 7.6.7 Reset Electrical Data/Timing TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 NOTE If a configuration pin must be rou.
www.ti.com PRODUCT PREVIEW CLKIN1 PCLK RESET RESETST A T SYSREFCLK (PLL1C) Z Group POR SYSCLK3 SYSCLK4 SYSCLK5 AECLKOUT (Internal) Boot and Device Configuration Pins Low Group High Group CLKIN2 Intern.
www.ti.com PRODUCT PREVIEW CLKIN1 CLKIN2 POR RESET (A)(B) RESETST A T Boot and Device Configuration Pins (C) 9 7 6 8 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 A. RESET should only be used after device has been powered up.
www.ti.com PRODUCT PREVIEW 7.7 PLL1 and PLL1 Controller TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The primary PLL controller generates the inpu.
www.ti.com PRODUCT PREVIEW 1 0 0 1 DIVIDER D4 CLKIN1 (B) PLLEN (PLLCTL.[0]) SYSCLK2 SYSCLK3 AECLKIN (External EMIF Clock Input) EMIF A DIVIDER PREDIV DIVIDER D2 (A) DIVIDER D3 (A) AECLKOUT PLL V1 C2 C1 EMI Filter +1.
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 • SYSCLK4 is used as the internal clock for the EMIFA. It is also used to clock other logic within the DSP. • SYSCLK5 clocks the emulation and trace logic of the DSP.
www.ti.com PRODUCT PREVIEW 7.7.2 PLL1 Controller Memory Map TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The PLL lock time is the amount of time needed from when the PLL is taken out of reset (PLLRST = 1 with PLLEN = 0) to when to when the PLL controller can be switched to PLL mode (PLLEN = 1).
www.ti.com PRODUCT PREVIEW 7.7.3 PLL1 Controller Register Descriptions TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 This section provides a description of the PLL1 controller registers.
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.7.3.2 PLL Multiplier Control Register The PLL multiplier control register (PLLM) is shown in Figure 7-12 and described in Table 7-20 .
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.7.3.3 PLL Pre-Divider Control Register The PLL pre-divider control register (PREDIV) is shown in Figure 7-13 and described in Table 7-21 .
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.7.3.4 PLL Controller Divider 4 Register The PLL controller divider 4 register (PLLDIV4) is shown in Figure 7-14 and described in Table 7-22 .
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.7.3.5 PLL Controller Divider 5 Register The PLL controller divider 5 register (PLLDIV5) is shown in Figure 7-15 and described in Table 7-23 .
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.7.3.6 PLL Controller Command Register The PLL controller command register (PLLCMD) contains the command bit for GO operation.
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.7.3.7 PLL Controller Status Register The PLL controller status register (PLLSTAT) shows the PLL controller status. PLLSTAT is shown in Figure 7-17 and described in Table 7-25 .
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.7.3.8 PLL Controller Clock Align Control Register The PLL controller clock align control register (ALNCTL) is shown in Figure 7-18 and described in Table 7-26 .
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.7.3.9 PLLDIV Ratio Change Status Register Whenever a different ratio is written to the PLLDIV n registers, the PLLCTRL flags the change in the PLLDIV ratio change status registers (DCHANGE).
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.7.3.10 SYSCLK Status Register The SYSCLK status register (SYSTAT) shows the status of the system clocks (SYSCLK n ). SYSTAT is shown in Figure 7-20 and described in Table 7-28 .
www.ti.com PRODUCT PREVIEW 7.7.4 PLL1 Controller Input and Output Clock Electrical Data/Timing CLKIN1 2 3 4 4 5 1 SYSCLK4 3 4 4 2 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-29. Timing Requirements for CLKIN1 Devices (1) (2) (3) (see Figure 7-21 ) -720 -850 -1000 NO.
www.ti.com PRODUCT PREVIEW 7.8 PLL2 and PLL2 Controller PLL V2 PLL2 SYSCLK2 (From PLL1 Controller) SYSCLK1 DDR2 Memory Controller EMAC CLKIN2 (B)(C) C162 560 pF EMI Filter +1.
www.ti.com PRODUCT PREVIEW 7.8.1 PLL2 Controller Device-Specific Information TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.
www.ti.com PRODUCT PREVIEW 7.8.2 PLL2 Controller Memory Map 7.8.3 PLL2 Controller Register Descriptions TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The memory map of the PLL2 controller is shown in Table 7-32 .
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.8.3.1 PLL Controller Divider 1 Register The PLL controller divider 1 register (PLLDIV1) is shown in Figure 7-24 and described in Table 7-33 .
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.8.3.2 PLL Controller Command Register The PLL controller command register (PLLCMD) contains the command bit for GO operation.
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.8.3.3 PLL Controller Status Register The PLL controller status register (PLLSTAT) shows the PLL controller status. PLLSTAT is shown in Figure 7-26 and described in Table 7-35 .
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.8.3.5 PLLDIV Ratio Change Status Register Whenever a different ratio is written to the PLLDIV1 register, the PLLCTRL flags the change in the DCHANGE status register.
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.8.3.6 SYSCLK Status Register The SYSCLK status register (SYSTAT) shows the status of the system clock (SYSCLK1). SYSTAT is shown in Figure 7-29 and described in Table 7-38 .
www.ti.com PRODUCT PREVIEW 7.8.4 PLL2 Controller Input Clock Electrical Data/Timing CLKIN2 2 3 4 4 5 1 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-39. Timing Requirements for CLKIN2 (1) (2) (3) (see Figure 7-30 ) -720 -850 NO.
www.ti.com PRODUCT PREVIEW 7.9 DDR2 Memory Controller 7.9.1 DDR2 Memory Controller Device-Specific Information TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The 32-bit DDR2 Memory Controller bus of the C6454 is used to interface to JESD79D-2A standard-compliant DDR2 SDRAM devices.
www.ti.com PRODUCT PREVIEW 7.9.2 DDR2 Memory Controller Peripheral Register Description(s) 7.9.3 DDR2 Memory Controller Electrical Data/Timing TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-40.
www.ti.com PRODUCT PREVIEW 7.10 External Memory Interface A (EMIFA) 7.10.1 EMIFA Device-Specific Information TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMB.
www.ti.com PRODUCT PREVIEW 7.10.2 EMIFA Peripheral Register Description(s) TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-41.
www.ti.com PRODUCT PREVIEW 7.10.3 EMIFA Electrical Data/Timing AECLKIN 2 3 4 4 5 1 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-42. Timing Requirements for AECLKIN for EMIFA (1) (2) (see Figure 7-31 ) -720 -850 NO.
www.ti.com PRODUCT PREVIEW 4 5 1 2 AECLKIN AECLKOUT1 3 3 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-43. Switching Characteristics Over Recommended Operating Conditions for AECLKOUT for the EMIFA Module (1) (2) (3) (see Figure 7-32 ) -720 -850 NO.
www.ti.com PRODUCT PREVIEW AECLKOUT ACEx ABE[7:0] AEA[19:0]/ ABA[1:0] AED[63:0] AAOE/ASOE ( A) AR/W AA WE/ASWE ( A) AARDY (B ) Byte Enables Address Read Data Hold = 1 2 Strobe = 4 Setup = 1 2 2 4 10 10 1 1 1 3 A AAOE/ASOE and AAWE /ASWE operate as AAOE (identified under select signals) and AA WE , respectively , during asynchronous memory accesses.
www.ti.com PRODUCT PREVIEW AECLKOUT ACEx ABE[7:0] AEA[19:0]/ ABA[1:0] AED[63:0] AAOE/ASOE (A ) AR/W AA WE/ASWE ( A) AARDY (B ) Byte Enables Address W rite Data Hold = 1 12 Strobe = 4 Setup = 1 12 12 1.
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.10.3.2 Programmable Synchronous Interface Timing Table 7-46. Timing Requirements for Programmable Synchronous Interface Cycles for EMIFA Module (see Figure 7-36 ) -720 -850 NO.
www.ti.com PRODUCT PREVIEW AECLKOUT ACEx ABE[7:0] AEA[19:0]/ABA[1:0] AED[63:0] ASADS/ASRE (B) AAOE/ASOE (B ) AA WE/ASWE ( B) BE1 BE2 BE3 BE4 Q1 Q2 Q3 9 1 4 5 8 9 6 7 3 1 2 BE1 BE2 BE3 BE4 EA1 EA2 EA4 .
www.ti.com PRODUCT PREVIEW AECLKOUT ACEx ABE[7:0] AEA[19:0]/ABA[1:0] AED[63:0] ASADS/ASRE (B) AAOE/ASOE (B) AA WE /ASWE (B) BE1 BE2 BE3 BE4 Q1 Q2 Q3 1 1 3 12 10 4 2 1 8 5 8 EA1 EA2 EA3 EA4 10 W rite L.
www.ti.com PRODUCT PREVIEW 7.10.4 HOLD/ HOLDA Timing HOLD HOLDA EMIF Bus (A) DSP Owns Bus External Requestor Owns Bus DSP Owns Bus DSP DSP 1 3 2 5 4 AECLKOUT TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-48.
www.ti.com PRODUCT PREVIEW 7.10.5 BUSREQ Timing AECLKOUTx 1 ABUSREQ 1 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-50. Switching Characteristics Over Recommended Operating Conditions for the BUSREQ Cycles for EMIFA Module (see Figure 7-40 ) -720 -850 NO.
www.ti.com PRODUCT PREVIEW 7.11 I2C Peripheral 7.11.1 I2C Device-Specific Information TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The inter-integ.
www.ti.com PRODUCT PREVIEW Clock Prescale I2CPSC Peripheral Clock (CPU/6) I2CCLKH Generator Bit Clock I2CCLKL Noise Filter SCL I2CXSR I2CDXR T ransmit T ransmit Shift T ransmit Buffer I2CDRR Shift I2C.
www.ti.com PRODUCT PREVIEW 7.11.2 I2C Peripheral Register Description(s) TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-51.
www.ti.com PRODUCT PREVIEW 7.11.3 I2C Electrical Data/Timing TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.11.3.1 Inter-Integrated Circuits (I2C) Timing Table 7-52. Timing Requirements for I2C Timings (1) (see Figure 7-42 ) -720 -850 -1000 NO.
www.ti.com PRODUCT PREVIEW 10 8 4 3 7 12 5 6 14 2 3 13 Stop Start Repeated Start Stop SDA SCL 1 1 1 9 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Figure 7-42. I2C Receive Timings Table 7-53. Switching Characteristics for I2C Timings (1) (see Figure 7-43 ) -720 -850 -1000 NO.
www.ti.com PRODUCT PREVIEW 25 23 19 18 22 27 20 21 17 18 28 Stop Start Repeated Start Stop SDA SCL 16 26 24 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Figure 7-43.
www.ti.com PRODUCT PREVIEW 7.12 Host-Port Interface (HPI) Peripheral 7.12.1 HPI Device-Specific Information 7.12.2 HPI Peripheral Register Description(s) TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The C6454 device includes a user-configurable 16-bit or 32-bit Host-port interface (HPI16/HPI32).
www.ti.com PRODUCT PREVIEW 7.12.3 HPI Electrical Data/Timing TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-55. Timing Requirements for Host-Port Interface Cycles (1) (2) (see Table 7-56 through Figure 7-51 ) -720 -850 NO.
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-56. Switching Characteristics for Host-Port Interface Cycles (1) (2) (see Table 7-56 through Figure 7-51 ) -720 -850 NO.
www.ti.com PRODUCT PREVIEW HCS HAS HCNTL[1:0] HR/W HHWIL HSTROBE (A ) HD[15:0] HRDY (B) 16 15 37 13 14 16 15 37 13 3 1 2 3 1 2 38 7 4 6 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT( HDS1 XOR HDS2)] OR HCS.
www.ti.com PRODUCT PREVIEW HCS HAS HR/W HHWIL HSTROBE (A ) HD[15:0] HRDY (B) 2 3 1 37 9 10 14 2 38 12 1 1 12 1 1 12 1 1 13 7 6 1 3 13 37 9 10 36 HCNTL[1:0] 12 1 1 12 1 1 12 1 1 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 A.
www.ti.com PRODUCT PREVIEW HCS HAS HCNTL[1:0] HR/W HHWIL HSTROBE (A ) HD[15:0] HRDY (B) 34 5 17 18 17 18 34 5 4 38 37 13 16 15 14 13 16 15 37 35 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT( HDS1 XOR HDS2)] OR HCS.
www.ti.com PRODUCT PREVIEW HCS HAS HCNTL[1:0] HR/W HHWIL HSTROBE (A ) HD[15:0] HRDY (B) 5 34 17 18 13 10 12 9 37 12 12 1 1 1 1 1 1 17 18 14 1 1 1 1 1 1 37 10 9 13 12 12 12 5 34 38 35 36 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 A.
www.ti.com PRODUCT PREVIEW 15 16 3 2 4 1 38 13 7 6 HCS (input) HAS (input) HSTROBE (A ) (input) HR/W (input) HRDY (B) (output) HD[31:0] (output) HCNTL[1:0] (input) 37 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 A.
www.ti.com PRODUCT PREVIEW 36 1 1 10 12 9 1 38 13 2 3 6 HCS (input) HAS (input) HSTROBE (A ) (input) HR/W (input) HRDY (B) (output) HD[31:0] (output) HCNTL[1:0] (input) 7 37 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 A.
www.ti.com PRODUCT PREVIEW 17 15 38 5 16 13 18 34 35 4 HCS (input) HAS (input) HSTROBE (A ) (input) HR/W (input) HRDY (B) (output) HD[31:0] (input) HCNTL[1:0] (input) 37 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 A.
www.ti.com PRODUCT PREVIEW HRDY (B) (output) 5 1 1 9 17 18 34 HAS (input) HR/W (input) HSTROBE (A ) (input) HCS (input) 35 36 38 HD[31:0] (input) HCNTL[1:0] (input) 10 12 13 37 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 A.
www.ti.com PRODUCT PREVIEW 7.13 Multichannel Buffered Serial Port (McBSP) TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The McBSP provides these fu.
www.ti.com PRODUCT PREVIEW 7.13.1 McBSP Device-Specific Information TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The CLKS signal is shared by both McBSP0 and McBSP1 on this device. Also, the CLKGDV field of the Sample Rate Generator Register (SRGR) must always be set to a value of 1 or greater.
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-58. McBSP 1 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME COMM.
www.ti.com PRODUCT PREVIEW 7.13.2 McBSP Electrical Data/Timing TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.13.2.1 Multichannel Buffered Serial Port (McBSP) Timing Table 7-59. Timing Requirements for McBSP (1) (see Figure 7-52 ) -720 -850 NO.
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-60. Switching Characteristics Over Recommended Operating Conditions for McBSP (see Figure 7-52 ) (continued) -720 -850 NO.
www.ti.com PRODUCT PREVIEW Bit(n-1) (n-2) (n-3) Bit 0 Bit(n-1) (n-2) (n-3) 14 12 1 1 10 9 3 3 2 8 7 6 5 4 4 3 1 3 2 CLKS CLKR FSR (int) FSR (ext) DR CLKX FSX (int) FSX (ext) FSX (XDA TDL Y=00b) DX 13 .
www.ti.com PRODUCT PREVIEW Bit 0 Bit(n-1) (n-2) (n-3) (n-4) Bit 0 Bit(n-1) (n-2) (n-3) (n-4) 5 4 3 8 7 6 2 1 CLKX FSX DX DR TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-62.
www.ti.com PRODUCT PREVIEW Bit 0 Bit(n-1) (n-2) (n-3) (n-4) Bit 0 Bit(n-1) (n-2) (n-3) (n-4) 4 3 7 6 2 1 CLKX FSX DX DR 5 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-64.
www.ti.com PRODUCT PREVIEW Bit 0 Bit(n-1) (n-2) (n-3) (n-4) Bit 0 Bit(n-1) (n-2) (n-3) (n-4) 5 4 3 8 7 6 2 1 CLKX FSX DX DR TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-66.
www.ti.com PRODUCT PREVIEW Bit 0 Bit(n-1) (n-2) (n-3) (n-4) Bit 0 Bit(n-1) (n-2) (n-3) (n-4) 5 4 3 7 6 2 1 CLKX FSX DX DR TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-68.
www.ti.com PRODUCT PREVIEW 7.14 Ethernet MAC (EMAC) Configuration Bus DMA Memory T ransfer Controller Peripheral Bus EMAC Control Module EMAC Module MDIO Module MDIO Bus EMAC/MDIO Interrupt Interrupt .
www.ti.com PRODUCT PREVIEW 7.14.1 EMAC Device-Specific Information TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Interface Modes The EMAC module on.
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-70. EMAC/MDIO Multiplexed Pins (MII, RMII, and GMII Modes) BALL NU.
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Interface Mode Clocking The on-chip PLL2 and PLL2 Controller generate all the clocks to the EMAC module. When enabled, the input clock to the PLL2 Controller (CLKIN2) must have a 25 MHz frequency.
www.ti.com PRODUCT PREVIEW 7.14.2 EMAC Peripheral Register Description(s) TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-71.
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-71. Ethernet MAC (EMAC) Control Registers (continued) HEX ADDRESS .
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-71. Ethernet MAC (EMAC) Control Registers (continued) HEX ADDRESS .
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-72. EMAC Statistics Registers (continued) HEX ADDRESS RANGE ACRONY.
www.ti.com PRODUCT PREVIEW 7.14.3 EMAC Electrical Data/Timing MRCLK (Input) 2 3 1 4 4 MTCLK (Input) 2 3 1 4 4 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.14.3.1 EMAC MII and GMII Electrical Data/Timing Table 7-75.
www.ti.com PRODUCT PREVIEW GMTCLK (Output) 2 3 1 4 4 MRCLK (Input) 1 2 MRXD7−MRXD4(GMII only), MRXD3−MRXD0, MRXDV , MRXER (Inputs) TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-77.
www.ti.com PRODUCT PREVIEW 1 MTCLK (Input) MTXD7−MTXD4(GMII only), MTXD3−MTXD0, MTXEN (Outputs) 1 GMTCLK (Output) MTXD7−MTXD0, MTXEN (Outputs) TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-79.
www.ti.com PRODUCT PREVIEW RMREFCLK (Input) 1 2 3 3 1 RMREFCLK (Input) MTXD1-MTXD0, MTXEN (Outputs) TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.14.3.2 EMAC RMII Electrical Data/Timing The RMREFCLK pin is used to source a clock to the EMAC when it is configured for RMII operation.
www.ti.com PRODUCT PREVIEW RMREFCLK (Input) 1 2 3 3 4 5 MRXD1-MRXD0, MCRSDV , MRXER (Inputs) TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-83. Timing Requirements for EMAC RMII Input Receive for 100 Mbps (1) (see Figure 7-67 ) -720 -850 NO.
www.ti.com PRODUCT PREVIEW RGREFCLK (Output) 2 3 4 4 1 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.14.3.3 EMAC RGMII Electrical Data/Timing An extra clock signal, RGREFCLK, running at 125 MHz is included as a convenience to the user.
www.ti.com PRODUCT PREVIEW RXD[3:0] (A) RXCTL (A) RXC (at DSP) (B) 5 RXERR RXDV 6 1st Half-byte 2nd Half-byte RXD[7:4] RXD[3:0] 2 3 1 4 4 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-86.
www.ti.com PRODUCT PREVIEW TXC (at DSP) (B) TXD[3:0] (A) TXCTL (A) 5 6 1st Half-byte TXERR TXEN 2nd Half-byte 1 2 Internal TXC TXC at DSP pins 4 4 2 3 1 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-88.
www.ti.com PRODUCT PREVIEW 7.14.4 Management Data Input/Output (MDIO) TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The Management Data Input/Output (MDIO) module implements the 802.
www.ti.com PRODUCT PREVIEW 1 3 4 MDCLK MDIO (input) 1 7 MDCLK MDIO (output) TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.14.4.3 MDIO Electrical Data/Timing Table 7-90. Timing Requirements for MDIO Input (R)(G)MII (see Figure 7-71 ) -720 -850 NO.
www.ti.com PRODUCT PREVIEW 7.15 Timers 7.15.1 Timers Device-Specific Information 7.15.2 Timers Peripheral Register Description(s) TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 20.
www.ti.com PRODUCT PREVIEW 7.15.3 Timers Electrical Data/Timing TINPLx T OUTLx 4 3 2 1 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-94. Timing Requirements for Timer Inputs (1) (see Figure 7-73 ) -720 -850 NO.
www.ti.com PRODUCT PREVIEW 7.16 Peripheral Component Interconnect (PCI) 7.16.1 PCI Device-Specific Information TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The C6454 DSP supports connections to a PCI backplane via the integrated PCI master/slave bus interface.
www.ti.com PRODUCT PREVIEW 7.16.2 PCI Peripheral Register Description(s) TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-97.
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-98. PCI Back End Configuration Registers DSP ACCESS ACRONYM DSP AC.
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-98. PCI Back End Configuration Registers (continued) DSP ACCESS AC.
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-100. PCI Hook Configuration Registers DSP ACCESS ACRONYM DSP ACCES.
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-101. PCI External Memory Space (continued) HEX ADDRESS OFFSET ACRO.
www.ti.com PRODUCT PREVIEW 7.16.3 PCI Electrical Data/Timing TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Texas Instruments (TI) has performed the.
www.ti.com PRODUCT PREVIEW 7.17 General-Purpose Input/Output (GPIO) 7.17.1 GPIO Device-Specific Information 7.17.2 GPIO Peripheral Register Description(s) TMS320C6454 Fixed-Point Digital Signal Proces.
www.ti.com PRODUCT PREVIEW 7.17.3 GPIO Electrical Data/Timing GPIx GPOx 4 3 2 1 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-103. Timing Requirements for GPIO Inputs (1) (2) (see Figure 7-74 ) -720 -850 NO.
www.ti.com PRODUCT PREVIEW 7.18 IEEE 1149.1 JTAG 7.18.1 JTAG Device-Specific Information 7.18.2 JTAG Peripheral Register Description(s) 7.18.3 JTAG Electrical Data/Timing TCK TDO TDI/TMS/TRST 1 2 3 4 2 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.
www.ti.com PRODUCT PREVIEW 8 Mechanical Data 8.1 Thermal Data 8.2 Packaging Information TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 8-1 shows the thermal resistance characteristics for the PBGA - ZTZ/GTZ mechanical package.
www.ti.com PRODUCT PREVIEW Revision History TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 This data sheet revision history highlights the technical changes made to the SPRS311 device-specific data sheet to make it an SPRS311A revision.
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 C6454 Revision History (continued) SEE ADDITIONS/MODIFICATIONS/DELETIONS Section 3.
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 C6454 Revision History (continued) SEE ADDITIONS/MODIFICATIONS/DELETIONS Section 7.
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 C6454 Revision History (continued) SEE ADDITIONS/MODIFICATIONS/DELETIONS Section 7.
PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) TMS320C6454BZTZ ACTIVE FCBGA ZTZ 697 44 Pb-Free (RoHS Ex.
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IMPORT ANT NOTICE T exas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.
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