Texas InstrumentsメーカーTMS320C6455の使用説明書/サービス説明書
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TMS320C6455/C6454 DSP DDR2 Memory Controller User ' s Guide Literature Number: SPRU970G December 2005 – Revised June 2011.
2 SPRU970G – December 2005 – Revised June 2011 Submit Documentation Feedback Copyright © 2005 – 2011, Texas Instruments Incorporated.
Contents Preface ....................................................................................................................................... 7 1 Introduction .................................................................................
www.ti.com List of Figures 1 Device Block Diagram .................................................................................................... 10 2 DDR2 Memory Controller Signals ................................................................
www.ti.com List of Tables 1 DDR2 Memory Controller Signal Descriptions ......................................................................... 12 2 DDR2 SDRAM Commands .................................................................................
6 List of Tables SPRU970G – December 2005 – Revised June 2011 Submit Documentation Feedback Copyright © 2005 – 2011, Texas Instruments Incorporated.
Preface SPRU970G – December 2005 – Revised June 2011 Read This First About This Manual This document describes the DDR2 memory controller in the TMS320C6455/C6454 digital signal processors (DSPs). Notational Conventions This document uses the following conventions.
8 Read This First SPRU970G – December 2005 – Revised June 2011 Submit Documentation Feedback Copyright © 2005 – 2011, Texas Instruments Incorporated.
User ' s Guide SPRU970G – December 2005 – Revised June 2011 C6455/C6454 DDR2 Memory Controller 1 Introduction 1.1 Purpose of the Peripheral The DDR2 memory controller is used to interface with JESD79-2B standard compliant DDR2 SDRAM devices. Memory types such as DDR1 SDRAM, SDR SDRAM, SBSRAM, and asynchronous memories are not supported.
L1 S1 M1 D1 Data path A Register file A Register file B D2 Data path B S2 M2 L2 L1 data memory controller Cache control Memory protection Interrupt and exception controller Power control Instruction d.
www.ti.com Peripheral Architecture 2 Peripheral Architecture The DDR2 memory controller can gluelessly interface to most standard DDR2 SDRAM devices and supports such features as self-refresh mode and prioritized refresh.
DED[31:0] DDR2 Memory Controller DDR2CLKOUT DDR2CLKOUT DCE0 DSDCKE DSDRAS DSDWE DSDDQM[3:0] DSDCAS DBA[2:0] DSDDQS[3:0] DEA[13:0] V REFSSTL DSDDQGA TE[3:0] DSDDQS[3:0] DEODT[1:0] DDRSLRA TE Peripheral Architecture www.ti.com Figure 2. DDR2 Memory Controller Signals Table 1.
www.ti.com Peripheral Architecture 2.4 Protocol Description(s) The DDR2 memory controller supports the DDR2 SDRAM commands listed in Table 2 . Table 3 shows the signal truth table for the DDR2 SDRAM commands. Table 2. DDR2 SDRAM Commands Command Function ACTV Activates the selected bank and row.
COL MRS/EMRS BANK DDR2CLKOUT DDR2CLKOUT DCE0 DSDCKE DSDRAS DSDWE DSDCAS DBA[2:0] DEA[13:0] Peripheral Architecture www.ti.com 2.4.1 Mode Register Set (MRS and EMRS) DDR2 SDRAM contains mode and extended mode registers that configure the DDR2 memory for operation.
REFR DDR2CLKOUT DDR2CLKOUT DCE0 DSDCKE DSDRAS DSDWE DSDDQM[3:0] DSDCAS DBA[2:0] DEA[13:0] www.ti.com Peripheral Architecture 2.4.2 Refresh Mode The DDR2 memory controller issues refresh commands to the DDR2 SDRAM device ( Figure 4 ). REFR is automatically preceded by a DCAB command, ensuring the deactivation of all CE spaces and banks selected.
ACTV BANK ROW DDR2CLKOUT DDR2CLKOUT DCE0 DSDCKE DSDRAS DSDWE DSDDQM[3:0] DSDCAS DBA[2:0] DEA[13:0] Peripheral Architecture www.ti.com 2.4.3 Activation (ACTV) The DDR2 memory controller automatically issues the activate (ACTV) command before a read or write to a closed row of memory.
DCAB DDR2CLKOUT DDR2CLKOUT DCE0 DSDCKE DSDRAS DSDWE DSDDQM[3:0] DSDCAS DBA[2:0] DEA[13:1 1,9:0] DEA[10] www.ti.com Peripheral Architecture 2.4.4 Deactivation (DCAB and DEAC) The precharge all banks command (DCAB) is performed after a reset to the DDR2 memory controller or following the initialization sequence.
DEAC DDR2CLKOUT DDR2CLKOUT DCE0 DSDCKE DSDRAS DSDWE DSDDQM[3:0] DSDCAS DBA[2:0] DEA[13:1 1,9:0] DEA[10] Peripheral Architecture www.ti.com The DEAC command closes a single bank of memory specified by the bank select signals. Figure 7 shows the timings diagram for a DEAC command.
DED[31:0] DSDDQS[3:0] COL BANK DEA[10] CASLatency D0 D1 D2 D3 D4 D5 D6 D7 DDR2CLKOUT DDR2CLKOUT DCE0 DSDCKE DSDRAS DSDWE DSDDQM[3:0] DSDCAS DBA[2:0] DEA[13:0] www.ti.com Peripheral Architecture 2.4.5 READ Command Figure 8 shows the DDR2 memory controller performing a read burst from DDR2 SDRAM.
DED[31:0] DSDDQS[3:0] COL BANK DQM7 Sample D0 D1 D2 D3 D4 D5 D6 D7 DQM1 DQM2 DQM3 DQM4 DQM5 DQM6 DQM8 WriteLatency DEA[10] DDR2CLKOUT DDR2CLKOUT DCE0 DSDCKE DSDRAS DSDWE DSDDQM[3:0] DSDCAS DBA[2:0] DEA[13:0] Peripheral Architecture www.
DDR2 memory controller data bus DED[31:24] (Byte Lane 3) DED[23:16] (Byte Lane 2) DED[15:8] (Byte Lane 1) DED[7:0] (Byte Lane 0) 32-bit memory device 16-bit memory device www.ti.com Peripheral Architecture Figure 10 shows the byte lanes used on the DDR2 memory controller.
Peripheral Architecture www.ti.com Figure 11 and Figure 12 show how the logical address bits map to the row, column, bank, and chip select bits all combinations of IBANK and PAGESIZE values.
Col. 0 Col. 1 Col. 2 Col. 3 Col. 4 Col. M−1 Col. M Row 0, bank 0 Row 0, bank 1 Row 0, bank 2 Row 0, bank P Row 1, bank 1 Row 1, bank 0 Row 1, bank 2 Row 1, bank P Row N, bank 2 Row N, bank 1 Row N, bank 0 Row N, bank P www.
0 1 2 3 M Bank 0 Row 0 Row 1 Row 2 Row N C o l l C o l C o l C o Row 0 Row N Row 1 Row 2 C C Bank 1 l l 0 2 1 o o C C l l 3 M o o Row 0 Row N Row 1 Row 2 C C Bank 2 l l 0 2 1 o o l l l l Row N Row 2 Row 0 Row 1 Bank P 0123 M C C l l 3 M o o o C o C o C o C Peripheral Architecture www.
Command/Data Scheduler Command FIFO W rite FIFO Read FIFO Registers Command to Memory W rite Data to Memory Read Data from Memory Command Data EDMA BUS www.
Peripheral Architecture www.ti.com Next, the DDR2 memory controller examines each of the commands selected by the individual masters and performs the following reordering: • Among all pending reads, selects reads to rows already open. Among all pending writes, selects writes to rows already open.
www.ti.com Peripheral Architecture 2.7.3 Possible Race Condition A race condition may exist when certain masters write data to the DDR2 memory controller.
Peripheral Architecture www.ti.com 2.9 Self-Refresh Mode Setting the self refresh (SR) bit in the SDRAM refresh control register (SDRFC) to 1 forces the DDR2 memory controller to place the external DDR2 SDRAM in a low-power mode (self refresh), in which the DDR2 SDRAM maintains valid data while consuming a minimal amount of power.
www.ti.com Peripheral Architecture • Following a write to the two least-significant bytes in the SDRAM configuration register (SDCFG); see Section 2.11.3 . At the end of the initialization sequence, the DDR2 memory controller performs an auto-refresh cycle, leaving the DDR2 memory controller in an idle state with all banks deactivated.
Peripheral Architecture www.ti.com 2.11.2 DDR2 SDRAM Initialization After Reset After a hard or a soft reset, the DDR2 memory controller will automatically start the initialization sequence.
www.ti.com Using the DDR2 Memory Controller 3 Using the DDR2 Memory Controller The following sections show various ways to connect the DDR2 memory controller to DDR2 memory devices. The steps required to configure the DDR2 memory controller for external memory access are also described.
DDR2CLKOUT DDR2CLKOUT DSDCKE DCE0 DSDWE DSDRAS DSDCAS DSDDQM0 DSDDQM1 DSDDQS0 DSDDQS1 DBA[2:0] DEA[13:0] DED[15:0] ODT0 DSDDQS0 DSDDQS1 CK CK CKE CS WE RAS CAS LDM LDQS UDQS BA[2:0] A[12:0] DQ[15:0] O.
DDR2CLKOUT DDR2CLKOUT DSDCKE DCE0 DSDWE DSDRAS DSDCAS DSDDQM0 DSDDQM1 DSDDQS0 DSDDQS1 DBA[2:0] DEA[13:0] DED[15:0] V REFSSTL ODT0 DSDDQS0 DSDDQS1 CK CK CKE CS WE RAS CAS LDM UDM LDQS UDQS BA[2:0] A[12.
DDR2CLKOUT DDR2CLKOUT DSDCKE DCE0 DSDWE DSDRAS DSDCAS DSDDQM0 DSDDQM1 DSDDQS0 DSDDQS1 DBA[2:0] DEA[13:0] DED[7:0] V REFSSTL ODT0 DSDDQS0 DSDDQS1 CK CK CKE CS WE RAS CAS DM DQS RDQS BA[2:0] A[13:0] DQ[.
www.ti.com Using the DDR2 Memory Controller 3.2 Configuring DDR2 Memory Controller Registers to Meet DDR2 SDRAM Specifications The DDR2 memory controller allows a high degree of programmability for shaping DDR2 accesses. This provides the DDR2 memory controller with the flexibility to interface with a variety of DDR2 devices.
Using the DDR2 Memory Controller www.ti.com Table 12 displays the DDR2-533 refresh rate specification. Table 12. DDR2 Memory Refresh Specification Symbol Description Value t REF Average Periodic Refresh Interval 7.8 μ s Therefore, the value for the REFRESH-RATE can be calculated as follows: REFRESH_RATE = 250 MHz × 7.
www.ti.com Using the DDR2 Memory Controller Table 15. SDTIM2 Configuration DDR2 SDRAM Data Register Field Sheet Parameter Data Sheet Formula (Register Field Name Name Description Value Field Must Be ≥ ) Value T_ODT t AOND t AOND specifies the ODT turn-on 2 (t CK cycles) t AOND 2 delay T_XSNR t XSNR Exit self refresh to a non-read 137.
DDR2 Memory Controller Registers www.ti.com 4 DDR2 Memory Controller Registers Table 17 lists the memory-mapped registers for the DDR2 memory controller.
www.ti.com DDR2 Memory Controller Registers 4.1 Module ID and Revision Register (MIDR) The Module ID and Revision register (MIDR) is shown in Figure 19 and described in Table 18 .
DDR2 Memory Controller Registers www.ti.com 4.2 DDR2 Memory Controller Status Register (DMCSTAT) The DDR2 memory controller status register (DMCSTAT) is shown in Figure 20 Figure 20.
www.ti.com DDR2 Memory Controller Registers 4.3 SDRAM Configuration Register (SDCFG) The SDRAM configuration register (SDCFG) contains fields that program the DDR2 memory controller to meet the specification of the DDR2 memory.
DDR2 Memory Controller Registers www.ti.com Table 20. SDRAM Configuration Register (SDCFG) Field Descriptions (continued) Bit Field Value Description 11-9 CL CAS latency. The value of this field defines the CAS latency, to be used when accessing connected SDRAM devices.
www.ti.com DDR2 Memory Controller Registers 4.4 SDRAM Refresh Control Register (SDRFC) The SDRAM refresh control register (SDRFC) is used to configure the DDR2 memory controller to: • Enter and Exit the self-refresh state.
DDR2 Memory Controller Registers www.ti.com 4.5 SDRAM Timing 1 Register (SDTIM1) The SDRAM timing 1 register (SDTIM1) configures the DDR2 memory controller to meet many of the AC timing specification of the DDR2 memory. Note that DDR2CLKOUT is equal to the period of the DDR2CLKOUT signal.
www.ti.com DDR2 Memory Controller Registers Table 22. SDRAM Timing 1 Register (SDTIM1) Field Descriptions (continued) Bit Field Value Description 5-3 T_RRD These bits specify the minimum number of DDR2CLKOUT cycles from an activate command to an activate command in a different bank, minus 1.
DDR2 Memory Controller Registers www.ti.com 4.6 SDRAM Timing 2 Register (SDTIM2) Like the SDRAM timing 1 register (SDTIM1), the SDRAM timing 2 register (SDTIM2) also configures the DDR2 memory controller to meet the AC timing specification of the DDR2 memory.
www.ti.com DDR2 Memory Controller Registers 4.7 Burst Priority Register (BPRIO) The Burst Priority Register (BPRIO) helps prevent command starvation within the DDR2 memory controller.
DDR2 Memory Controller Registers www.ti.com 4.8 DDR2 Memory Controller Control Register (DMCCTL) The DDR2 memory controller control register (DMCCTL) resets the interface logic of the DDR2 memory controller. The DMCCTL is shown in Figure 26 and described in Table 25 .
www.ti.com Revision History Revision History This revision history highlights the technical changes made to the document in this revision. See Additions/Modifications/Deletions Table 1 Modified Descri.
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