Intelメーカー273246-002の使用説明書/サービス説明書
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Celeron™ Processor Development Kit Manual July 1999 Order N umber: 27 3246-00 2.
Celeron™ Proces sor Devel opment Ki t Man ual Informati on in this do cumen t is provided in connection with Intel products . No licens e, express or imp lied, by estoppel o r othe rwise, to any intellectua l property rights i s grante d by thi s docume nt.
Celeron™ Proce ssor Developm ent Kit M anual iii Contents 1 About This Manual .................. ............. ............ ............. ............. ............. ................ 1-1 1.1 Content O verview .. ............. ............. .........
iv Celeron™ Proces sor Devel opment Ki t Man ual 3.2.19 Post Code Debug ger ......... ............ ............. .................... ............. ...... 3-6 3.2.20 Clock Generation.. ...... ............. ...... ............. ....... ...... .......
Celeron™ Proce ssor Developm ent Kit M anual v 5.10.1 Console R edirect ion ....... ................... ............. ............. ............. ......... 5-9 5.10.2 CE-Ready W indows CE Loader ........ ............. ............. ............. ...
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Celeron™ Proce ssor Developm ent Kit M anual 1-1 About This Manual 1 This manual tel ls yo u how t o set up and us e t he evaluat ion board and pr oces sor assembl y incl u ded in your Celeron ™ Processor Developmen t Kit.
1-2 Celeron™ Proce ssor Deve lopment Ki t Manual About This Manua l 1.3 T echnical Support 1.3.1 Electronic Suppor t Systems Intel’ s site o n the World Wi de W eb (http ://www .intel.com /) prov id es up-to-date techn ical informat ion and p roduct support.
Celeron™ Proce ssor Developm ent Kit M anual 1-3 About Thi s Manual 1.3.1.2 Intel Product Forums Intel provides technical expertise through electronic messaging.
1-4 Celeron™ Proce ssor Deve lopment Ki t Manual About This Manua l 1.5 R elated Docum ents T able 1 - 1. Related Documents Document Tit le Order Number Inte l ® Celeron™ Processor datasheet 2436.
Celeron™ Proce ssor Developm ent Kit M anual 2-1 Getting Started 2 This chapter identifies the Developm ent Kit’ s key components, features and specification s, and tells you ho w to set up th e bo ard for operation. 2.1 Overview The evaluation board co nsists of a baseboar d and a processor assembly .
2-2 Celeron™ Proce ssor Deve lopment Ki t Manual Getting S tarted 2.1.2 Baseboard Features The baseboard has these features: • Flash system BIOS ROM — General Software system BIOS — In- circuit BIOS upg radab ility • T wo SDRAM DIMM connectors • 32-Mbyte SDRAM DIMM included — 4 Mbyte x64, 3.
Celeron™ Proce ssor Developm ent Kit M anual 2-3 Gett ing St arted 2.3 Software Key Featur es The software in t he kit was chosen to facilitate developmen t of real-time appl ications b ased on th e components used in th e evaluation bo ard. The softwar e tools included in you r kit are described in this section.
2-4 Celeron™ Proce ssor Deve lopment Ki t Manual Getting S tarted 2.3.2 QNX Software Systems, Ltd. QNX Real Time Operating System for Intel Architecture.
Celeron™ Proce ssor Developm ent Kit M anual 2-5 Gett ing St arted 2.5 Setting up th e Evaluation Board Once you have gathered t he hardware desc ribed in the las t section, fo llow the steps below to set up your evaluation board.
2-6 Celeron™ Proce ssor Deve lopment Ki t Manual Getting S tarted 3. Make sure the board’ s jumpers are set to the following default location s. • J14 - Not ins talled • J15 - I nstalle d • J20 - Jump er pin s 2- 3 • J21 - Jump er pin s 2- 3 • J22 - Jump er pin s 2- 3 • J23 - Jump er pin s 2- 3 • J24 - Jump er pin s 1- 2 4.
Celeron™ Proce ssor Developm ent Kit M anual 2-7 Gett ing St arted — Y ou may have to make changes to the system BIOS to enable this hard disk. See Chapter 5, “BIOS Quick Reference” for mo re information . • Floppy drive: A floppy disk dri ve connected to the ev aluation board is the most d irect method for loadin g software.
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Celeron™ Proce ssor Developm ent Kit M anual 3-1 Theory of Operation 3 3.1 Block Diagram Figure 3-1. Evaluation Board Block Dia gram Celeron™ Processor Sensor PIIX4E DRAM Bus ITP V oltage Regulato.
3-2 Celeron™ Proce ssor Deve lopment Ki t Manual Theory of O peration 3.2 Sys tem Operatio n The Celeron™ pro cessor evaluation boar d is a full-f eatured system board and processor assembly .
Celeron™ Proce ssor Developm ent Kit M anual 3-3 Theory of O peration 3.2. 2.1 Syste m Bus I nter f ac e The 82443B X support s a maxim um of 4 Gbyt es of memor y address space fro m the proces sor perspectiv e. The lar gest address size is 32 bits.
3-4 Celeron™ Proce ssor Deve lopment Ki t Manual Theory of O peration 3.2.4 82371EB PCI to ISA/ IDE Xcelerator ( PIIX4E) The 82443BX is design ed to sup port the PIIX4 E I/O br idge. The P IIX4E is a highly-int egrated multifunction a l co mponent that supp o rts the following: • PCI Revi sion 2.
Celeron™ Proce ssor Developm ent Kit M anual 3-5 Theory of O peration 3.2.10 IDE Support The evaluation boar d supports bo th a primary and secondary I DE interface via two 4 0-pin IDE connectors. The connector labeled I DE1 is the primary interface.
3-6 Celeron™ Proce ssor Deve lopment Ki t Manual Theory of O peration 3.2.19 Post Code Debugger The evaluat ion board has an on- board Post Code Debugger . Data from any program that does an I/O write to 0080H is l atched and d isplaye d on the two LEDs (U12 and U1 3).
Celeron™ Proce ssor Developm ent Kit M anual 3-7 Theory of O peration 3.2.22 Memory Map T abl e 3-2. Memory Map Address Range (Hex) Size Description 100000-8000000 127.
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Celeron™ Proce ssor Developm ent Kit M anual 4-1 Hardware Reference 4 This section pro vides reference informatio n on the syst em desig n. Included in this s ection is connector pinout informati on, jump er settin gs, and other s ystem des ign in formatio n.
4-2 Celeron™ Proce ssor Deve lopment Ki t Manual Hardware Reference 4.3 ISA and PCI Expansion Slots The evaluation platform has three PCI expansion slots and two ISA slots. 4.4 PCI Device Map ping On the evaluation platform the PCI devices are mapp ed to PCI dev ice numbers b y connecting an address line to the IDSEL signal of each PCI device.
Celeron™ Proce ssor Developm ent Kit M anual 4-3 Hardware R eference 4.5 Con nect or P ino uts 4.5.1 A TX Power C onnector T able 4-2 shows the signals assigned to the ATX style power conn ector . T abl e 4-2. Primary Power Connector (J1 1 ) Pin Name Function 1 3.
4-4 Celeron™ Proce ssor Deve lopment Ki t Manual Hardware Reference 4.5.2 ITP Debugger Connector 4.5.3 Stacked USB P0 is the bo ttom connecto r . P1 is on to p.
Celeron™ Proce ssor Developm ent Kit M anual 4-5 Hardware R eference 4.5.4 Mouse and Keyboard Connectors The keyboard port is on top . The mou se port is o n the bot tom.
4-6 Celeron™ Proce ssor Deve lopment Ki t Manual Hardware Reference 4.5.6 Serial Ports COM1 is the top conn ector . COM2 is th e bo ttom connector . 4.5.7 IDE Co nnector T able 4 -7. Serial Port Connector Pinout (J4) Pin Signal Name 1 DCD 2 S erial In (SIN) 3 Serial Out (SOUT) 4D T R 5G N D 6D S R 7R T S 8C T S 9R I T able 4 -8.
Celeron™ Proce ssor Developm ent Kit M anual 4-7 Hardware R eference 4.5.8 Floppy Drive Connector T able 4-9. Disket te Drive He ader Connector (JP 1) Pin Signal Name Pin Signal Name 1 Ground 2 FDHD.
4-8 Celeron™ Proce ssor Deve lopment Ki t Manual Hardware Reference 4.5.9 PCI Slot Connector T able 4-10 . PC I Slo ts ( J7, J 8, J9) Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name A1 VCC B1 - 12V A32 AD16 B32 AD17 A2 + 12V B2 GND A33 3.
Celeron™ Proce ssor Developm ent Kit M anual 4-9 Hardware R eference 4.5.10 ISA Sl ot Connector T abl e 4-1 1. ISA Slots (J5, J6) Pin Signal Name Pin Signal Name P in Signal Name Pin Signal Nam e A1.
4-10 Celeron™ Proce ssor Deve lopment Ki t Manual Hardware Reference 4.6 AGP C onnector T able 4- 12. AGP Slot (J13) P i n # BA P i n # BA 1 OVRCNT# 12V 34 Vddq3.3 Vddq3.3 2 5.0V TYPEDET# 35 AD21 AD22 3 5.0V Reserved 36 AD19 AD20 4 USB+ U SB- 37 GND GND 5 GND GND 38 AD17 AD18 6 INTB# INT A # 39 C/BE2# AD16 7 CLK RST# 40 Vddq3.
Celeron™ Proce ssor Developm ent Kit M anual 4-11 Hardware R eference 4.7 Jum per s T able 4-13 shows default Ju mper sett i ngs . 4.7.1 Enable Spread Spectrum Clocking (J 14) This jumper is used to enable o r disable spread spectrum clock ing on the clock syn thesizer .
4-12 Celeron™ Proce ssor Deve lopment Ki t Manual Hardware Reference 4.7.4 Flash BIOS VPP Se lect (J 21) This jumper controls the vo ltage presented to the flash BI OS VPP pin. The 2-3 position sup plies 5 V and is the defau lt for no rmal o peratio n.
Celeron™ Proce ssor Developm ent Kit M anual 4-13 Hardware R eference 4.8 In-Circuit BIOS Update The BIOS can be up graded in-circuit. B IOS updates may pe riodically be posted to Intel’ s Developers’ site at http:// www .intel.com /des ign/. To r e p r o g r a m t h e B I O S : 1.
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Celeron™ Proce ssor Developm ent Kit M anual 5-1 BIOS Quick Reference 5 The Celeron pr ocessor evaluation b oard is licensed with a single cop y of Embedd ed BIOS and Embedded DOS softwar e from General Software, Inc. 1 This s oftware is provid ed for demonstrat ion purpos es only and mus t be licens ed directl y from General Software, Inc.
5-2 Celeron™ Proce ssor Deve lopment Ki t Manual BIOS Quic k Referen ce When the system is powered on for the first time, you’ll need to con figure the system through the Setup Screen System (described later) before peripherals, such as disk drives, are recog nized by the BIOS.
Celeron™ Proce ssor Developm ent Kit M anual 5-3 BIOS Qu ick Refe rence 5.3 Setup Screen System The system is configured from within the Setup Screen System, which is a series of menus that can be i.
5-4 Celeron™ Proce ssor Deve lopment Ki t Manual BIOS Quic k Referen ce 5.3.2 Config uring Drive Assignm ents Embedded BIOS allows the user to map a dif ferent file system to each drive letter .
Celeron™ Proce ssor Developm ent Kit M anual 5-5 BIOS Qu ick Refe rence 5.3.3 Configuring IDE Drive T ypes If true IDE disk file systems (and not their emu lators, such as ROM, RAM, or flash di sks) are mapped to drive letter s, then the IDE dr ives themselves must be configured in this section.
5-6 Celeron™ Proce ssor Deve lopment Ki t Manual BIOS Quic k Referen ce 5.4 Con figuring Boo t Actions Embedded BIOS s upports up to si x dif ferent us er -defined steps in th e boot s equence. Wh en the entire system has b een initialized, POS T executes these steps in order until an operating sy stem successfully loads.
Celeron™ Proce ssor Developm ent Kit M anual 5-7 BIOS Qu ick Refe rence 5.6 Shadow Conf iguration Setu p Screen The system’ s Shadow Configuration Setup Screen ( Figure 5-5) allows the selective enabling and disabling of shad owing in 16 Kbyte secti ons, except f or the t op 64 Kbyt es of th e BIOS ROM, which is shadowed as a unit.
5-8 Celeron™ Proce ssor Deve lopment Ki t Manual BIOS Quic k Referen ce 5.7 Standard Diag nostics R outines Setup Screen Embedded s ystems may require aut omated burn-in testing in the d evelopment cycle. This facility is provided directly in the system’ s system BIOS through the Standard Diagnostics Routines Setup Screen (Figure 5-6).
Celeron™ Proce ssor Developm ent Kit M anual 5-9 BIOS Qu ick Refe rence 5.9 Start RS232 Manufacturing L ink Setup Screen The Embedded B IOS Manufacturi ng Mode may be invok ed from th e Setup S creen main me nu, as well as a boot activity .
5-10 Celeron™ Proce ssor Deve lopment Ki t Manual BIOS Quic k Referen ce The software on the tar get can be any terminal emulation prog ram that suppo rts ANSI terminal mode, using 9600 bau d, no parity , and one stop bit (Note: This can be modified by the OEM during BIOS adaptation.
Celeron™ Proce ssor Developm ent Kit M anual 5-11 BIOS Qu ick Refe rence T o activate the debugger at an y time from th e main console, press the left shift and the contro l keys together .
5-12 Celeron™ Proce ssor Deve lopment Ki t Manual BIOS Quic k Referen ce A complete d iscu ssion of t he debu gger is beyond the scope o f this chapter; however , complet e documentation is available fro m General Software via th e web at http://www .
Celeron™ Proce ssor Developm ent Kit M anual 5-13 BIOS Qu ick Refe rence POST_STATUS_VIDEOROM 2ch Passing control to video ROM. POST_STATUS_POSTVIDEO 2dh Control returned from video ROM. POST_STATUS_CHECKEGAVGA 2eh Check for EGA/VGA adapter. POST_STATUS_TESTVIDEOMEMORY 2fh No EGA/VGA found, test video memory.
5-14 Celeron™ Proce ssor Deve lopment Ki t Manual BIOS Quic k Referen ce POST_STATUS_BEFORESETUP 86h Password accepted. POST_STATUS_CALLSETUP 87h Entering setup system. POST_STATUS_POSTSETUP 88h Setup system exited. POST_STATUS_DISPPWRON 89h Display power-on screen message.
Celeron™ Proce ssor Developm ent Kit M anual 5-15 BIOS Qu ick Refe rence 5.12 Emb edded B IOS Beep Co des Embedded BIOS tests much of the system hardware early in POST before messages can be displayed on the screen.
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Celeron™ Proce ssor Developm ent Kit M anual A-1 PLD Code Listing A The code listing below is for the 22V10 PLD. TITLE 22V10 PORT 80 ADDRESS DECODER / FLASH DECODE PATTERN 1 REVISION B AUTHOR CHRIS .
A-2 Celeron™ Proce ssor Deve lopment Ki t Manual PLD Code Li sting SETF AEN /IOWR_BAR SETF /AEN SETF IOWR_BAR SETF SA0 /IOWR_BAR SETF /SA0 /IOWR_BAR SETF IOWR_BAR SETF /SA0 /SA1 /SA2 /SA3 /SA4 /SA5 .
Celeron™ Proce ssor Developm ent Kit M anual B-1 Bill of Materials B T a b le B-1 is the bill of mate rials for th e baseboard. T able B-2 is the bill o f materials for the Proces sor A ssemb ly .
B-2 Celeron™ Proce ssor Deve lopment Ki t Manual Bill of Materi als U1 1 BIOS FLA SH Memory ,TSOP12X20/40S INTEL 28F002BC U8 VLSI ,PII X4, PCI t o I DE &I SA Bridge,324 mBGA,BGA20x20- 324 Intel .
Celeron™ Proce ssor Developm ent Kit M anual B-3 Bill of Material s R33,R35,R37,R48,R52,R9 8-R100, R106,R108- R1 16,R1 18-R122 Chip Resistor ,0 Ohm Shunt,5%,CR0805 Panasonic ERJ6GE Y0R00V DO NOT POP.
B-4 Celeron™ Proce ssor Deve lopment Ki t Manual Bill of Materi als XBT1 Battery Holder Socket Renata HU-2032-1 BT1 Battery Reneta CR2032 D1,D2,D5 Diode,LED,SO T23-A Siemens LGS260-D O U1 VLSI,Super.
Celeron™ Proce ssor Developm ent Kit M anual B-5 Bill of Material s T abl e B-2. Celer on™ Processor Assembly Bil l of Materials (Sheet 1 of 2) Reference Descriptions Manufacturer Manufacturer P/N C1 CAP 20 pF 25V CC0603 Panasonic ECU-V1H200JCM C1 17 CAP 4700pF 50V CC0603 Panasonic ECJ-1VB 1H472K C84-C85, C94-C98 CAP 0.
B-6 Celeron™ Proce ssor Deve lopment Ki t Manual Bill of Materi als R75,R73 Resistor 47K CR0805 P anasonic ERJ-6GEY J472V R55,R56 Resistor 75 1% CR0805 P anasonic ERJ-6ENF07 50V R60 Resistor 100 1% .
Celeron™ Proce ssor Developm ent Kit M anual C-1 Schematics C The most current schematics, includ ing “flat” sch ematics (without the 400-pin connector), are located on Intel’ s Devel oper W eb sit e at: http://www .intel.co m /design/i ntarch/schems/.
5 5 4 4 3 3 2 2 1 1 D D C C B B A A 1. Swapped AD23 and AD19 on 400 pin co n nector. 2. Separated CSEL on IDE0 and IDE1 3. Swapped pins 1 and 3 (V5 with TP) on CPU-Fan c onnector. 4. Tied VBAT (pin 65) to 5.0V on Su p er I/O. 5. Changed RP48 to 4.7K. (Pullups for mouse and k eyboard.
A A B B C C D D E E 4 4 3 3 2 2 1 1 DRAM (DIMM) Page 5,6,7 PIIX4 Page 13,14 PCI Connectors Page 10,11 Super I/O Page 16 Flash Bios Port 80 Page 20 ISA Connectors Page 18 PCI BUS ISA BUS CPU Module Con.
A A B B C C D D E E 4 4 3 3 2 2 1 1 THIS DRAWING CONTAINS INFORMATION WHICH HA S NOT BEEN VERIFIED FOR MANUFACTURING AS AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATIO N.
A A B B C C D D E E 4 4 3 3 2 2 1 1 Note:GFBCLK must be 3.0" longer than GCKOUT THIS DRAWING CONTAINS INFORMATION WHICH HA S NOT BEEN VERIFIED FOR MANUFACTURING AS AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATIO N.
A A B B C C D D E E 4 4 3 3 2 2 1 1 Slave address 10100000b Socket 0 THIS DRAWING CONTAINS INFORMATION WHICH HA S NOT BEEN VERIFIED FOR MANUFACTURING AS AN END USER PRODUCT.
A A B B C C D D E E 4 4 3 3 2 2 1 1 Slave address 10100001b Socket 1 THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AS AN END U SER PRODUCT.
A A B B C C D D E E 4 4 3 3 2 2 1 1 Slave address 10100010b Socket 2 Note: J16 is not popula ted THIS DRAWING CONTAINS INFORMATION WHICH HA S NOT BEEN VERIFIED FOR MANUFACTURING AS AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATIO N.
A A B B C C D D E E 4 4 3 3 2 2 1 1 Stuff only to enable stopping of clocks This circuit is only used for TX/Pentium Designs. Note only two DIMMS are supported. This circuit is only used for BX/PentiumII Designs. Note three DIMMS are supported. These caps can be tuned to change delay through buffer.
A A B B C C D D E E 4 4 3 3 2 2 1 1 ISA Pullup s PCI Pullu ps Note IRQ8 Pull-up is on PIIX4 page THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AS AN END U SER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATIO N.
A A B B C C D D E E 4 4 3 3 2 2 1 1 PCI SLOT 0 PCI SLOT 1 J7/J8 V5_ 0: A5, A8, A10, A16, A59, A61, A62 | A1, A3, A4 B5, B6, B19, B22, B59, B61, B62 J7/J8 V3_ 3: A21, A27, A33, A39 A45, A53 B25, B31, B.
A A B B C C D D E E 4 4 3 3 2 2 1 1 PCI SLOT 2 THIS DRAWING CONTAINS INFORMATION WHICH HA S NOT BEEN VERIFIED FOR MANUFACTURING AS AN END USER PRODUCT.
A A B B C C D D E E 4 4 3 3 2 2 1 1 Stub length from connector to resistor must be less than 0.1" Pin A3 is tied to ground per AGP Specification Rev 1.0 THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AS AN END U SER PRODUCT.
A A B B C C D D E E 4 4 3 3 2 2 1 1 PIIX4 is PCI device #8 This circuit is to prevent IOAPIC from being powered by IRQ#8 when in suspend and power is not applied to device. Note: U14, C203,C215, C210 , R50 and R51 are not popula ted THIS DRAWING CONTAINS INFORMATION WHICH HA S NOT BEEN VERIFIED FOR MANUFACTURING AS AN END USER PRODUCT.
A A B B C C D D E E 4 4 3 3 2 2 1 1 CPU Module must drive CONFIG1l to indicate processor type. 3.3V = PentiumII 0V = Pentium 1-2 Normal Operation 2-3 Clear CMOS Keep crystal close to PIIX4 and caps close to crystal Trace lengths should be equal THIS DRAWING CONTAINS INFORMATION WHICH HA S NOT BEEN VERIFIED FOR MANUFACTURING AS AN END USER PRODUCT.
A A B B C C D D E E 4 4 3 3 2 2 1 1 Primary IDE Connect or Secondary IDE Connect or HD Active LED THIS DRAWING CONTAINS INFORMATION WHICH HA S NOT BEEN VERIFIED FOR MANUFACTURING AS AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATIO N.
A A B B C C D D E E 4 4 3 3 2 2 1 1 PULL romCs# high so as not to interfere with boot rom! Install for 370 Config address Install for 3F0 Config address Do not stuff Install only one resistor! This disables the ROM buffers.
A A B B C C D D E E 4 4 3 3 2 2 1 1 NOTE 1: USB differential traces route together (Z0- & Z0+) and (Z1- & Z1+). Must be 45 Ohm Matched Stripline width 0.015 (for 1 oz)->44.88/45.45 Ohm. 8Ohm/100MHz/500mA 8Ohm/100MHz/500mA PCB Trace 45 Ohm Matched, Routed Together Stripline width 0.
A A B B C C D D E E 4 4 3 3 2 2 1 1 ISA Slots J5/J6 V5_ 0: B03, B29, B3 1, D16 J5/J6 GN D: B01, B10, D18 J5/J6: +12V B09 -12V B07 -5V B05 Note Cap Direc tion Note Cap Direc tion THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AS AN END U SER PRODUCT.
A A B B C C D D E E 4 4 3 3 2 2 1 1 COM0/COM1 FLOPPY PARALLEL COM1 COM0 THIS DRAWING CONTAINS INFORMATION WHICH HA S NOT BEEN VERIFIED FOR MANUFACTURING AS AN END USER PRODUCT.
A A B B C C D D E E 4 4 3 3 2 2 1 1 Expect All 0's except SA7=1 for P80 Decode Standard Stuff Option Port 80 THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AS AN END U SER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATIO N.
A A B B C C D D E E 4 4 3 3 2 2 1 1 Note Cap Dire ction Power Indicator s SPEAKER HEADER Open Collec tor PS_OK = OR of PW_OK,-DBRESET,RESET SWITCH Note: Add screen marking for V5_0 LED, V3_3 LED Place.
A A B B C C D D E E 4 4 3 3 2 2 1 1 Make these connections Cutable Make these connections Cutable Make these connections Cutable Make these connections Cutable Make these connections Cutable Make these connections Cutable THIS DRAWING CONTAINS INFORMATION WHICH HA S NOT BEEN VERIFIED FOR MANUFACTURING AS AN END USER PRODUCT.
5 5 4 4 3 3 2 2 1 1 D D C C B B A A No license, express or implied, by estoppel or otherwise, to an y intellectual property rights is granted herein. Revision A1 THIS DRAWING CONTAINS INFOR MATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACT URING AS AN END USER PRODUCT.
5 5 4 4 3 3 2 2 1 1 D D C C B B A A Socket 370 Page 3&4 440BX Page 7&8 CPU Connector Page 9 GTL+ Termination Page 5 & 6 GTL+ ITP Bus Ratio Logic Thermal Sensor Page 10 Voltage Regulator Pa.
A A B B C C D D E E 4 4 3 3 2 2 1 1 THIS SCHEMATIC IS PROVIDED "AS IS" WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF PROPOSAL, SPECIFICATION OR SAMPLE.
A A B B C C D D E E 4 4 3 3 2 2 1 1 **REFERENCE VOLTAGE FOR P ROCESSOR. THERE ARE 8 VREF PINS. PLACE ONE CAPACITOR NEAR EVERY 2 VREF PINS. Make MREF as short and fat a s possible. Use at least 24 m ill line. THIS DRAWING CONTAINS INFORM ATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTU RING AS AN END USER PRODUCT.
5 5 4 4 3 3 2 2 1 1 D D C C B B A A GTL+ TERMINATION RESISTORS-BX THIS DRAWING CONTAINS INFOR MATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACT URING AS AN END USER PRODUCT. INTEL IS NOT R ESPONSIBLE FOR THE MISUSE OF THIS I NFORMATION. Resistor Packs placed for Dual End Termination.
5 5 4 4 3 3 2 2 1 1 D D C C B B A A Place one Cap near every two R-packs THIS DRAWING CONTAINS INFORM ATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTU RING AS AN END USER PRODUCT.
5 5 4 4 3 3 2 2 1 1 D D C C B B A A Place as cl ose as possible to B X Are these suppose to be 0.001uF? Note: PCI 5V THIS DRAWING CONTAINS INFORM ATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTU RING AS AN END USER PRODUCT. INTEL IS NOT RE SPONSIBLE FOR THE MISUSE OF THIS I NFORMATION.
5 5 4 4 3 3 2 2 1 1 D D C C B B A A Resistor Function Board De fault Setting R21 R22 R23 R24 R25 In-Order Queue Depth Enable. Quick Start Select AGP Dis able Memory Mo dule Configura tion Host Bus Buf.
5 5 4 4 3 3 2 2 1 1 D D C C B B A A AGP clock signals Layout: G_CLKIN,GCLKO_A+G_CLKOUT, GCLKO_B+G_CLKOUT should all be the same length Mounting Holes THIS DRAWING CONTAINS INFORM ATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTU RING AS AN END USER PRODUCT.
5 5 4 4 3 3 2 2 1 1 D D C C B B A A UNUSED GATES BUS RATIO SE L EC T FOR PR OCESSOR Address Select Straps Current Address: 1001 110 THE RM AL SENSOR THIS DRAWING CONTAINS INFOR MATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACT URING AS AN END USER PRODUCT.
5 5 4 4 3 3 2 2 1 1 D D C C B B A A GTL Reference Voltage Generator Place c lose to C S- /CS+ Place near pin 3 Place ar ound uProcessor Note: AGND must tie directly to nearest output CAP.
Celeron™ Proce ssor Developm ent Kit M anual Index-1 Index #, d efine d 1-1 440BX AGP set 3-2 82371EB PCI ISA IDE Xce lerator (PIIX4E) 2-1 , 3-4 82443BX Host Bridge/Controller 2-1 A Address siz e 3-.
Index-2 Celeron™ Proce ssor Deve lopment Ki t Manual J15, cl oc k frequen cy select ion 4-11 J20, on/ of f 4- 11 J21, flash BIOS VPP select 4-1 2 J22 , f l ash BIOS bo ot block cont rol 4-1 2 J23, S.
デバイスIntel 273246-002の購入後に(又は購入する前であっても)重要なポイントは、説明書をよく読むことです。その単純な理由はいくつかあります:
Intel 273246-002をまだ購入していないなら、この製品の基本情報を理解する良い機会です。まずは上にある説明書の最初のページをご覧ください。そこにはIntel 273246-002の技術情報の概要が記載されているはずです。デバイスがあなたのニーズを満たすかどうかは、ここで確認しましょう。Intel 273246-002の取扱説明書の次のページをよく読むことにより、製品の全機能やその取り扱いに関する情報を知ることができます。Intel 273246-002で得られた情報は、きっとあなたの購入の決断を手助けしてくれることでしょう。
Intel 273246-002を既にお持ちだが、まだ読んでいない場合は、上記の理由によりそれを行うべきです。そうすることにより機能を適切に使用しているか、又はIntel 273246-002の不適切な取り扱いによりその寿命を短くする危険を犯していないかどうかを知ることができます。
ですが、ユーザガイドが果たす重要な役割の一つは、Intel 273246-002に関する問題の解決を支援することです。そこにはほとんどの場合、トラブルシューティング、すなわちIntel 273246-002デバイスで最もよく起こりうる故障・不良とそれらの対処法についてのアドバイスを見つけることができるはずです。たとえ問題を解決できなかった場合でも、説明書にはカスタマー・サービスセンター又は最寄りのサービスセンターへの問い合わせ先等、次の対処法についての指示があるはずです。